rename.hh revision 1755
12914Ssaidi@eecs.umich.edu/* 28856Sandreas.hansson@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68856Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78856Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88856Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98856Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108856Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118856Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128856Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138856Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 142914Ssaidi@eecs.umich.edu * this software without specific prior written permission. 152914Ssaidi@eecs.umich.edu * 162914Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172914Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182914Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192914Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202914Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212914Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222914Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232914Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242914Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252914Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262914Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272914Ssaidi@eecs.umich.edu */ 282914Ssaidi@eecs.umich.edu 292914Ssaidi@eecs.umich.edu// Todo: 302914Ssaidi@eecs.umich.edu// Fix up trap and barrier handling. 312914Ssaidi@eecs.umich.edu// May want to have different statuses to differentiate the different stall 322914Ssaidi@eecs.umich.edu// conditions. 332914Ssaidi@eecs.umich.edu 342914Ssaidi@eecs.umich.edu#ifndef __CPU_O3_CPU_SIMPLE_RENAME_HH__ 352914Ssaidi@eecs.umich.edu#define __CPU_O3_CPU_SIMPLE_RENAME_HH__ 362914Ssaidi@eecs.umich.edu 372914Ssaidi@eecs.umich.edu#include <list> 382914Ssaidi@eecs.umich.edu 392914Ssaidi@eecs.umich.edu#include "base/statistics.hh" 402914Ssaidi@eecs.umich.edu#include "base/timebuf.hh" 418856Sandreas.hansson@arm.com 422914Ssaidi@eecs.umich.edu// Will need rename maps for both the int reg file and fp reg file. 432914Ssaidi@eecs.umich.edu// Or change rename map class to handle both. (RegFile handles both.) 448708Sandreas.hansson@arm.comtemplate<class Impl> 452914Ssaidi@eecs.umich.educlass SimpleRename 462914Ssaidi@eecs.umich.edu{ 478914Sandreas.hansson@arm.com public: 488914Sandreas.hansson@arm.com // Typedefs from the Impl. 498922Swilliam.wang@arm.com typedef typename Impl::ISA ISA; 505740Snate@binkert.org typedef typename Impl::CPUPol CPUPol; 515740Snate@binkert.org typedef typename Impl::DynInstPtr DynInstPtr; 525740Snate@binkert.org typedef typename Impl::FullCPU FullCPU; 534490Sstever@eecs.umich.edu typedef typename Impl::Params Params; 544490Sstever@eecs.umich.edu 554490Sstever@eecs.umich.edu typedef typename CPUPol::FetchStruct FetchStruct; 568914Sandreas.hansson@arm.com typedef typename CPUPol::DecodeStruct DecodeStruct; 578914Sandreas.hansson@arm.com typedef typename CPUPol::RenameStruct RenameStruct; 588914Sandreas.hansson@arm.com typedef typename CPUPol::TimeStruct TimeStruct; 593296Ssaidi@eecs.umich.edu 604929Sstever@gmail.com // Typedefs from the CPUPol 613091Sstever@eecs.umich.edu typedef typename CPUPol::FreeList FreeList; 623091Sstever@eecs.umich.edu typedef typename CPUPol::RenameMap RenameMap; 633091Sstever@eecs.umich.edu 643349Sbinkertn@umich.edu // Typedefs from the ISA. 653091Sstever@eecs.umich.edu typedef typename ISA::Addr Addr; 668922Swilliam.wang@arm.com 678922Swilliam.wang@arm.com public: 688922Swilliam.wang@arm.com // Rename will block if ROB becomes full or issue queue becomes full, 694670Sstever@eecs.umich.edu // or there are no free registers to rename to. 704670Sstever@eecs.umich.edu // Only case where rename squashes is if IEW squashes. 714670Sstever@eecs.umich.edu enum Status { 724670Sstever@eecs.umich.edu Running, 734670Sstever@eecs.umich.edu Idle, 744670Sstever@eecs.umich.edu Squashing, 754670Sstever@eecs.umich.edu Blocked, 764626Sstever@eecs.umich.edu Unblocking, 773091Sstever@eecs.umich.edu BarrierStall 783175Srdreslin@umich.edu }; 794626Sstever@eecs.umich.edu 804670Sstever@eecs.umich.edu private: 814670Sstever@eecs.umich.edu Status _status; 824626Sstever@eecs.umich.edu 838914Sandreas.hansson@arm.com public: 844626Sstever@eecs.umich.edu SimpleRename(Params ¶ms); 854490Sstever@eecs.umich.edu 863309Srdreslin@umich.edu void regStats(); 874670Sstever@eecs.umich.edu 883091Sstever@eecs.umich.edu void setCPU(FullCPU *cpu_ptr); 893091Sstever@eecs.umich.edu 90 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 91 92 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 93 94 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 95 96 void setRenameMap(RenameMap *rm_ptr); 97 98 void setFreeList(FreeList *fl_ptr); 99 100 void dumpHistory(); 101 102 void tick(); 103 104 void rename(); 105 106 void squash(); 107 108 private: 109 void block(); 110 111 inline void unblock(); 112 113 void doSquash(); 114 115 void removeFromHistory(InstSeqNum inst_seq_num); 116 117 inline void renameSrcRegs(DynInstPtr &inst); 118 119 inline void renameDestRegs(DynInstPtr &inst); 120 121 inline int calcFreeROBEntries(); 122 123 inline int calcFreeIQEntries(); 124 125 /** Holds the previous information for each rename. 126 * Note that often times the inst may have been deleted, so only access 127 * the pointer for the address and do not dereference it. 128 */ 129 struct RenameHistory { 130 RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, 131 PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) 132 : instSeqNum(_instSeqNum), archReg(_archReg), 133 newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg), 134 placeHolder(false) 135 { 136 } 137 138 /** Constructor used specifically for cases where a place holder 139 * rename history entry is being made. 140 */ 141 RenameHistory(InstSeqNum _instSeqNum) 142 : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0), 143 prevPhysReg(0), placeHolder(true) 144 { 145 } 146 147 InstSeqNum instSeqNum; 148 RegIndex archReg; 149 PhysRegIndex newPhysReg; 150 PhysRegIndex prevPhysReg; 151 bool placeHolder; 152 }; 153 154 std::list<RenameHistory> historyBuffer; 155 156 /** CPU interface. */ 157 FullCPU *cpu; 158 159 // Interfaces to objects outside of rename. 160 /** Time buffer interface. */ 161 TimeBuffer<TimeStruct> *timeBuffer; 162 163 /** Wire to get IEW's output from backwards time buffer. */ 164 typename TimeBuffer<TimeStruct>::wire fromIEW; 165 166 /** Wire to get commit's output from backwards time buffer. */ 167 typename TimeBuffer<TimeStruct>::wire fromCommit; 168 169 /** Wire to write infromation heading to previous stages. */ 170 // Might not be the best name as not only decode will read it. 171 typename TimeBuffer<TimeStruct>::wire toDecode; 172 173 /** Rename instruction queue. */ 174 TimeBuffer<RenameStruct> *renameQueue; 175 176 /** Wire to write any information heading to IEW. */ 177 typename TimeBuffer<RenameStruct>::wire toIEW; 178 179 /** Decode instruction queue interface. */ 180 TimeBuffer<DecodeStruct> *decodeQueue; 181 182 /** Wire to get decode's output from decode queue. */ 183 typename TimeBuffer<DecodeStruct>::wire fromDecode; 184 185 /** Skid buffer between rename and decode. */ 186 std::queue<DecodeStruct> skidBuffer; 187 188 /** Rename map interface. */ 189 SimpleRenameMap *renameMap; 190 191 /** Free list interface. */ 192 FreeList *freeList; 193 194 /** Delay between iew and rename, in ticks. */ 195 int iewToRenameDelay; 196 197 /** Delay between decode and rename, in ticks. */ 198 int decodeToRenameDelay; 199 200 /** Delay between commit and rename, in ticks. */ 201 unsigned commitToRenameDelay; 202 203 /** Rename width, in instructions. */ 204 unsigned renameWidth; 205 206 /** Commit width, in instructions. Used so rename knows how many 207 * instructions might have freed registers in the previous cycle. 208 */ 209 unsigned commitWidth; 210 211 /** The instruction that rename is currently on. It needs to have 212 * persistent state so that when a stall occurs in the middle of a 213 * group of instructions, it can restart at the proper instruction. 214 */ 215 unsigned numInst; 216 217 Stats::Scalar<> renameSquashCycles; 218 Stats::Scalar<> renameIdleCycles; 219 Stats::Scalar<> renameBlockCycles; 220 Stats::Scalar<> renameUnblockCycles; 221 Stats::Scalar<> renameRenamedInsts; 222 Stats::Scalar<> renameSquashedInsts; 223 Stats::Scalar<> renameROBFullEvents; 224 Stats::Scalar<> renameIQFullEvents; 225 Stats::Scalar<> renameFullRegistersEvents; 226 Stats::Scalar<> renameRenamedOperands; 227 Stats::Scalar<> renameRenameLookups; 228 Stats::Scalar<> renameHBPlaceHolders; 229 Stats::Scalar<> renameCommittedMaps; 230 Stats::Scalar<> renameUndoneMaps; 231 Stats::Scalar<> renameValidUndoneMaps; 232}; 233 234#endif // __CPU_O3_CPU_SIMPLE_RENAME_HH__ 235