rename.hh revision 12109
11689SN/A/*
29444SAndreas.Sandberg@ARM.com * Copyright (c) 2012 ARM Limited
39444SAndreas.Sandberg@ARM.com * All rights reserved
49444SAndreas.Sandberg@ARM.com *
59444SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall
69444SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual
79444SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating
89444SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software
99444SAndreas.Sandberg@ARM.com * licensed hereunder.  You may use the software subject to the license
109444SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated
119444SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software,
129444SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form.
139444SAndreas.Sandberg@ARM.com *
142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan
1510239Sbinhpham@cs.rutgers.edu * Copyright (c) 2013 Advanced Micro Devices, Inc.
161689SN/A * All rights reserved.
171689SN/A *
181689SN/A * Redistribution and use in source and binary forms, with or without
191689SN/A * modification, are permitted provided that the following conditions are
201689SN/A * met: redistributions of source code must retain the above copyright
211689SN/A * notice, this list of conditions and the following disclaimer;
221689SN/A * redistributions in binary form must reproduce the above copyright
231689SN/A * notice, this list of conditions and the following disclaimer in the
241689SN/A * documentation and/or other materials provided with the distribution;
251689SN/A * neither the name of the copyright holders nor the names of its
261689SN/A * contributors may be used to endorse or promote products derived from
271689SN/A * this software without specific prior written permission.
281689SN/A *
291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402665Ssaidi@eecs.umich.edu *
412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
421689SN/A */
431689SN/A
442292SN/A#ifndef __CPU_O3_RENAME_HH__
452292SN/A#define __CPU_O3_RENAME_HH__
461060SN/A
471060SN/A#include <list>
4811246Sradhika.jagtap@ARM.com#include <utility>
491060SN/A
501461SN/A#include "base/statistics.hh"
518229Snate@binkert.org#include "config/the_isa.hh"
527813Ssteve.reinhardt@amd.com#include "cpu/timebuf.hh"
5311246Sradhika.jagtap@ARM.com#include "sim/probe/probe.hh"
541060SN/A
558737Skoansin.tan@gmail.comstruct DerivO3CPUParams;
565529Snate@binkert.org
572292SN/A/**
582329SN/A * DefaultRename handles both single threaded and SMT rename. Its
592329SN/A * width is specified by the parameters; each cycle it tries to rename
602329SN/A * that many instructions. It holds onto the rename history of all
612329SN/A * instructions with destination registers, storing the
622329SN/A * arch. register, the new physical register, and the old physical
632329SN/A * register, to allow for undoing of mappings if squashing happens, or
642329SN/A * freeing up registers upon commit. Rename handles blocking if the
652329SN/A * ROB, IQ, or LSQ is going to be full. Rename also handles barriers,
662329SN/A * and does so by stalling on the instruction until the ROB is empty
672329SN/A * and there are no instructions in flight to the ROB.
682292SN/A */
691060SN/Atemplate<class Impl>
702292SN/Aclass DefaultRename
711060SN/A{
721060SN/A  public:
731060SN/A    // Typedefs from the Impl.
741060SN/A    typedef typename Impl::CPUPol CPUPol;
751061SN/A    typedef typename Impl::DynInstPtr DynInstPtr;
762733Sktlim@umich.edu    typedef typename Impl::O3CPU O3CPU;
771060SN/A
782292SN/A    // Typedefs from the CPUPol
791061SN/A    typedef typename CPUPol::DecodeStruct DecodeStruct;
801061SN/A    typedef typename CPUPol::RenameStruct RenameStruct;
811061SN/A    typedef typename CPUPol::TimeStruct TimeStruct;
821060SN/A    typedef typename CPUPol::FreeList FreeList;
831060SN/A    typedef typename CPUPol::RenameMap RenameMap;
842292SN/A    // These are used only for initialization.
852292SN/A    typedef typename CPUPol::IEW IEW;
862292SN/A    typedef typename CPUPol::Commit Commit;
871060SN/A
8810378Sandreas.hansson@arm.com    // A deque is used to queue the instructions. Barrier insts must
8910378Sandreas.hansson@arm.com    // be added to the front of the queue, which is the only reason for
9010378Sandreas.hansson@arm.com    // using a deque instead of a queue. (Most other stages use a
912329SN/A    // queue)
9210378Sandreas.hansson@arm.com    typedef std::deque<DynInstPtr> InstQueue;
932292SN/A
941060SN/A  public:
952329SN/A    /** Overall rename status. Used to determine if the CPU can
962329SN/A     * deschedule itself due to a lack of activity.
972292SN/A     */
982292SN/A    enum RenameStatus {
992292SN/A        Active,
1002292SN/A        Inactive
1012292SN/A    };
1022292SN/A
1032292SN/A    /** Individual thread status. */
1042292SN/A    enum ThreadStatus {
1051060SN/A        Running,
1061060SN/A        Idle,
1072292SN/A        StartSquash,
1081060SN/A        Squashing,
1091060SN/A        Blocked,
1101060SN/A        Unblocking,
1112301SN/A        SerializeStall
1121060SN/A    };
1131060SN/A
1141060SN/A  private:
1152292SN/A    /** Rename status. */
1162292SN/A    RenameStatus _status;
1172292SN/A
1182292SN/A    /** Per-thread status. */
1192292SN/A    ThreadStatus renameStatus[Impl::MaxThreads];
1201060SN/A
12111246Sradhika.jagtap@ARM.com    /** Probe points. */
12212105Snathanael.premillieu@arm.com    typedef typename std::pair<InstSeqNum, PhysRegIdPtr> SeqNumRegPair;
12311246Sradhika.jagtap@ARM.com    /** To probe when register renaming for an instruction is complete */
12411246Sradhika.jagtap@ARM.com    ProbePointArg<DynInstPtr> *ppRename;
12511246Sradhika.jagtap@ARM.com    /**
12611246Sradhika.jagtap@ARM.com     * To probe when an instruction is squashed and the register mapping
12711246Sradhika.jagtap@ARM.com     * for it needs to be undone
12811246Sradhika.jagtap@ARM.com     */
12911246Sradhika.jagtap@ARM.com    ProbePointArg<SeqNumRegPair> *ppSquashInRename;
13011246Sradhika.jagtap@ARM.com
1311060SN/A  public:
1322292SN/A    /** DefaultRename constructor. */
1335529Snate@binkert.org    DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params);
1341060SN/A
1352292SN/A    /** Returns the name of rename. */
1362292SN/A    std::string name() const;
1372292SN/A
1382292SN/A    /** Registers statistics. */
1391062SN/A    void regStats();
1401062SN/A
14111246Sradhika.jagtap@ARM.com    /** Registers probes. */
14211246Sradhika.jagtap@ARM.com    void regProbePoints();
14311246Sradhika.jagtap@ARM.com
1442292SN/A    /** Sets the main backwards communication time buffer pointer. */
1451060SN/A    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
1461060SN/A
1472292SN/A    /** Sets pointer to time buffer used to communicate to the next stage. */
1481060SN/A    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
1491060SN/A
1502292SN/A    /** Sets pointer to time buffer coming from decode. */
1511060SN/A    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
1521060SN/A
1532292SN/A    /** Sets pointer to IEW stage. Used only for initialization. */
1542292SN/A    void setIEWStage(IEW *iew_stage)
1552292SN/A    { iew_ptr = iew_stage; }
1561060SN/A
1572292SN/A    /** Sets pointer to commit stage. Used only for initialization. */
1582292SN/A    void setCommitStage(Commit *commit_stage)
1592292SN/A    { commit_ptr = commit_stage; }
1602292SN/A
1612292SN/A  private:
1622292SN/A    /** Pointer to IEW stage. Used only for initialization. */
1632292SN/A    IEW *iew_ptr;
1642292SN/A
1652292SN/A    /** Pointer to commit stage. Used only for initialization. */
1662292SN/A    Commit *commit_ptr;
1672292SN/A
1682292SN/A  public:
1692292SN/A    /** Initializes variables for the stage. */
1709427SAndreas.Sandberg@ARM.com    void startupStage();
1712292SN/A
1722292SN/A    /** Sets pointer to list of active threads. */
1736221Snate@binkert.org    void setActiveThreads(std::list<ThreadID> *at_ptr);
1742292SN/A
1752292SN/A    /** Sets pointer to rename maps (per-thread structures). */
1762292SN/A    void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
1772292SN/A
1782292SN/A    /** Sets pointer to the free list. */
1791060SN/A    void setFreeList(FreeList *fl_ptr);
1801060SN/A
1812292SN/A    /** Sets pointer to the scoreboard. */
1822292SN/A    void setScoreboard(Scoreboard *_scoreboard);
1832292SN/A
1849444SAndreas.Sandberg@ARM.com    /** Perform sanity checks after a drain. */
1859444SAndreas.Sandberg@ARM.com    void drainSanityCheck() const;
1862843Sktlim@umich.edu
1879444SAndreas.Sandberg@ARM.com    /** Has the stage drained? */
1889444SAndreas.Sandberg@ARM.com    bool isDrained() const;
1892307SN/A
1902348SN/A    /** Takes over from another CPU's thread. */
1912307SN/A    void takeOverFrom();
1922307SN/A
1932292SN/A    /** Squashes all instructions in a thread. */
1946221Snate@binkert.org    void squash(const InstSeqNum &squash_seq_num, ThreadID tid);
1952292SN/A
1962292SN/A    /** Ticks rename, which processes all input signals and attempts to rename
1972292SN/A     * as many instructions as possible.
1982292SN/A     */
1992292SN/A    void tick();
2002292SN/A
2012292SN/A    /** Debugging function used to dump history buffer of renamings. */
2021060SN/A    void dumpHistory();
2031060SN/A
2042292SN/A  private:
2059444SAndreas.Sandberg@ARM.com    /** Reset this pipeline stage */
2069444SAndreas.Sandberg@ARM.com    void resetStage();
2079444SAndreas.Sandberg@ARM.com
2082292SN/A    /** Determines what to do based on rename's current status.
2092292SN/A     * @param status_change rename() sets this variable if there was a status
2102292SN/A     * change (ie switching from blocking to unblocking).
2112292SN/A     * @param tid Thread id to rename instructions from.
2122292SN/A     */
2136221Snate@binkert.org    void rename(bool &status_change, ThreadID tid);
2141060SN/A
2152292SN/A    /** Renames instructions for the given thread. Also handles serializing
2162292SN/A     * instructions.
2172292SN/A     */
2186221Snate@binkert.org    void renameInsts(ThreadID tid);
2191060SN/A
2202292SN/A    /** Inserts unused instructions from a given thread into the skid buffer,
2212292SN/A     * to be renamed once rename unblocks.
2222292SN/A     */
2236221Snate@binkert.org    void skidInsert(ThreadID tid);
2241060SN/A
2252292SN/A    /** Separates instructions from decode into individual lists of instructions
2262292SN/A     * sorted by thread.
2272292SN/A     */
2282292SN/A    void sortInsts();
2291060SN/A
2302292SN/A    /** Returns if all of the skid buffers are empty. */
2312292SN/A    bool skidsEmpty();
2321060SN/A
2332292SN/A    /** Updates overall rename status based on all of the threads' statuses. */
2342292SN/A    void updateStatus();
2351060SN/A
2362292SN/A    /** Switches rename to blocking, and signals back that rename has become
2372292SN/A     * blocked.
2382292SN/A     * @return Returns true if there is a status change.
2392292SN/A     */
2406221Snate@binkert.org    bool block(ThreadID tid);
2411060SN/A
2422292SN/A    /** Switches rename to unblocking if the skid buffer is empty, and signals
2432292SN/A     * back that rename has unblocked.
2442292SN/A     * @return Returns true if there is a status change.
2452292SN/A     */
2466221Snate@binkert.org    bool unblock(ThreadID tid);
2471061SN/A
2482292SN/A    /** Executes actual squash, removing squashed instructions. */
2496221Snate@binkert.org    void doSquash(const InstSeqNum &squash_seq_num, ThreadID tid);
2501061SN/A
2512292SN/A    /** Removes a committed instruction's rename history. */
2526221Snate@binkert.org    void removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid);
2531061SN/A
2542292SN/A    /** Renames the source registers of an instruction. */
2556221Snate@binkert.org    inline void renameSrcRegs(DynInstPtr &inst, ThreadID tid);
2561061SN/A
2572292SN/A    /** Renames the destination registers of an instruction. */
2586221Snate@binkert.org    inline void renameDestRegs(DynInstPtr &inst, ThreadID tid);
2592292SN/A
2602292SN/A    /** Calculates the number of free ROB entries for a specific thread. */
2616221Snate@binkert.org    inline int calcFreeROBEntries(ThreadID tid);
2622292SN/A
2632292SN/A    /** Calculates the number of free IQ entries for a specific thread. */
2646221Snate@binkert.org    inline int calcFreeIQEntries(ThreadID tid);
2652292SN/A
26610239Sbinhpham@cs.rutgers.edu    /** Calculates the number of free LQ entries for a specific thread. */
26710239Sbinhpham@cs.rutgers.edu    inline int calcFreeLQEntries(ThreadID tid);
26810239Sbinhpham@cs.rutgers.edu
26910239Sbinhpham@cs.rutgers.edu    /** Calculates the number of free SQ entries for a specific thread. */
27010239Sbinhpham@cs.rutgers.edu    inline int calcFreeSQEntries(ThreadID tid);
2712292SN/A
2722292SN/A    /** Returns the number of valid instructions coming from decode. */
2732292SN/A    unsigned validInsts();
2742292SN/A
2752292SN/A    /** Reads signals telling rename to block/unblock. */
2766221Snate@binkert.org    void readStallSignals(ThreadID tid);
2772292SN/A
2782292SN/A    /** Checks if any stages are telling rename to block. */
2796221Snate@binkert.org    bool checkStall(ThreadID tid);
2802292SN/A
2812348SN/A    /** Gets the number of free entries for a specific thread. */
2826221Snate@binkert.org    void readFreeEntries(ThreadID tid);
2832292SN/A
2842348SN/A    /** Checks the signals and updates the status. */
2856221Snate@binkert.org    bool checkSignalsAndUpdate(ThreadID tid);
2862292SN/A
2872292SN/A    /** Either serializes on the next instruction available in the InstQueue,
2882292SN/A     * or records that it must serialize on the next instruction to enter
2892292SN/A     * rename.
2902292SN/A     * @param inst_list The list of younger, unprocessed instructions for the
2912292SN/A     * thread that has the serializeAfter instruction.
2922292SN/A     * @param tid The thread id.
2932292SN/A     */
2946221Snate@binkert.org    void serializeAfter(InstQueue &inst_list, ThreadID tid);
2952292SN/A
2962292SN/A    /** Holds the information for each destination register rename. It holds
2972292SN/A     * the instruction's sequence number, the arch register, the old physical
2982292SN/A     * register for that arch. register, and the new physical register.
2991060SN/A     */
3001060SN/A    struct RenameHistory {
30112106SRekai.GonzalezAlberquilla@arm.com        RenameHistory(InstSeqNum _instSeqNum, const RegId& _archReg,
30212105Snathanael.premillieu@arm.com                      PhysRegIdPtr _newPhysReg,
30312105Snathanael.premillieu@arm.com                      PhysRegIdPtr _prevPhysReg)
3041060SN/A            : instSeqNum(_instSeqNum), archReg(_archReg),
3052292SN/A              newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg)
3061060SN/A        {
3071060SN/A        }
3081060SN/A
3092292SN/A        /** The sequence number of the instruction that renamed. */
3101060SN/A        InstSeqNum instSeqNum;
3112292SN/A        /** The architectural register index that was renamed. */
31212104Snathanael.premillieu@arm.com        RegId archReg;
3132292SN/A        /** The new physical register that the arch. register is renamed to. */
31412105Snathanael.premillieu@arm.com        PhysRegIdPtr newPhysReg;
31512105Snathanael.premillieu@arm.com        /** The old physical register that the arch. register was renamed to.
31612105Snathanael.premillieu@arm.com         */
31712105Snathanael.premillieu@arm.com        PhysRegIdPtr prevPhysReg;
3181060SN/A    };
3191060SN/A
3202292SN/A    /** A per-thread list of all destination register renames, used to either
3212292SN/A     * undo rename mappings or free old physical registers.
3222292SN/A     */
3232292SN/A    std::list<RenameHistory> historyBuffer[Impl::MaxThreads];
3241060SN/A
3252292SN/A    /** Pointer to CPU. */
3262733Sktlim@umich.edu    O3CPU *cpu;
3271060SN/A
3282292SN/A    /** Pointer to main time buffer used for backwards communication. */
3291060SN/A    TimeBuffer<TimeStruct> *timeBuffer;
3301060SN/A
3311060SN/A    /** Wire to get IEW's output from backwards time buffer. */
3321060SN/A    typename TimeBuffer<TimeStruct>::wire fromIEW;
3331060SN/A
3341060SN/A    /** Wire to get commit's output from backwards time buffer. */
3351060SN/A    typename TimeBuffer<TimeStruct>::wire fromCommit;
3361060SN/A
3371060SN/A    /** Wire to write infromation heading to previous stages. */
3381060SN/A    typename TimeBuffer<TimeStruct>::wire toDecode;
3391060SN/A
3401060SN/A    /** Rename instruction queue. */
3411060SN/A    TimeBuffer<RenameStruct> *renameQueue;
3421060SN/A
3431060SN/A    /** Wire to write any information heading to IEW. */
3441060SN/A    typename TimeBuffer<RenameStruct>::wire toIEW;
3451060SN/A
3461060SN/A    /** Decode instruction queue interface. */
3471060SN/A    TimeBuffer<DecodeStruct> *decodeQueue;
3481060SN/A
3491060SN/A    /** Wire to get decode's output from decode queue. */
3501060SN/A    typename TimeBuffer<DecodeStruct>::wire fromDecode;
3511060SN/A
3522292SN/A    /** Queue of all instructions coming from decode this cycle. */
3532292SN/A    InstQueue insts[Impl::MaxThreads];
3542292SN/A
3551060SN/A    /** Skid buffer between rename and decode. */
3562292SN/A    InstQueue skidBuffer[Impl::MaxThreads];
3571060SN/A
3581060SN/A    /** Rename map interface. */
3592292SN/A    RenameMap *renameMap[Impl::MaxThreads];
3601060SN/A
3611060SN/A    /** Free list interface. */
3621060SN/A    FreeList *freeList;
3631060SN/A
3642292SN/A    /** Pointer to the list of active threads. */
3656221Snate@binkert.org    std::list<ThreadID> *activeThreads;
3662292SN/A
3672292SN/A    /** Pointer to the scoreboard. */
3682292SN/A    Scoreboard *scoreboard;
3692292SN/A
3702292SN/A    /** Count of instructions in progress that have been sent off to the IQ
3712292SN/A     * and ROB, but are not yet included in their occupancy counts.
3722292SN/A     */
3732292SN/A    int instsInProgress[Impl::MaxThreads];
3742292SN/A
37510239Sbinhpham@cs.rutgers.edu    /** Count of Load instructions in progress that have been sent off to the IQ
37610239Sbinhpham@cs.rutgers.edu     * and ROB, but are not yet included in their occupancy counts.
37710239Sbinhpham@cs.rutgers.edu     */
37810239Sbinhpham@cs.rutgers.edu    int loadsInProgress[Impl::MaxThreads];
37910239Sbinhpham@cs.rutgers.edu
38010239Sbinhpham@cs.rutgers.edu    /** Count of Store instructions in progress that have been sent off to the IQ
38110239Sbinhpham@cs.rutgers.edu     * and ROB, but are not yet included in their occupancy counts.
38210239Sbinhpham@cs.rutgers.edu     */
38310239Sbinhpham@cs.rutgers.edu    int storesInProgress[Impl::MaxThreads];
38410239Sbinhpham@cs.rutgers.edu
3852292SN/A    /** Variable that tracks if decode has written to the time buffer this
3862292SN/A     * cycle. Used to tell CPU if there is activity this cycle.
3872292SN/A     */
3882292SN/A    bool wroteToTimeBuffer;
3892292SN/A
3902292SN/A    /** Structures whose free entries impact the amount of instructions that
3912292SN/A     * can be renamed.
3922292SN/A     */
3932292SN/A    struct FreeEntries {
3942292SN/A        unsigned iqEntries;
3952292SN/A        unsigned robEntries;
39610239Sbinhpham@cs.rutgers.edu        unsigned lqEntries;
39710239Sbinhpham@cs.rutgers.edu        unsigned sqEntries;
3982292SN/A    };
3992292SN/A
4002292SN/A    /** Per-thread tracking of the number of free entries of back-end
4012292SN/A     * structures.
4022292SN/A     */
4032292SN/A    FreeEntries freeEntries[Impl::MaxThreads];
4042292SN/A
4052292SN/A    /** Records if the ROB is empty. In SMT mode the ROB may be dynamically
4062292SN/A     * partitioned between threads, so the ROB must tell rename when it is
4072292SN/A     * empty.
4082292SN/A     */
4092292SN/A    bool emptyROB[Impl::MaxThreads];
4102292SN/A
4112292SN/A    /** Source of possible stalls. */
4122292SN/A    struct Stalls {
4132292SN/A        bool iew;
4142292SN/A        bool commit;
4152292SN/A    };
4162292SN/A
4172292SN/A    /** Tracks which stages are telling decode to stall. */
4182292SN/A    Stalls stalls[Impl::MaxThreads];
4192292SN/A
4202301SN/A    /** The serialize instruction that rename has stalled on. */
4212301SN/A    DynInstPtr serializeInst[Impl::MaxThreads];
4222292SN/A
4232292SN/A    /** Records if rename needs to serialize on the next instruction for any
4242292SN/A     * thread.
4252292SN/A     */
4262292SN/A    bool serializeOnNextInst[Impl::MaxThreads];
4272292SN/A
4281060SN/A    /** Delay between iew and rename, in ticks. */
4291060SN/A    int iewToRenameDelay;
4301060SN/A
4311060SN/A    /** Delay between decode and rename, in ticks. */
4321060SN/A    int decodeToRenameDelay;
4331060SN/A
4341060SN/A    /** Delay between commit and rename, in ticks. */
4351060SN/A    unsigned commitToRenameDelay;
4361060SN/A
4371060SN/A    /** Rename width, in instructions. */
4381060SN/A    unsigned renameWidth;
4391060SN/A
4401060SN/A    /** Commit width, in instructions.  Used so rename knows how many
4411060SN/A     *  instructions might have freed registers in the previous cycle.
4421060SN/A     */
4431060SN/A    unsigned commitWidth;
4441061SN/A
4452292SN/A    /** The index of the instruction in the time buffer to IEW that rename is
4462292SN/A     * currently using.
4471061SN/A     */
4482292SN/A    unsigned toIEWIndex;
4491062SN/A
4502292SN/A    /** Whether or not rename needs to block this cycle. */
4512292SN/A    bool blockThisCycle;
4522292SN/A
4533788Sgblack@eecs.umich.edu    /** Whether or not rename needs to resume a serialize instruction
4543788Sgblack@eecs.umich.edu     * after squashing. */
4553788Sgblack@eecs.umich.edu    bool resumeSerialize;
4563788Sgblack@eecs.umich.edu
4573798Sgblack@eecs.umich.edu    /** Whether or not rename needs to resume clearing out the skidbuffer
4583798Sgblack@eecs.umich.edu     * after squashing. */
4593798Sgblack@eecs.umich.edu    bool resumeUnblocking;
4603798Sgblack@eecs.umich.edu
4612292SN/A    /** The number of threads active in rename. */
4626221Snate@binkert.org    ThreadID numThreads;
4632292SN/A
4642292SN/A    /** The maximum skid buffer size. */
4652292SN/A    unsigned skidBufferMax;
4662292SN/A
4672292SN/A    /** Enum to record the source of a structure full stall.  Can come from
4682292SN/A     * either ROB, IQ, LSQ, and it is priortized in that order.
4692292SN/A     */
4702292SN/A    enum FullSource {
4712292SN/A        ROB,
4722292SN/A        IQ,
47310239Sbinhpham@cs.rutgers.edu        LQ,
47410239Sbinhpham@cs.rutgers.edu        SQ,
4752292SN/A        NONE
4762292SN/A    };
4772292SN/A
4782292SN/A    /** Function used to increment the stat that corresponds to the source of
4792292SN/A     * the stall.
4802292SN/A     */
4812292SN/A    inline void incrFullStat(const FullSource &source);
4822292SN/A
4832292SN/A    /** Stat for total number of cycles spent squashing. */
4845999Snate@binkert.org    Stats::Scalar renameSquashCycles;
4852292SN/A    /** Stat for total number of cycles spent idle. */
4865999Snate@binkert.org    Stats::Scalar renameIdleCycles;
4872292SN/A    /** Stat for total number of cycles spent blocking. */
4885999Snate@binkert.org    Stats::Scalar renameBlockCycles;
4892301SN/A    /** Stat for total number of cycles spent stalling for a serializing inst. */
4905999Snate@binkert.org    Stats::Scalar renameSerializeStallCycles;
4912292SN/A    /** Stat for total number of cycles spent running normally. */
4925999Snate@binkert.org    Stats::Scalar renameRunCycles;
4932292SN/A    /** Stat for total number of cycles spent unblocking. */
4945999Snate@binkert.org    Stats::Scalar renameUnblockCycles;
4952292SN/A    /** Stat for total number of renamed instructions. */
4965999Snate@binkert.org    Stats::Scalar renameRenamedInsts;
4972292SN/A    /** Stat for total number of squashed instructions that rename discards. */
4985999Snate@binkert.org    Stats::Scalar renameSquashedInsts;
4992292SN/A    /** Stat for total number of times that the ROB starts a stall in rename. */
5005999Snate@binkert.org    Stats::Scalar renameROBFullEvents;
5012292SN/A    /** Stat for total number of times that the IQ starts a stall in rename. */
5025999Snate@binkert.org    Stats::Scalar renameIQFullEvents;
50310239Sbinhpham@cs.rutgers.edu    /** Stat for total number of times that the LQ starts a stall in rename. */
50410239Sbinhpham@cs.rutgers.edu    Stats::Scalar renameLQFullEvents;
50510239Sbinhpham@cs.rutgers.edu    /** Stat for total number of times that the SQ starts a stall in rename. */
50610239Sbinhpham@cs.rutgers.edu    Stats::Scalar renameSQFullEvents;
5072292SN/A    /** Stat for total number of times that rename runs out of free registers
5082292SN/A     * to use to rename. */
5095999Snate@binkert.org    Stats::Scalar renameFullRegistersEvents;
5102292SN/A    /** Stat for total number of renamed destination registers. */
5115999Snate@binkert.org    Stats::Scalar renameRenamedOperands;
5122292SN/A    /** Stat for total number of source register rename lookups. */
5135999Snate@binkert.org    Stats::Scalar renameRenameLookups;
5147897Shestness@cs.utexas.edu    Stats::Scalar intRenameLookups;
5157897Shestness@cs.utexas.edu    Stats::Scalar fpRenameLookups;
51612109SRekai.GonzalezAlberquilla@arm.com    Stats::Scalar vecRenameLookups;
5172292SN/A    /** Stat for total number of committed renaming mappings. */
5185999Snate@binkert.org    Stats::Scalar renameCommittedMaps;
5192292SN/A    /** Stat for total number of mappings that were undone due to a squash. */
5205999Snate@binkert.org    Stats::Scalar renameUndoneMaps;
5212348SN/A    /** Number of serialize instructions handled. */
5225999Snate@binkert.org    Stats::Scalar renamedSerializing;
5232348SN/A    /** Number of instructions marked as temporarily serializing. */
5245999Snate@binkert.org    Stats::Scalar renamedTempSerializing;
5252348SN/A    /** Number of instructions inserted into skid buffers. */
5265999Snate@binkert.org    Stats::Scalar renameSkidInsts;
5271060SN/A};
5281060SN/A
5292292SN/A#endif // __CPU_O3_RENAME_HH__
530