rename.hh revision 1060
11689SN/A// Todo: 22329SN/A// Figure out rename map for reg vs fp (probably just have one rename map). 31689SN/A// In simple case, there is no renaming, so have this stage do basically 41689SN/A// nothing. 51689SN/A// Fix up trap and barrier handling. Fix up squashing too, as it's too 61689SN/A// dependent upon the iew stage continually telling it to squash. 71689SN/A// Have commit send back information whenever a branch has committed. This 81689SN/A// way the history buffer can be cleared beyond the point where the branch 91689SN/A// was. 101689SN/A 111689SN/A#ifndef __SIMPLE_RENAME_HH__ 121689SN/A#define __SIMPLE_RENAME_HH__ 131689SN/A 141689SN/A//Will want to include: time buffer, structs, free list, rename map 151689SN/A#include <list> 161689SN/A 171689SN/A#include "base/timebuf.hh" 181689SN/A#include "cpu/beta_cpu/comm.hh" 191689SN/A#include "cpu/beta_cpu/rename_map.hh" 201689SN/A#include "cpu/beta_cpu/free_list.hh" 211689SN/A 221689SN/Ausing namespace std; 231689SN/A 241689SN/A// Will need rename maps for both the int reg file and fp reg file. 251689SN/A// Or change rename map class to handle both. (RegFile handles both.) 261689SN/Atemplate<class Impl> 272665Ssaidi@eecs.umich.educlass SimpleRename 282665Ssaidi@eecs.umich.edu{ 292831Sksewell@umich.edu public: 301689SN/A // Typedefs from the Impl. 311689SN/A typedef typename Impl::ISA ISA; 326221Snate@binkert.org typedef typename Impl::CPUPol CPUPol; 336221Snate@binkert.org typedef typename Impl::DynInst DynInst; 341858SN/A typedef typename Impl::FullCPU FullCPU; 351717SN/A typedef typename Impl::Params Params; 361060SN/A 376221Snate@binkert.org typedef typename Impl::FetchStruct FetchStruct; 382292SN/A typedef typename Impl::DecodeStruct DecodeStruct; 391061SN/A typedef typename Impl::RenameStruct RenameStruct; 404329Sktlim@umich.edu typedef typename Impl::TimeStruct TimeStruct; 412980Sgblack@eecs.umich.edu 426221Snate@binkert.org // Typedefs from the CPUPol 434329Sktlim@umich.edu typedef typename CPUPol::FreeList FreeList; 444329Sktlim@umich.edu typedef typename CPUPol::RenameMap RenameMap; 451060SN/A 461060SN/A // Typedefs from the ISA. 472292SN/A typedef typename ISA::Addr Addr; 481060SN/A 496221Snate@binkert.org public: 502877Sksewell@umich.edu // Rename will block if ROB becomes full or issue queue becomes full, 512292SN/A // or there are no free registers to rename to. 522292SN/A // Only case where rename squashes is if IEW squashes. 532292SN/A enum Status { 542292SN/A Running, 552980Sgblack@eecs.umich.edu Idle, 562292SN/A Squashing, 572292SN/A Blocked, 582292SN/A Unblocking, 592292SN/A BarrierStall 602292SN/A }; 612292SN/A 622292SN/A private: 632292SN/A Status _status; 642292SN/A 652292SN/A public: 666221Snate@binkert.org SimpleRename(Params ¶ms); 676221Snate@binkert.org 682292SN/A void setCPU(FullCPU *cpu_ptr); 692292SN/A 702292SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 712292SN/A 724329Sktlim@umich.edu void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 732292SN/A 742292SN/A void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 752292SN/A 762292SN/A void setRenameMap(RenameMap *rm_ptr); 772292SN/A 786221Snate@binkert.org void setFreeList(FreeList *fl_ptr); 796221Snate@binkert.org 802292SN/A void dumpHistory(); 812292SN/A 822292SN/A void tick(); 832292SN/A 844329Sktlim@umich.edu void rename(); 852292SN/A 862292SN/A void squash(); 872292SN/A 882292SN/A private: 896221Snate@binkert.org void block(); 906221Snate@binkert.org 912292SN/A inline void unblock(); 922292SN/A 932292SN/A void doSquash(); 942292SN/A 952292SN/A void removeFromHistory(InstSeqNum inst_seq_num); 961060SN/A 972292SN/A /** Holds the previous information for each rename. 986221Snate@binkert.org * Note that often times the inst may have been deleted, so only access 996221Snate@binkert.org * the pointer for the address and do not dereference it. 1002292SN/A */ 1011060SN/A struct RenameHistory { 1022292SN/A RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, 1032292SN/A PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) 1042292SN/A : instSeqNum(_instSeqNum), archReg(_archReg), 1052292SN/A newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg), 1062292SN/A placeHolder(false) 1072292SN/A { 1082292SN/A } 1094329Sktlim@umich.edu 1104329Sktlim@umich.edu /** Constructor used specifically for cases where a place holder 1114329Sktlim@umich.edu * rename history entry is being made. 1124329Sktlim@umich.edu */ 1134329Sktlim@umich.edu RenameHistory(InstSeqNum _instSeqNum) 1144329Sktlim@umich.edu : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0), 1154329Sktlim@umich.edu prevPhysReg(0), placeHolder(true) 1162292SN/A { 1176221Snate@binkert.org } 1182292SN/A 1192292SN/A InstSeqNum instSeqNum; 1202292SN/A RegIndex archReg; 1212292SN/A PhysRegIndex newPhysReg; 1222292SN/A PhysRegIndex prevPhysReg; 1232307SN/A bool placeHolder; 1242307SN/A }; 1252307SN/A 1262307SN/A list<RenameHistory> historyBuffer; 1276221Snate@binkert.org 1282307SN/A /** CPU interface. */ 1292307SN/A FullCPU *cpu; 1302307SN/A 1312307SN/A // Interfaces to objects outside of rename. 1322307SN/A /** Time buffer interface. */ 1332307SN/A TimeBuffer<TimeStruct> *timeBuffer; 1342307SN/A 1352307SN/A /** Wire to get IEW's output from backwards time buffer. */ 1366221Snate@binkert.org typename TimeBuffer<TimeStruct>::wire fromIEW; 1372307SN/A 1382307SN/A /** Wire to get commit's output from backwards time buffer. */ 1392307SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 1402307SN/A 1412307SN/A /** Wire to write infromation heading to previous stages. */ 1422307SN/A // Might not be the best name as not only decode will read it. 1432307SN/A typename TimeBuffer<TimeStruct>::wire toDecode; 1442307SN/A 1452307SN/A /** Rename instruction queue. */ 1462307SN/A TimeBuffer<RenameStruct> *renameQueue; 1472307SN/A 1482292SN/A /** Wire to write any information heading to IEW. */ 1492292SN/A typename TimeBuffer<RenameStruct>::wire toIEW; 1502292SN/A 1512292SN/A /** Decode instruction queue interface. */ 1522292SN/A TimeBuffer<DecodeStruct> *decodeQueue; 1532292SN/A 1543867Sbinkertn@umich.edu /** Wire to get decode's output from decode queue. */ 1552292SN/A typename TimeBuffer<DecodeStruct>::wire fromDecode; 1566221Snate@binkert.org 1576221Snate@binkert.org /** Skid buffer between rename and decode. */ 1582292SN/A queue<DecodeStruct> skidBuffer; 1593867Sbinkertn@umich.edu 1606221Snate@binkert.org /** Rename map interface. */ 1613867Sbinkertn@umich.edu SimpleRenameMap *renameMap; 1622292SN/A 1633867Sbinkertn@umich.edu /** Free list interface. */ 1642292SN/A FreeList *freeList; 1653867Sbinkertn@umich.edu 1662292SN/A /** Delay between iew and rename, in ticks. */ 1672292SN/A int iewToRenameDelay; 1682292SN/A 1692292SN/A /** Delay between decode and rename, in ticks. */ 1702292SN/A int decodeToRenameDelay; 1712292SN/A 1722292SN/A /** Delay between commit and rename, in ticks. */ 1736221Snate@binkert.org unsigned commitToRenameDelay; 1742292SN/A 1752292SN/A /** Rename width, in instructions. */ 1762292SN/A unsigned renameWidth; 1772292SN/A 1782292SN/A /** Commit width, in instructions. Used so rename knows how many 1792292SN/A * instructions might have freed registers in the previous cycle. 1801060SN/A */ 1811060SN/A unsigned commitWidth; 1821061SN/A}; 1831060SN/A 1841060SN/A#endif // __SIMPLE_RENAME_HH__ 1851060SN/A