rename.hh revision 10239
11689SN/A/* 29444SAndreas.Sandberg@ARM.com * Copyright (c) 2012 ARM Limited 39444SAndreas.Sandberg@ARM.com * All rights reserved 49444SAndreas.Sandberg@ARM.com * 59444SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69444SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79444SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89444SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99444SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109444SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119444SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129444SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139444SAndreas.Sandberg@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 1510239Sbinhpham@cs.rutgers.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 421689SN/A */ 431689SN/A 442292SN/A#ifndef __CPU_O3_RENAME_HH__ 452292SN/A#define __CPU_O3_RENAME_HH__ 461060SN/A 471060SN/A#include <list> 481060SN/A 491461SN/A#include "base/statistics.hh" 508229Snate@binkert.org#include "config/the_isa.hh" 517813Ssteve.reinhardt@amd.com#include "cpu/timebuf.hh" 521060SN/A 538737Skoansin.tan@gmail.comstruct DerivO3CPUParams; 545529Snate@binkert.org 552292SN/A/** 562329SN/A * DefaultRename handles both single threaded and SMT rename. Its 572329SN/A * width is specified by the parameters; each cycle it tries to rename 582329SN/A * that many instructions. It holds onto the rename history of all 592329SN/A * instructions with destination registers, storing the 602329SN/A * arch. register, the new physical register, and the old physical 612329SN/A * register, to allow for undoing of mappings if squashing happens, or 622329SN/A * freeing up registers upon commit. Rename handles blocking if the 632329SN/A * ROB, IQ, or LSQ is going to be full. Rename also handles barriers, 642329SN/A * and does so by stalling on the instruction until the ROB is empty 652329SN/A * and there are no instructions in flight to the ROB. 662292SN/A */ 671060SN/Atemplate<class Impl> 682292SN/Aclass DefaultRename 691060SN/A{ 701060SN/A public: 711060SN/A // Typedefs from the Impl. 721060SN/A typedef typename Impl::CPUPol CPUPol; 731061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 742733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 751060SN/A 762292SN/A // Typedefs from the CPUPol 771061SN/A typedef typename CPUPol::DecodeStruct DecodeStruct; 781061SN/A typedef typename CPUPol::RenameStruct RenameStruct; 791061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 801060SN/A typedef typename CPUPol::FreeList FreeList; 811060SN/A typedef typename CPUPol::RenameMap RenameMap; 822292SN/A // These are used only for initialization. 832292SN/A typedef typename CPUPol::IEW IEW; 842292SN/A typedef typename CPUPol::Commit Commit; 851060SN/A 861060SN/A // Typedefs from the ISA. 872107SN/A typedef TheISA::RegIndex RegIndex; 881060SN/A 892329SN/A // A list is used to queue the instructions. Barrier insts must 902329SN/A // be added to the front of the list, which is the only reason for 912329SN/A // using a list instead of a queue. (Most other stages use a 922329SN/A // queue) 932292SN/A typedef std::list<DynInstPtr> InstQueue; 942935Sksewell@umich.edu typedef typename std::list<DynInstPtr>::iterator ListIt; 952292SN/A 961060SN/A public: 972329SN/A /** Overall rename status. Used to determine if the CPU can 982329SN/A * deschedule itself due to a lack of activity. 992292SN/A */ 1002292SN/A enum RenameStatus { 1012292SN/A Active, 1022292SN/A Inactive 1032292SN/A }; 1042292SN/A 1052292SN/A /** Individual thread status. */ 1062292SN/A enum ThreadStatus { 1071060SN/A Running, 1081060SN/A Idle, 1092292SN/A StartSquash, 1101060SN/A Squashing, 1111060SN/A Blocked, 1121060SN/A Unblocking, 1132301SN/A SerializeStall 1141060SN/A }; 1151060SN/A 1161060SN/A private: 1172292SN/A /** Rename status. */ 1182292SN/A RenameStatus _status; 1192292SN/A 1202292SN/A /** Per-thread status. */ 1212292SN/A ThreadStatus renameStatus[Impl::MaxThreads]; 1221060SN/A 1231060SN/A public: 1242292SN/A /** DefaultRename constructor. */ 1255529Snate@binkert.org DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params); 1261060SN/A 1272292SN/A /** Returns the name of rename. */ 1282292SN/A std::string name() const; 1292292SN/A 1302292SN/A /** Registers statistics. */ 1311062SN/A void regStats(); 1321062SN/A 1332292SN/A /** Sets the main backwards communication time buffer pointer. */ 1341060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1351060SN/A 1362292SN/A /** Sets pointer to time buffer used to communicate to the next stage. */ 1371060SN/A void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 1381060SN/A 1392292SN/A /** Sets pointer to time buffer coming from decode. */ 1401060SN/A void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 1411060SN/A 1422292SN/A /** Sets pointer to IEW stage. Used only for initialization. */ 1432292SN/A void setIEWStage(IEW *iew_stage) 1442292SN/A { iew_ptr = iew_stage; } 1451060SN/A 1462292SN/A /** Sets pointer to commit stage. Used only for initialization. */ 1472292SN/A void setCommitStage(Commit *commit_stage) 1482292SN/A { commit_ptr = commit_stage; } 1492292SN/A 1502292SN/A private: 1512292SN/A /** Pointer to IEW stage. Used only for initialization. */ 1522292SN/A IEW *iew_ptr; 1532292SN/A 1542292SN/A /** Pointer to commit stage. Used only for initialization. */ 1552292SN/A Commit *commit_ptr; 1562292SN/A 1572292SN/A public: 1582292SN/A /** Initializes variables for the stage. */ 1599427SAndreas.Sandberg@ARM.com void startupStage(); 1602292SN/A 1612292SN/A /** Sets pointer to list of active threads. */ 1626221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 1632292SN/A 1642292SN/A /** Sets pointer to rename maps (per-thread structures). */ 1652292SN/A void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 1662292SN/A 1672292SN/A /** Sets pointer to the free list. */ 1681060SN/A void setFreeList(FreeList *fl_ptr); 1691060SN/A 1702292SN/A /** Sets pointer to the scoreboard. */ 1712292SN/A void setScoreboard(Scoreboard *_scoreboard); 1722292SN/A 1739444SAndreas.Sandberg@ARM.com /** Perform sanity checks after a drain. */ 1749444SAndreas.Sandberg@ARM.com void drainSanityCheck() const; 1752843Sktlim@umich.edu 1769444SAndreas.Sandberg@ARM.com /** Has the stage drained? */ 1779444SAndreas.Sandberg@ARM.com bool isDrained() const; 1782307SN/A 1792348SN/A /** Takes over from another CPU's thread. */ 1802307SN/A void takeOverFrom(); 1812307SN/A 1822292SN/A /** Squashes all instructions in a thread. */ 1836221Snate@binkert.org void squash(const InstSeqNum &squash_seq_num, ThreadID tid); 1842292SN/A 1852292SN/A /** Ticks rename, which processes all input signals and attempts to rename 1862292SN/A * as many instructions as possible. 1872292SN/A */ 1882292SN/A void tick(); 1892292SN/A 1902292SN/A /** Debugging function used to dump history buffer of renamings. */ 1911060SN/A void dumpHistory(); 1921060SN/A 1932292SN/A private: 1949444SAndreas.Sandberg@ARM.com /** Reset this pipeline stage */ 1959444SAndreas.Sandberg@ARM.com void resetStage(); 1969444SAndreas.Sandberg@ARM.com 1972292SN/A /** Determines what to do based on rename's current status. 1982292SN/A * @param status_change rename() sets this variable if there was a status 1992292SN/A * change (ie switching from blocking to unblocking). 2002292SN/A * @param tid Thread id to rename instructions from. 2012292SN/A */ 2026221Snate@binkert.org void rename(bool &status_change, ThreadID tid); 2031060SN/A 2042292SN/A /** Renames instructions for the given thread. Also handles serializing 2052292SN/A * instructions. 2062292SN/A */ 2076221Snate@binkert.org void renameInsts(ThreadID tid); 2081060SN/A 2092292SN/A /** Inserts unused instructions from a given thread into the skid buffer, 2102292SN/A * to be renamed once rename unblocks. 2112292SN/A */ 2126221Snate@binkert.org void skidInsert(ThreadID tid); 2131060SN/A 2142292SN/A /** Separates instructions from decode into individual lists of instructions 2152292SN/A * sorted by thread. 2162292SN/A */ 2172292SN/A void sortInsts(); 2181060SN/A 2192292SN/A /** Returns if all of the skid buffers are empty. */ 2202292SN/A bool skidsEmpty(); 2211060SN/A 2222292SN/A /** Updates overall rename status based on all of the threads' statuses. */ 2232292SN/A void updateStatus(); 2241060SN/A 2252292SN/A /** Switches rename to blocking, and signals back that rename has become 2262292SN/A * blocked. 2272292SN/A * @return Returns true if there is a status change. 2282292SN/A */ 2296221Snate@binkert.org bool block(ThreadID tid); 2301060SN/A 2312292SN/A /** Switches rename to unblocking if the skid buffer is empty, and signals 2322292SN/A * back that rename has unblocked. 2332292SN/A * @return Returns true if there is a status change. 2342292SN/A */ 2356221Snate@binkert.org bool unblock(ThreadID tid); 2361061SN/A 2372292SN/A /** Executes actual squash, removing squashed instructions. */ 2386221Snate@binkert.org void doSquash(const InstSeqNum &squash_seq_num, ThreadID tid); 2391061SN/A 2402292SN/A /** Removes a committed instruction's rename history. */ 2416221Snate@binkert.org void removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid); 2421061SN/A 2432292SN/A /** Renames the source registers of an instruction. */ 2446221Snate@binkert.org inline void renameSrcRegs(DynInstPtr &inst, ThreadID tid); 2451061SN/A 2462292SN/A /** Renames the destination registers of an instruction. */ 2476221Snate@binkert.org inline void renameDestRegs(DynInstPtr &inst, ThreadID tid); 2482292SN/A 2492292SN/A /** Calculates the number of free ROB entries for a specific thread. */ 2506221Snate@binkert.org inline int calcFreeROBEntries(ThreadID tid); 2512292SN/A 2522292SN/A /** Calculates the number of free IQ entries for a specific thread. */ 2536221Snate@binkert.org inline int calcFreeIQEntries(ThreadID tid); 2542292SN/A 25510239Sbinhpham@cs.rutgers.edu /** Calculates the number of free LQ entries for a specific thread. */ 25610239Sbinhpham@cs.rutgers.edu inline int calcFreeLQEntries(ThreadID tid); 25710239Sbinhpham@cs.rutgers.edu 25810239Sbinhpham@cs.rutgers.edu /** Calculates the number of free SQ entries for a specific thread. */ 25910239Sbinhpham@cs.rutgers.edu inline int calcFreeSQEntries(ThreadID tid); 2602292SN/A 2612292SN/A /** Returns the number of valid instructions coming from decode. */ 2622292SN/A unsigned validInsts(); 2632292SN/A 2642292SN/A /** Reads signals telling rename to block/unblock. */ 2656221Snate@binkert.org void readStallSignals(ThreadID tid); 2662292SN/A 2672292SN/A /** Checks if any stages are telling rename to block. */ 2686221Snate@binkert.org bool checkStall(ThreadID tid); 2692292SN/A 2702348SN/A /** Gets the number of free entries for a specific thread. */ 2716221Snate@binkert.org void readFreeEntries(ThreadID tid); 2722292SN/A 2732348SN/A /** Checks the signals and updates the status. */ 2746221Snate@binkert.org bool checkSignalsAndUpdate(ThreadID tid); 2752292SN/A 2762292SN/A /** Either serializes on the next instruction available in the InstQueue, 2772292SN/A * or records that it must serialize on the next instruction to enter 2782292SN/A * rename. 2792292SN/A * @param inst_list The list of younger, unprocessed instructions for the 2802292SN/A * thread that has the serializeAfter instruction. 2812292SN/A * @param tid The thread id. 2822292SN/A */ 2836221Snate@binkert.org void serializeAfter(InstQueue &inst_list, ThreadID tid); 2842292SN/A 2852292SN/A /** Holds the information for each destination register rename. It holds 2862292SN/A * the instruction's sequence number, the arch register, the old physical 2872292SN/A * register for that arch. register, and the new physical register. 2881060SN/A */ 2891060SN/A struct RenameHistory { 2901060SN/A RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, 2911060SN/A PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) 2921060SN/A : instSeqNum(_instSeqNum), archReg(_archReg), 2932292SN/A newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg) 2941060SN/A { 2951060SN/A } 2961060SN/A 2972292SN/A /** The sequence number of the instruction that renamed. */ 2981060SN/A InstSeqNum instSeqNum; 2992292SN/A /** The architectural register index that was renamed. */ 3001060SN/A RegIndex archReg; 3012292SN/A /** The new physical register that the arch. register is renamed to. */ 3021060SN/A PhysRegIndex newPhysReg; 3032292SN/A /** The old physical register that the arch. register was renamed to. */ 3041060SN/A PhysRegIndex prevPhysReg; 3051060SN/A }; 3061060SN/A 3072292SN/A /** A per-thread list of all destination register renames, used to either 3082292SN/A * undo rename mappings or free old physical registers. 3092292SN/A */ 3102292SN/A std::list<RenameHistory> historyBuffer[Impl::MaxThreads]; 3111060SN/A 3122292SN/A /** Pointer to CPU. */ 3132733Sktlim@umich.edu O3CPU *cpu; 3141060SN/A 3152292SN/A /** Pointer to main time buffer used for backwards communication. */ 3161060SN/A TimeBuffer<TimeStruct> *timeBuffer; 3171060SN/A 3181060SN/A /** Wire to get IEW's output from backwards time buffer. */ 3191060SN/A typename TimeBuffer<TimeStruct>::wire fromIEW; 3201060SN/A 3211060SN/A /** Wire to get commit's output from backwards time buffer. */ 3221060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 3231060SN/A 3241060SN/A /** Wire to write infromation heading to previous stages. */ 3251060SN/A typename TimeBuffer<TimeStruct>::wire toDecode; 3261060SN/A 3271060SN/A /** Rename instruction queue. */ 3281060SN/A TimeBuffer<RenameStruct> *renameQueue; 3291060SN/A 3301060SN/A /** Wire to write any information heading to IEW. */ 3311060SN/A typename TimeBuffer<RenameStruct>::wire toIEW; 3321060SN/A 3331060SN/A /** Decode instruction queue interface. */ 3341060SN/A TimeBuffer<DecodeStruct> *decodeQueue; 3351060SN/A 3361060SN/A /** Wire to get decode's output from decode queue. */ 3371060SN/A typename TimeBuffer<DecodeStruct>::wire fromDecode; 3381060SN/A 3392292SN/A /** Queue of all instructions coming from decode this cycle. */ 3402292SN/A InstQueue insts[Impl::MaxThreads]; 3412292SN/A 3421060SN/A /** Skid buffer between rename and decode. */ 3432292SN/A InstQueue skidBuffer[Impl::MaxThreads]; 3441060SN/A 3451060SN/A /** Rename map interface. */ 3462292SN/A RenameMap *renameMap[Impl::MaxThreads]; 3471060SN/A 3481060SN/A /** Free list interface. */ 3491060SN/A FreeList *freeList; 3501060SN/A 3512292SN/A /** Pointer to the list of active threads. */ 3526221Snate@binkert.org std::list<ThreadID> *activeThreads; 3532292SN/A 3542292SN/A /** Pointer to the scoreboard. */ 3552292SN/A Scoreboard *scoreboard; 3562292SN/A 3572292SN/A /** Count of instructions in progress that have been sent off to the IQ 3582292SN/A * and ROB, but are not yet included in their occupancy counts. 3592292SN/A */ 3602292SN/A int instsInProgress[Impl::MaxThreads]; 3612292SN/A 36210239Sbinhpham@cs.rutgers.edu /** Count of Load instructions in progress that have been sent off to the IQ 36310239Sbinhpham@cs.rutgers.edu * and ROB, but are not yet included in their occupancy counts. 36410239Sbinhpham@cs.rutgers.edu */ 36510239Sbinhpham@cs.rutgers.edu int loadsInProgress[Impl::MaxThreads]; 36610239Sbinhpham@cs.rutgers.edu 36710239Sbinhpham@cs.rutgers.edu /** Count of Store instructions in progress that have been sent off to the IQ 36810239Sbinhpham@cs.rutgers.edu * and ROB, but are not yet included in their occupancy counts. 36910239Sbinhpham@cs.rutgers.edu */ 37010239Sbinhpham@cs.rutgers.edu int storesInProgress[Impl::MaxThreads]; 37110239Sbinhpham@cs.rutgers.edu 3722292SN/A /** Variable that tracks if decode has written to the time buffer this 3732292SN/A * cycle. Used to tell CPU if there is activity this cycle. 3742292SN/A */ 3752292SN/A bool wroteToTimeBuffer; 3762292SN/A 3772292SN/A /** Structures whose free entries impact the amount of instructions that 3782292SN/A * can be renamed. 3792292SN/A */ 3802292SN/A struct FreeEntries { 3812292SN/A unsigned iqEntries; 3822292SN/A unsigned robEntries; 38310239Sbinhpham@cs.rutgers.edu unsigned lqEntries; 38410239Sbinhpham@cs.rutgers.edu unsigned sqEntries; 3852292SN/A }; 3862292SN/A 3872292SN/A /** Per-thread tracking of the number of free entries of back-end 3882292SN/A * structures. 3892292SN/A */ 3902292SN/A FreeEntries freeEntries[Impl::MaxThreads]; 3912292SN/A 3922292SN/A /** Records if the ROB is empty. In SMT mode the ROB may be dynamically 3932292SN/A * partitioned between threads, so the ROB must tell rename when it is 3942292SN/A * empty. 3952292SN/A */ 3962292SN/A bool emptyROB[Impl::MaxThreads]; 3972292SN/A 3982292SN/A /** Source of possible stalls. */ 3992292SN/A struct Stalls { 4002292SN/A bool iew; 4012292SN/A bool commit; 4022292SN/A }; 4032292SN/A 4042292SN/A /** Tracks which stages are telling decode to stall. */ 4052292SN/A Stalls stalls[Impl::MaxThreads]; 4062292SN/A 4072301SN/A /** The serialize instruction that rename has stalled on. */ 4082301SN/A DynInstPtr serializeInst[Impl::MaxThreads]; 4092292SN/A 4102292SN/A /** Records if rename needs to serialize on the next instruction for any 4112292SN/A * thread. 4122292SN/A */ 4132292SN/A bool serializeOnNextInst[Impl::MaxThreads]; 4142292SN/A 4151060SN/A /** Delay between iew and rename, in ticks. */ 4161060SN/A int iewToRenameDelay; 4171060SN/A 4181060SN/A /** Delay between decode and rename, in ticks. */ 4191060SN/A int decodeToRenameDelay; 4201060SN/A 4211060SN/A /** Delay between commit and rename, in ticks. */ 4221060SN/A unsigned commitToRenameDelay; 4231060SN/A 4241060SN/A /** Rename width, in instructions. */ 4251060SN/A unsigned renameWidth; 4261060SN/A 4271060SN/A /** Commit width, in instructions. Used so rename knows how many 4281060SN/A * instructions might have freed registers in the previous cycle. 4291060SN/A */ 4301060SN/A unsigned commitWidth; 4311061SN/A 4322292SN/A /** The index of the instruction in the time buffer to IEW that rename is 4332292SN/A * currently using. 4341061SN/A */ 4352292SN/A unsigned toIEWIndex; 4361062SN/A 4372292SN/A /** Whether or not rename needs to block this cycle. */ 4382292SN/A bool blockThisCycle; 4392292SN/A 4403788Sgblack@eecs.umich.edu /** Whether or not rename needs to resume a serialize instruction 4413788Sgblack@eecs.umich.edu * after squashing. */ 4423788Sgblack@eecs.umich.edu bool resumeSerialize; 4433788Sgblack@eecs.umich.edu 4443798Sgblack@eecs.umich.edu /** Whether or not rename needs to resume clearing out the skidbuffer 4453798Sgblack@eecs.umich.edu * after squashing. */ 4463798Sgblack@eecs.umich.edu bool resumeUnblocking; 4473798Sgblack@eecs.umich.edu 4482292SN/A /** The number of threads active in rename. */ 4496221Snate@binkert.org ThreadID numThreads; 4502292SN/A 4512292SN/A /** The maximum skid buffer size. */ 4522292SN/A unsigned skidBufferMax; 4532292SN/A 4542361SN/A PhysRegIndex maxPhysicalRegs; 4552361SN/A 4562292SN/A /** Enum to record the source of a structure full stall. Can come from 4572292SN/A * either ROB, IQ, LSQ, and it is priortized in that order. 4582292SN/A */ 4592292SN/A enum FullSource { 4602292SN/A ROB, 4612292SN/A IQ, 46210239Sbinhpham@cs.rutgers.edu LQ, 46310239Sbinhpham@cs.rutgers.edu SQ, 4642292SN/A NONE 4652292SN/A }; 4662292SN/A 4672292SN/A /** Function used to increment the stat that corresponds to the source of 4682292SN/A * the stall. 4692292SN/A */ 4702292SN/A inline void incrFullStat(const FullSource &source); 4712292SN/A 4722292SN/A /** Stat for total number of cycles spent squashing. */ 4735999Snate@binkert.org Stats::Scalar renameSquashCycles; 4742292SN/A /** Stat for total number of cycles spent idle. */ 4755999Snate@binkert.org Stats::Scalar renameIdleCycles; 4762292SN/A /** Stat for total number of cycles spent blocking. */ 4775999Snate@binkert.org Stats::Scalar renameBlockCycles; 4782301SN/A /** Stat for total number of cycles spent stalling for a serializing inst. */ 4795999Snate@binkert.org Stats::Scalar renameSerializeStallCycles; 4802292SN/A /** Stat for total number of cycles spent running normally. */ 4815999Snate@binkert.org Stats::Scalar renameRunCycles; 4822292SN/A /** Stat for total number of cycles spent unblocking. */ 4835999Snate@binkert.org Stats::Scalar renameUnblockCycles; 4842292SN/A /** Stat for total number of renamed instructions. */ 4855999Snate@binkert.org Stats::Scalar renameRenamedInsts; 4862292SN/A /** Stat for total number of squashed instructions that rename discards. */ 4875999Snate@binkert.org Stats::Scalar renameSquashedInsts; 4882292SN/A /** Stat for total number of times that the ROB starts a stall in rename. */ 4895999Snate@binkert.org Stats::Scalar renameROBFullEvents; 4902292SN/A /** Stat for total number of times that the IQ starts a stall in rename. */ 4915999Snate@binkert.org Stats::Scalar renameIQFullEvents; 49210239Sbinhpham@cs.rutgers.edu /** Stat for total number of times that the LQ starts a stall in rename. */ 49310239Sbinhpham@cs.rutgers.edu Stats::Scalar renameLQFullEvents; 49410239Sbinhpham@cs.rutgers.edu /** Stat for total number of times that the SQ starts a stall in rename. */ 49510239Sbinhpham@cs.rutgers.edu Stats::Scalar renameSQFullEvents; 4962292SN/A /** Stat for total number of times that rename runs out of free registers 4972292SN/A * to use to rename. */ 4985999Snate@binkert.org Stats::Scalar renameFullRegistersEvents; 4992292SN/A /** Stat for total number of renamed destination registers. */ 5005999Snate@binkert.org Stats::Scalar renameRenamedOperands; 5012292SN/A /** Stat for total number of source register rename lookups. */ 5025999Snate@binkert.org Stats::Scalar renameRenameLookups; 5037897Shestness@cs.utexas.edu Stats::Scalar intRenameLookups; 5047897Shestness@cs.utexas.edu Stats::Scalar fpRenameLookups; 5052292SN/A /** Stat for total number of committed renaming mappings. */ 5065999Snate@binkert.org Stats::Scalar renameCommittedMaps; 5072292SN/A /** Stat for total number of mappings that were undone due to a squash. */ 5085999Snate@binkert.org Stats::Scalar renameUndoneMaps; 5092348SN/A /** Number of serialize instructions handled. */ 5105999Snate@binkert.org Stats::Scalar renamedSerializing; 5112348SN/A /** Number of instructions marked as temporarily serializing. */ 5125999Snate@binkert.org Stats::Scalar renamedTempSerializing; 5132348SN/A /** Number of instructions inserted into skid buffers. */ 5145999Snate@binkert.org Stats::Scalar renameSkidInsts; 5151060SN/A}; 5161060SN/A 5172292SN/A#endif // __CPU_O3_RENAME_HH__ 518