regfile.hh revision 6314:781969fbeca9 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Gabe Black
30 */
31
32#ifndef __CPU_O3_REGFILE_HH__
33#define __CPU_O3_REGFILE_HH__
34
35#include "arch/isa_traits.hh"
36#include "arch/regfile.hh"
37#include "arch/types.hh"
38#include "base/trace.hh"
39#include "config/full_system.hh"
40#include "cpu/o3/comm.hh"
41
42#if FULL_SYSTEM
43#include "arch/kernel_stats.hh"
44#endif
45
46#include <vector>
47
48/**
49 * Simple physical register file class.
50 * Right now this is specific to Alpha until we decide if/how to make things
51 * generic enough to support other ISAs.
52 */
53template <class Impl>
54class PhysRegFile
55{
56  protected:
57    typedef TheISA::IntReg IntReg;
58    typedef TheISA::FloatReg FloatReg;
59    typedef TheISA::FloatRegBits FloatRegBits;
60
61    typedef union {
62        FloatReg d;
63        FloatRegBits q;
64    } PhysFloatReg;
65
66    // Note that most of the definitions of the IntReg, FloatReg, etc. exist
67    // within the Impl/ISA class and not within this PhysRegFile class.
68
69    // Will make these registers public for now, but they probably should
70    // be private eventually with some accessor functions.
71  public:
72    typedef typename Impl::O3CPU O3CPU;
73
74    /**
75     * Constructs a physical register file with the specified amount of
76     * integer and floating point registers.
77     */
78    PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
79                unsigned _numPhysicalFloatRegs);
80
81    //Everything below should be pretty well identical to the normal
82    //register file that exists within AlphaISA class.
83    //The duplication is unfortunate but it's better than having
84    //different ways to access certain registers.
85
86    /** Reads an integer register. */
87    uint64_t readIntReg(PhysRegIndex reg_idx)
88    {
89        assert(reg_idx < numPhysicalIntRegs);
90
91        DPRINTF(IEW, "RegFile: Access to int register %i, has data "
92                "%#x\n", int(reg_idx), intRegFile[reg_idx]);
93        return intRegFile[reg_idx];
94    }
95
96    /** Reads a floating point register (double precision). */
97    FloatReg readFloatReg(PhysRegIndex reg_idx)
98    {
99        // Remove the base Float reg dependency.
100        reg_idx = reg_idx - numPhysicalIntRegs;
101
102        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
103
104        FloatReg floatReg = floatRegFile[reg_idx].d;
105
106        DPRINTF(IEW, "RegFile: Access to float register %i, has "
107                "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q);
108
109        return floatReg;
110    }
111
112    FloatRegBits readFloatRegBits(PhysRegIndex reg_idx)
113    {
114        // Remove the base Float reg dependency.
115        reg_idx = reg_idx - numPhysicalIntRegs;
116
117        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
118
119        FloatRegBits floatRegBits = floatRegFile[reg_idx].q;
120
121        DPRINTF(IEW, "RegFile: Access to float register %i as int, "
122                "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits);
123
124        return floatRegBits;
125    }
126
127    /** Sets an integer register to the given value. */
128    void setIntReg(PhysRegIndex reg_idx, uint64_t val)
129    {
130        assert(reg_idx < numPhysicalIntRegs);
131
132        DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
133                int(reg_idx), val);
134
135        if (reg_idx != TheISA::ZeroReg)
136            intRegFile[reg_idx] = val;
137    }
138
139    /** Sets a double precision floating point register to the given value. */
140    void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
141    {
142        // Remove the base Float reg dependency.
143        reg_idx = reg_idx - numPhysicalIntRegs;
144
145        assert(reg_idx < numPhysicalFloatRegs);
146
147        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
148                int(reg_idx), (uint64_t)val);
149
150#if THE_ISA == ALPHA_ISA
151        if (reg_idx != TheISA::ZeroReg)
152#endif
153            floatRegFile[reg_idx].d = val;
154    }
155
156    void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
157    {
158        // Remove the base Float reg dependency.
159        reg_idx = reg_idx - numPhysicalIntRegs;
160
161        assert(reg_idx < numPhysicalFloatRegs);
162
163        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
164                int(reg_idx), (uint64_t)val);
165
166        floatRegFile[reg_idx].q = val;
167    }
168
169  public:
170    /** (signed) integer register file. */
171    IntReg *intRegFile;
172
173    /** Floating point register file. */
174    PhysFloatReg *floatRegFile;
175
176#if FULL_SYSTEM
177  private:
178    int intrflag;                       // interrupt flag
179#endif
180
181  private:
182    /** CPU pointer. */
183    O3CPU *cpu;
184
185  public:
186    /** Number of physical integer registers. */
187    unsigned numPhysicalIntRegs;
188    /** Number of physical floating point registers. */
189    unsigned numPhysicalFloatRegs;
190};
191
192template <class Impl>
193PhysRegFile<Impl>::PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
194                               unsigned _numPhysicalFloatRegs)
195    : cpu(_cpu), numPhysicalIntRegs(_numPhysicalIntRegs),
196      numPhysicalFloatRegs(_numPhysicalFloatRegs)
197{
198    intRegFile = new IntReg[numPhysicalIntRegs];
199    floatRegFile = new PhysFloatReg[numPhysicalFloatRegs];
200
201    memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs);
202    memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs);
203}
204
205#endif
206