regfile.hh revision 2733
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Gabe Black 30 */ 31 32#ifndef __CPU_O3_REGFILE_HH__ 33#define __CPU_O3_REGFILE_HH__ 34 35#include "arch/isa_traits.hh" 36#include "arch/faults.hh" 37#include "arch/types.hh" 38#include "base/trace.hh" 39#include "config/full_system.hh" 40#include "cpu/o3/comm.hh" 41 42#if FULL_SYSTEM 43#include "kern/kernel_stats.hh" 44 45#endif 46 47#include <vector> 48 49/** 50 * Simple physical register file class. 51 * Right now this is specific to Alpha until we decide if/how to make things 52 * generic enough to support other ISAs. 53 */ 54template <class Impl> 55class PhysRegFile 56{ 57 protected: 58 typedef TheISA::IntReg IntReg; 59 typedef TheISA::FloatReg FloatReg; 60 typedef TheISA::FloatRegBits FloatRegBits; 61 typedef TheISA::MiscRegFile MiscRegFile; 62 typedef TheISA::MiscReg MiscReg; 63 64 typedef union { 65 FloatReg d; 66 FloatRegBits q; 67 } PhysFloatReg; 68 69 // Note that most of the definitions of the IntReg, FloatReg, etc. exist 70 // within the Impl/ISA class and not within this PhysRegFile class. 71 72 // Will make these registers public for now, but they probably should 73 // be private eventually with some accessor functions. 74 public: 75 typedef typename Impl::O3CPU O3CPU; 76 77 /** 78 * Constructs a physical register file with the specified amount of 79 * integer and floating point registers. 80 */ 81 PhysRegFile(unsigned _numPhysicalIntRegs, 82 unsigned _numPhysicalFloatRegs); 83 84 //Everything below should be pretty well identical to the normal 85 //register file that exists within AlphaISA class. 86 //The duplication is unfortunate but it's better than having 87 //different ways to access certain registers. 88 89 //Add these in later when everything else is in place 90// void serialize(std::ostream &os); 91// void unserialize(Checkpoint *cp, const std::string §ion); 92 93 /** Reads an integer register. */ 94 uint64_t readIntReg(PhysRegIndex reg_idx) 95 { 96 assert(reg_idx < numPhysicalIntRegs); 97 98 DPRINTF(IEW, "RegFile: Access to int register %i, has data " 99 "%#x\n", int(reg_idx), intRegFile[reg_idx]); 100 return intRegFile[reg_idx]; 101 } 102 103 FloatReg readFloatReg(PhysRegIndex reg_idx, int width) 104 { 105 // Remove the base Float reg dependency. 106 reg_idx = reg_idx - numPhysicalIntRegs; 107 108 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 109 110 FloatReg floatReg = floatRegFile[reg_idx].d; 111 112 DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has " 113 "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q); 114 115 return floatReg; 116 } 117 118 /** Reads a floating point register (double precision). */ 119 FloatReg readFloatReg(PhysRegIndex reg_idx) 120 { 121 // Remove the base Float reg dependency. 122 reg_idx = reg_idx - numPhysicalIntRegs; 123 124 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 125 126 FloatReg floatReg = floatRegFile[reg_idx].d; 127 128 DPRINTF(IEW, "RegFile: Access to float register %i, has " 129 "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q); 130 131 return floatReg; 132 } 133 134 /** Reads a floating point register as an integer. */ 135 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width) 136 { 137 // Remove the base Float reg dependency. 138 reg_idx = reg_idx - numPhysicalIntRegs; 139 140 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 141 142 FloatRegBits floatRegBits = floatRegFile[reg_idx].q; 143 144 DPRINTF(IEW, "RegFile: Access to float register %i as int, " 145 "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits); 146 147 return floatRegBits; 148 } 149 150 FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) 151 { 152 // Remove the base Float reg dependency. 153 reg_idx = reg_idx - numPhysicalIntRegs; 154 155 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 156 157 FloatRegBits floatRegBits = floatRegFile[reg_idx].q; 158 159 DPRINTF(IEW, "RegFile: Access to float register %i as int, " 160 "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits); 161 162 return floatRegBits; 163 } 164 165 /** Sets an integer register to the given value. */ 166 void setIntReg(PhysRegIndex reg_idx, uint64_t val) 167 { 168 assert(reg_idx < numPhysicalIntRegs); 169 170 DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n", 171 int(reg_idx), val); 172 173 if (reg_idx != TheISA::ZeroReg) 174 intRegFile[reg_idx] = val; 175 } 176 177 /** Sets a single precision floating point register to the given value. */ 178 void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width) 179 { 180 // Remove the base Float reg dependency. 181 reg_idx = reg_idx - numPhysicalIntRegs; 182 183 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 184 185 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 186 int(reg_idx), (uint64_t)val); 187 188 if (reg_idx != TheISA::ZeroReg) 189 floatRegFile[reg_idx].d = val; 190 } 191 192 /** Sets a double precision floating point register to the given value. */ 193 void setFloatReg(PhysRegIndex reg_idx, FloatReg val) 194 { 195 // Remove the base Float reg dependency. 196 reg_idx = reg_idx - numPhysicalIntRegs; 197 198 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 199 200 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 201 int(reg_idx), (uint64_t)val); 202 203 if (reg_idx != TheISA::ZeroReg) 204 floatRegFile[reg_idx].d = val; 205 } 206 207 /** Sets a floating point register to the given integer value. */ 208 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width) 209 { 210 // Remove the base Float reg dependency. 211 reg_idx = reg_idx - numPhysicalIntRegs; 212 213 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 214 215 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 216 int(reg_idx), (uint64_t)val); 217 218 floatRegFile[reg_idx].q = val; 219 } 220 221 void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) 222 { 223 // Remove the base Float reg dependency. 224 reg_idx = reg_idx - numPhysicalIntRegs; 225 226 assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 227 228 DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 229 int(reg_idx), (uint64_t)val); 230 231 floatRegFile[reg_idx].q = val; 232 } 233 234 MiscReg readMiscReg(int misc_reg, unsigned thread_id) 235 { 236 return miscRegs[thread_id].readReg(misc_reg); 237 } 238 239 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, 240 unsigned thread_id) 241 { 242 return miscRegs[thread_id].readRegWithEffect(misc_reg, fault, 243 cpu->tcBase(thread_id)); 244 } 245 246 Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id) 247 { 248 return miscRegs[thread_id].setReg(misc_reg, val); 249 } 250 251 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, 252 unsigned thread_id) 253 { 254 return miscRegs[thread_id].setRegWithEffect(misc_reg, val, 255 cpu->tcBase(thread_id)); 256 } 257 258#if FULL_SYSTEM 259 int readIntrFlag() { return intrflag; } 260 /** Sets an interrupt flag. */ 261 void setIntrFlag(int val) { intrflag = val; } 262#endif 263 264 public: 265 /** (signed) integer register file. */ 266 IntReg *intRegFile; 267 268 /** Floating point register file. */ 269 PhysFloatReg *floatRegFile; 270 271 /** Miscellaneous register file. */ 272 MiscRegFile miscRegs[Impl::MaxThreads]; 273 274#if FULL_SYSTEM 275 private: 276 int intrflag; // interrupt flag 277#endif 278 279 private: 280 /** CPU pointer. */ 281 O3CPU *cpu; 282 283 public: 284 /** Sets the CPU pointer. */ 285 void setCPU(O3CPU *cpu_ptr) { cpu = cpu_ptr; } 286 287 /** Number of physical integer registers. */ 288 unsigned numPhysicalIntRegs; 289 /** Number of physical floating point registers. */ 290 unsigned numPhysicalFloatRegs; 291}; 292 293template <class Impl> 294PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs, 295 unsigned _numPhysicalFloatRegs) 296 : numPhysicalIntRegs(_numPhysicalIntRegs), 297 numPhysicalFloatRegs(_numPhysicalFloatRegs) 298{ 299 intRegFile = new IntReg[numPhysicalIntRegs]; 300 floatRegFile = new PhysFloatReg[numPhysicalFloatRegs]; 301 302 for (int i = 0; i < Impl::MaxThreads; ++i) { 303 miscRegs[i].clear(); 304 } 305 306 memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs); 307 memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs); 308} 309 310#endif 311