regfile.hh revision 13611:c8b7847b4171 
1/*
2 * Copyright (c) 2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * Copyright (c) 2013 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Gabe Black
43 */
44
45#ifndef __CPU_O3_REGFILE_HH__
46#define __CPU_O3_REGFILE_HH__
47
48#include <vector>
49
50#include "arch/isa_traits.hh"
51#include "arch/kernel_stats.hh"
52#include "arch/types.hh"
53#include "base/trace.hh"
54#include "config/the_isa.hh"
55#include "cpu/o3/comm.hh"
56#include "debug/IEW.hh"
57#include "enums/VecRegRenameMode.hh"
58
59class UnifiedFreeList;
60
61/**
62 * Simple physical register file class.
63 */
64class PhysRegFile
65{
66  private:
67
68    typedef TheISA::CCReg CCReg;
69    using VecElem = TheISA::VecElem;
70    using VecRegContainer = TheISA::VecRegContainer;
71    using PhysIds = std::vector<PhysRegId>;
72    using VecMode = Enums::VecRegRenameMode;
73    using VecPredRegContainer = TheISA::VecPredRegContainer;
74  public:
75    using IdRange = std::pair<PhysIds::const_iterator,
76                              PhysIds::const_iterator>;
77  private:
78    static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
79
80    /** Integer register file. */
81    std::vector<RegVal> intRegFile;
82    std::vector<PhysRegId> intRegIds;
83
84    /** Floating point register file. */
85    std::vector<RegVal> floatRegFile;
86    std::vector<PhysRegId> floatRegIds;
87
88    /** Vector register file. */
89    std::vector<VecRegContainer> vectorRegFile;
90    std::vector<PhysRegId> vecRegIds;
91    std::vector<PhysRegId> vecElemIds;
92
93    /** Predicate register file. */
94    std::vector<VecPredRegContainer> vecPredRegFile;
95    std::vector<PhysRegId> vecPredRegIds;
96
97    /** Condition-code register file. */
98    std::vector<CCReg> ccRegFile;
99    std::vector<PhysRegId> ccRegIds;
100
101    /** Misc Reg Ids */
102    std::vector<PhysRegId> miscRegIds;
103
104    /**
105     * Number of physical general purpose registers
106     */
107    unsigned numPhysicalIntRegs;
108
109    /**
110     * Number of physical floating point registers
111     */
112    unsigned numPhysicalFloatRegs;
113
114    /**
115     * Number of physical vector registers
116     */
117    unsigned numPhysicalVecRegs;
118
119    /**
120     * Number of physical vector element registers
121     */
122    unsigned numPhysicalVecElemRegs;
123
124    /**
125     * Number of physical predicate registers
126     */
127    unsigned numPhysicalVecPredRegs;
128
129    /**
130     * Number of physical CC registers
131     */
132    unsigned numPhysicalCCRegs;
133
134    /** Total number of physical registers. */
135    unsigned totalNumRegs;
136
137    /** Mode in which vector registers are addressed. */
138    VecMode vecMode;
139
140  public:
141    /**
142     * Constructs a physical register file with the specified amount of
143     * integer and floating point registers.
144     */
145    PhysRegFile(unsigned _numPhysicalIntRegs,
146                unsigned _numPhysicalFloatRegs,
147                unsigned _numPhysicalVecRegs,
148                unsigned _numPhysicalVecPredRegs,
149                unsigned _numPhysicalCCRegs,
150                VecMode vmode
151                );
152
153    /**
154     * Destructor to free resources
155     */
156    ~PhysRegFile() {}
157
158    /** Initialize the free list */
159    void initFreeList(UnifiedFreeList *freeList);
160
161    /** @return the number of integer physical registers. */
162    unsigned numIntPhysRegs() const { return numPhysicalIntRegs; }
163
164    /** @return the number of floating-point physical registers. */
165    unsigned numFloatPhysRegs() const { return numPhysicalFloatRegs; }
166    /** @return the number of vector physical registers. */
167    unsigned numVecPhysRegs() const { return numPhysicalVecRegs; }
168    /** @return the number of predicate physical registers. */
169    unsigned numPredPhysRegs() const { return numPhysicalVecPredRegs; }
170
171    /** @return the number of vector physical registers. */
172    unsigned numVecElemPhysRegs() const { return numPhysicalVecElemRegs; }
173
174    /** @return the number of condition-code physical registers. */
175    unsigned numCCPhysRegs() const { return numPhysicalCCRegs; }
176
177    /** @return the total number of physical registers. */
178    unsigned totalNumPhysRegs() const { return totalNumRegs; }
179
180    /** Gets a misc register PhysRegIdPtr. */
181    PhysRegIdPtr getMiscRegId(RegIndex reg_idx) {
182        return &miscRegIds[reg_idx];
183    }
184
185    /** Reads an integer register. */
186    RegVal
187    readIntReg(PhysRegIdPtr phys_reg) const
188    {
189        assert(phys_reg->isIntPhysReg());
190
191        DPRINTF(IEW, "RegFile: Access to int register %i, has data "
192                "%#x\n", phys_reg->index(), intRegFile[phys_reg->index()]);
193        return intRegFile[phys_reg->index()];
194    }
195
196    RegVal
197    readFloatReg(PhysRegIdPtr phys_reg) const
198    {
199        assert(phys_reg->isFloatPhysReg());
200
201        RegVal floatRegBits = floatRegFile[phys_reg->index()];
202
203        DPRINTF(IEW, "RegFile: Access to float register %i as int, "
204                "has data %#x\n", phys_reg->index(), floatRegBits);
205
206        return floatRegBits;
207    }
208
209    /** Reads a vector register. */
210    const VecRegContainer &
211    readVecReg(PhysRegIdPtr phys_reg) const
212    {
213        assert(phys_reg->isVectorPhysReg());
214
215        DPRINTF(IEW, "RegFile: Access to vector register %i, has "
216                "data %s\n", int(phys_reg->index()),
217                vectorRegFile[phys_reg->index()].print());
218
219        return vectorRegFile[phys_reg->index()];
220    }
221
222    /** Reads a vector register for modification. */
223    VecRegContainer &
224    getWritableVecReg(PhysRegIdPtr phys_reg)
225    {
226        /* const_cast for not duplicating code above. */
227        return const_cast<VecRegContainer&>(readVecReg(phys_reg));
228    }
229
230    /** Reads a vector register lane. */
231    template <typename VecElem, int LaneIdx>
232    VecLaneT<VecElem, true>
233    readVecLane(PhysRegIdPtr phys_reg) const
234    {
235        return readVecReg(phys_reg).laneView<VecElem, LaneIdx>();
236    }
237
238    /** Reads a vector register lane. */
239    template <typename VecElem>
240    VecLaneT<VecElem, true>
241    readVecLane(PhysRegIdPtr phys_reg) const
242    {
243        return readVecReg(phys_reg).laneView<VecElem>(phys_reg->elemIndex());
244    }
245
246    /** Get a vector register lane for modification. */
247    template <typename LD>
248    void
249    setVecLane(PhysRegIdPtr phys_reg, const LD& val)
250    {
251        assert(phys_reg->isVectorPhysReg());
252
253        DPRINTF(IEW, "RegFile: Setting vector register %i[%d] to %lx\n",
254                int(phys_reg->index()), phys_reg->elemIndex(), val);
255
256        vectorRegFile[phys_reg->index()].laneView<typename LD::UnderlyingType>(
257                phys_reg->elemIndex()) = val;
258    }
259
260    /** Reads a vector element. */
261    const VecElem &
262    readVecElem(PhysRegIdPtr phys_reg) const
263    {
264        assert(phys_reg->isVectorPhysElem());
265        auto ret = vectorRegFile[phys_reg->index()].as<VecElem>();
266        const VecElem& val = ret[phys_reg->elemIndex()];
267        DPRINTF(IEW, "RegFile: Access to element %d of vector register %i,"
268                " has data %#x\n", phys_reg->elemIndex(),
269                int(phys_reg->index()), val);
270
271        return val;
272    }
273
274    /** Reads a predicate register. */
275    const VecPredRegContainer& readVecPredReg(PhysRegIdPtr phys_reg) const
276    {
277        assert(phys_reg->isVecPredPhysReg());
278
279        DPRINTF(IEW, "RegFile: Access to predicate register %i, has "
280                "data %s\n", int(phys_reg->index()),
281                vecPredRegFile[phys_reg->index()].print());
282
283        return vecPredRegFile[phys_reg->index()];
284    }
285
286    VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr phys_reg)
287    {
288        /* const_cast for not duplicating code above. */
289        return const_cast<VecPredRegContainer&>(readVecPredReg(phys_reg));
290    }
291
292    /** Reads a condition-code register. */
293    CCReg
294    readCCReg(PhysRegIdPtr phys_reg)
295    {
296        assert(phys_reg->isCCPhysReg());
297
298        DPRINTF(IEW, "RegFile: Access to cc register %i, has "
299                "data %#x\n", phys_reg->index(),
300                ccRegFile[phys_reg->index()]);
301
302        return ccRegFile[phys_reg->index()];
303    }
304
305    /** Sets an integer register to the given value. */
306    void
307    setIntReg(PhysRegIdPtr phys_reg, RegVal val)
308    {
309        assert(phys_reg->isIntPhysReg());
310
311        DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n",
312                phys_reg->index(), val);
313
314        if (!phys_reg->isZeroReg())
315            intRegFile[phys_reg->index()] = val;
316    }
317
318    void
319    setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
320    {
321        assert(phys_reg->isFloatPhysReg());
322
323        DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
324                phys_reg->index(), (uint64_t)val);
325
326        if (!phys_reg->isZeroReg())
327            floatRegFile[phys_reg->index()] = val;
328    }
329
330    /** Sets a vector register to the given value. */
331    void
332    setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
333    {
334        assert(phys_reg->isVectorPhysReg());
335
336        DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n",
337                int(phys_reg->index()), val.print());
338
339        vectorRegFile[phys_reg->index()] = val;
340    }
341
342    /** Sets a vector register to the given value. */
343    void
344    setVecElem(PhysRegIdPtr phys_reg, const VecElem val)
345    {
346        assert(phys_reg->isVectorPhysElem());
347
348        DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to"
349                " %#x\n", phys_reg->elemIndex(), int(phys_reg->index()), val);
350
351        vectorRegFile[phys_reg->index()].as<VecElem>()[phys_reg->elemIndex()] =
352                val;
353    }
354
355    /** Sets a predicate register to the given value. */
356    void setVecPredReg(PhysRegIdPtr phys_reg, const VecPredRegContainer& val)
357    {
358        assert(phys_reg->isVecPredPhysReg());
359
360        DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
361                int(phys_reg->index()), val.print());
362
363        vecPredRegFile[phys_reg->index()] = val;
364    }
365
366    /** Sets a condition-code register to the given value. */
367    void
368    setCCReg(PhysRegIdPtr phys_reg, CCReg val)
369    {
370        assert(phys_reg->isCCPhysReg());
371
372        DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n",
373                phys_reg->index(), (uint64_t)val);
374
375        ccRegFile[phys_reg->index()] = val;
376    }
377
378    /** Get the PhysRegIds of the elems of a vector register.
379     * Auxiliary function to transition from Full vector mode to Elem mode.
380     */
381    IdRange getRegElemIds(PhysRegIdPtr reg);
382
383    /**
384     * Get the PhysRegIds of the elems of all vector registers.
385     * Auxiliary function to transition from Full vector mode to Elem mode
386     * and to initialise the rename map.
387     */
388    IdRange getRegIds(RegClass cls);
389
390    /**
391     * Get the true physical register id.
392     * As many parts work with PhysRegIdPtr, we need to be able to produce
393     * the pointer out of just class and register idx.
394     */
395    PhysRegIdPtr getTrueId(PhysRegIdPtr reg);
396};
397
398
399#endif //__CPU_O3_REGFILE_HH__
400