regfile.hh revision 12109
16167SN/A/* 26167SN/A * Copyright (c) 2016 ARM Limited 36167SN/A * All rights reserved 410036SAli.Saidi@ARM.com * 58835SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 610036SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77935SN/A * property including but not limited to intellectual property relating 87935SN/A * to a hardware implementation of the functionality of the software 97935SN/A * licensed hereunder. You may use the software subject to the license 106167SN/A * terms below provided that you ensure that this notice is replicated 116167SN/A * unmodified and in its entirety in all distributions of the software, 126167SN/A * modified or unmodified, in source code or in binary form. 139864Snilay@cs.wisc.edu * 148835SAli.Saidi@ARM.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 159864Snilay@cs.wisc.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 169864Snilay@cs.wisc.edu * All rights reserved. 1710036SAli.Saidi@ARM.com * 188835SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 198835SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 208835SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 217935SN/A * notice, this list of conditions and the following disclaimer; 229864Snilay@cs.wisc.edu * redistributions in binary form must reproduce the above copyright 238721SN/A * notice, this list of conditions and the following disclaimer in the 248721SN/A * documentation and/or other materials provided with the distribution; 258835SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 268835SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 277935SN/A * this software without specific prior written permission. 287935SN/A * 297935SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307935SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317935SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327935SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337935SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 348983Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356167SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 369864Snilay@cs.wisc.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 379864Snilay@cs.wisc.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 389864Snilay@cs.wisc.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3910036SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 409864Snilay@cs.wisc.edu * 419864Snilay@cs.wisc.edu * Authors: Kevin Lim 426167SN/A * Gabe Black 436167SN/A */ 449864Snilay@cs.wisc.edu 456167SN/A#ifndef __CPU_O3_REGFILE_HH__ 469864Snilay@cs.wisc.edu#define __CPU_O3_REGFILE_HH__ 476167SN/A 486167SN/A#include <vector> 498835SAli.Saidi@ARM.com 506167SN/A#include "arch/isa_traits.hh" 516167SN/A#include "arch/kernel_stats.hh" 5210036SAli.Saidi@ARM.com#include "arch/types.hh" 536167SN/A#include "base/trace.hh" 546167SN/A#include "config/the_isa.hh" 558835SAli.Saidi@ARM.com#include "cpu/o3/comm.hh" 569469Snilay@cs.wisc.edu#include "debug/IEW.hh" 576167SN/A#include "enums/VecRegRenameMode.hh" 586167SN/A 596167SN/Aclass UnifiedFreeList; 606167SN/A 616167SN/A/** 626167SN/A * Simple physical register file class. 638835SAli.Saidi@ARM.com */ 646167SN/Aclass PhysRegFile 659864Snilay@cs.wisc.edu{ 669469Snilay@cs.wisc.edu private: 676167SN/A 686167SN/A typedef TheISA::IntReg IntReg; 696167SN/A typedef TheISA::FloatReg FloatReg; 709469Snilay@cs.wisc.edu typedef TheISA::FloatRegBits FloatRegBits; 719469Snilay@cs.wisc.edu typedef TheISA::CCReg CCReg; 726167SN/A using VecElem = TheISA::VecElem; 739864Snilay@cs.wisc.edu using VecRegContainer = TheISA::VecRegContainer; 749864Snilay@cs.wisc.edu using PhysIds = std::vector<PhysRegId>; 759864Snilay@cs.wisc.edu using VecMode = Enums::VecRegRenameMode; 7610036SAli.Saidi@ARM.com public: 779864Snilay@cs.wisc.edu using IdRange = std::pair<PhysIds::const_iterator, 789864Snilay@cs.wisc.edu PhysIds::const_iterator>; 796167SN/A private: 806167SN/A static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg; 8110036SAli.Saidi@ARM.com 826167SN/A typedef union { 836167SN/A FloatReg d; 848835SAli.Saidi@ARM.com FloatRegBits q; 858835SAli.Saidi@ARM.com } PhysFloatReg; 8610036SAli.Saidi@ARM.com 878835SAli.Saidi@ARM.com /** Integer register file. */ 889469Snilay@cs.wisc.edu std::vector<IntReg> intRegFile; 899469Snilay@cs.wisc.edu std::vector<PhysRegId> intRegIds; 9010036SAli.Saidi@ARM.com 919469Snilay@cs.wisc.edu /** Floating point register file. */ 926167SN/A std::vector<PhysFloatReg> floatRegFile; 936167SN/A std::vector<PhysRegId> floatRegIds; 9410036SAli.Saidi@ARM.com 956167SN/A /** Vector register file. */ 966167SN/A std::vector<VecRegContainer> vectorRegFile; 976167SN/A std::vector<PhysRegId> vecRegIds; 986167SN/A std::vector<PhysRegId> vecElemIds; 9910036SAli.Saidi@ARM.com 1006167SN/A /** Condition-code register file. */ 1016167SN/A std::vector<CCReg> ccRegFile; 1026167SN/A std::vector<PhysRegId> ccRegIds; 1036167SN/A 1046167SN/A /** Misc Reg Ids */ 1056167SN/A std::vector<PhysRegId> miscRegIds; 1066167SN/A 1076167SN/A /** 1086167SN/A * Number of physical general purpose registers 10910036SAli.Saidi@ARM.com */ 11010036SAli.Saidi@ARM.com unsigned numPhysicalIntRegs; 1116167SN/A 1126167SN/A /** 1136167SN/A * Number of physical floating point registers 1146167SN/A */ 1156167SN/A unsigned numPhysicalFloatRegs; 1166167SN/A 1176167SN/A /** 1186167SN/A * Number of physical vector registers 1196167SN/A */ 1206167SN/A unsigned numPhysicalVecRegs; 1219469Snilay@cs.wisc.edu 1229469Snilay@cs.wisc.edu /** 1239469Snilay@cs.wisc.edu * Number of physical vector element registers 1249864Snilay@cs.wisc.edu */ 1259864Snilay@cs.wisc.edu unsigned numPhysicalVecElemRegs; 12610036SAli.Saidi@ARM.com 1279469Snilay@cs.wisc.edu /** 1289469Snilay@cs.wisc.edu * Number of physical CC registers 1299469Snilay@cs.wisc.edu */ 1309578Snilay@cs.wisc.edu unsigned numPhysicalCCRegs; 1319469Snilay@cs.wisc.edu 1329469Snilay@cs.wisc.edu /** Total number of physical registers. */ 1339469Snilay@cs.wisc.edu unsigned totalNumRegs; 1349469Snilay@cs.wisc.edu 13510036SAli.Saidi@ARM.com /** Mode in which vector registers are addressed. */ 13610036SAli.Saidi@ARM.com VecMode vecMode; 1379469Snilay@cs.wisc.edu 1389864Snilay@cs.wisc.edu public: 13910036SAli.Saidi@ARM.com /** 14010036SAli.Saidi@ARM.com * Constructs a physical register file with the specified amount of 1419864Snilay@cs.wisc.edu * integer and floating point registers. 1429469Snilay@cs.wisc.edu */ 14310036SAli.Saidi@ARM.com PhysRegFile(unsigned _numPhysicalIntRegs, 1449469Snilay@cs.wisc.edu unsigned _numPhysicalFloatRegs, 1459469Snilay@cs.wisc.edu unsigned _numPhysicalVecRegs, 1469469Snilay@cs.wisc.edu unsigned _numPhysicalCCRegs, 1479864Snilay@cs.wisc.edu VecMode vmode 1489864Snilay@cs.wisc.edu ); 1499864Snilay@cs.wisc.edu 15010036SAli.Saidi@ARM.com /** 1519864Snilay@cs.wisc.edu * Destructor to free resources 1529864Snilay@cs.wisc.edu */ 1539469Snilay@cs.wisc.edu ~PhysRegFile() {} 1546928SN/A 1556928SN/A /** Initialize the free list */ 1566928SN/A void initFreeList(UnifiedFreeList *freeList); 1579864Snilay@cs.wisc.edu 15810036SAli.Saidi@ARM.com /** @return the number of integer physical registers. */ 1599469Snilay@cs.wisc.edu unsigned numIntPhysRegs() const { return numPhysicalIntRegs; } 1606928SN/A 16110036SAli.Saidi@ARM.com /** @return the number of floating-point physical registers. */ 1629469Snilay@cs.wisc.edu unsigned numFloatPhysRegs() const { return numPhysicalFloatRegs; } 1636928SN/A /** @return the number of vector physical registers. */ 1649605Snilay@cs.wisc.edu unsigned numVecPhysRegs() const { return numPhysicalVecRegs; } 1656928SN/A 1668721SN/A /** @return the number of vector physical registers. */ 1679864Snilay@cs.wisc.edu unsigned numVecElemPhysRegs() const { return numPhysicalVecElemRegs; } 1686928SN/A 1696928SN/A /** @return the number of condition-code physical registers. */ 1709469Snilay@cs.wisc.edu unsigned numCCPhysRegs() const { return numPhysicalCCRegs; } 1716928SN/A 17210036SAli.Saidi@ARM.com /** @return the total number of physical registers. */ 1737935SN/A unsigned totalNumPhysRegs() const { return totalNumRegs; } 1749348SAli.Saidi@ARM.com 1759864Snilay@cs.wisc.edu /** Gets a misc register PhysRegIdPtr. */ 1767935SN/A PhysRegIdPtr getMiscRegId(RegIndex reg_idx) { 1776928SN/A return &miscRegIds[reg_idx]; 1786928SN/A } 1799469Snilay@cs.wisc.edu 1806928SN/A /** Reads an integer register. */ 1816928SN/A uint64_t readIntReg(PhysRegIdPtr phys_reg) const 1826928SN/A { 1836928SN/A assert(phys_reg->isIntPhysReg()); 1846928SN/A 1856928SN/A DPRINTF(IEW, "RegFile: Access to int register %i, has data " 1869864Snilay@cs.wisc.edu "%#x\n", phys_reg->index(), intRegFile[phys_reg->index()]); 1876928SN/A return intRegFile[phys_reg->index()]; 1886928SN/A } 18910036SAli.Saidi@ARM.com 1906928SN/A /** Reads a floating point register (double precision). */ 1916928SN/A FloatReg readFloatReg(PhysRegIdPtr phys_reg) const 1926928SN/A { 1936928SN/A assert(phys_reg->isFloatPhysReg()); 1946928SN/A 1956928SN/A DPRINTF(IEW, "RegFile: Access to float register %i, has " 1966928SN/A "data %#x\n", phys_reg->index(), 1976928SN/A floatRegFile[phys_reg->index()].q); 1989207Snilay@cs.wisc.edu 1996928SN/A return floatRegFile[phys_reg->index()].d; 2006928SN/A } 2016928SN/A 2029469Snilay@cs.wisc.edu FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg) const 2037935SN/A { 2048721SN/A assert(phys_reg->isFloatPhysReg()); 2057935SN/A 2069469Snilay@cs.wisc.edu FloatRegBits floatRegBits = floatRegFile[phys_reg->index()].q; 2077935SN/A 2089864Snilay@cs.wisc.edu DPRINTF(IEW, "RegFile: Access to float register %i as int, " 20910036SAli.Saidi@ARM.com "has data %#x\n", phys_reg->index(), 21010036SAli.Saidi@ARM.com (uint64_t)floatRegBits); 2117935SN/A 2127935SN/A return floatRegBits; 2139605Snilay@cs.wisc.edu } 2147935SN/A 2158721SN/A /** Reads a vector register. */ 2168835SAli.Saidi@ARM.com const VecRegContainer& readVecReg(PhysRegIdPtr phys_reg) const 2179469Snilay@cs.wisc.edu { 2189864Snilay@cs.wisc.edu assert(phys_reg->isVectorPhysReg()); 2197935SN/A 2207935SN/A DPRINTF(IEW, "RegFile: Access to vector register %i, has " 2219469Snilay@cs.wisc.edu "data %s\n", int(phys_reg->index()), 2228721SN/A vectorRegFile[phys_reg->index()].as<VecElem>().print()); 2238721SN/A 2249113SBrad.Beckmann@amd.com return vectorRegFile[phys_reg->index()]; 2259113SBrad.Beckmann@amd.com } 22610036SAli.Saidi@ARM.com 2278721SN/A /** Reads a vector register for modification. */ 2288721SN/A VecRegContainer& getWritableVecReg(PhysRegIdPtr phys_reg) 2298721SN/A { 2309113SBrad.Beckmann@amd.com /* const_cast for not duplicating code above. */ 2318721SN/A return const_cast<VecRegContainer&>(readVecReg(phys_reg)); 2328721SN/A } 2339113SBrad.Beckmann@amd.com 2349113SBrad.Beckmann@amd.com /** Reads a vector register lane. */ 2358721SN/A template <typename VecElem, int LaneIdx> 2369469Snilay@cs.wisc.edu VecLaneT<VecElem, true> 2378721SN/A readVecLane(PhysRegIdPtr phys_reg) const 2389578Snilay@cs.wisc.edu { 2399864Snilay@cs.wisc.edu return readVecReg(phys_reg).laneView<VecElem, LaneIdx>(); 2409469Snilay@cs.wisc.edu } 2418721SN/A 24210036SAli.Saidi@ARM.com /** Reads a vector register lane. */ 2439469Snilay@cs.wisc.edu template <typename VecElem> 2448721SN/A VecLaneT<VecElem, true> 2458721SN/A readVecLane(PhysRegIdPtr phys_reg) const 2468983Snate@binkert.org { 2478983Snate@binkert.org return readVecReg(phys_reg).laneView<VecElem>(phys_reg->elemIndex()); 2488983Snate@binkert.org } 2498721SN/A 2508721SN/A /** Get a vector register lane for modification. */ 2518721SN/A template <typename LD> 2528983Snate@binkert.org void 2538721SN/A setVecLane(PhysRegIdPtr phys_reg, const LD& val) 2549864Snilay@cs.wisc.edu { 2559864Snilay@cs.wisc.edu assert(phys_reg->isVectorPhysReg()); 2569864Snilay@cs.wisc.edu 2579864Snilay@cs.wisc.edu DPRINTF(IEW, "RegFile: Setting vector register %i[%d] to %lx\n", 25810036SAli.Saidi@ARM.com int(phys_reg->index()), phys_reg->elemIndex(), val); 2599864Snilay@cs.wisc.edu 2607935SN/A vectorRegFile[phys_reg->index()].laneView<typename LD::UnderlyingType>( 2617935SN/A phys_reg->elemIndex()) = val; 2629864Snilay@cs.wisc.edu } 2637935SN/A 2647935SN/A /** Reads a vector element. */ 2659864Snilay@cs.wisc.edu const VecElem& readVecElem(PhysRegIdPtr phys_reg) const 2667935SN/A { 2678721SN/A assert(phys_reg->isVectorPhysElem()); 26810036SAli.Saidi@ARM.com auto ret = vectorRegFile[phys_reg->index()].as<VecElem>(); 2699605Snilay@cs.wisc.edu const VecElem& val = ret[phys_reg->elemIndex()]; 2709605Snilay@cs.wisc.edu DPRINTF(IEW, "RegFile: Access to element %d of vector register %i," 2717935SN/A " has data %#x\n", phys_reg->elemIndex(), 2729864Snilay@cs.wisc.edu int(phys_reg->index()), val); 2738721SN/A 2749605Snilay@cs.wisc.edu return val; 2757935SN/A } 2769605Snilay@cs.wisc.edu 2778721SN/A /** Reads a condition-code register. */ 2788721SN/A CCReg readCCReg(PhysRegIdPtr phys_reg) 27910036SAli.Saidi@ARM.com { 2809469Snilay@cs.wisc.edu assert(phys_reg->isCCPhysReg()); 2819864Snilay@cs.wisc.edu 2827935SN/A DPRINTF(IEW, "RegFile: Access to cc register %i, has " 2838721SN/A "data %#x\n", phys_reg->index(), 2847935SN/A ccRegFile[phys_reg->index()]); 2857935SN/A 2869605Snilay@cs.wisc.edu return ccRegFile[phys_reg->index()]; 2878721SN/A } 2888721SN/A 28910036SAli.Saidi@ARM.com /** Sets an integer register to the given value. */ 2909469Snilay@cs.wisc.edu void setIntReg(PhysRegIdPtr phys_reg, uint64_t val) 2919864Snilay@cs.wisc.edu { 2927935SN/A assert(phys_reg->isIntPhysReg()); 2938721SN/A 2947935SN/A DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n", 2957935SN/A phys_reg->index(), val); 2969605Snilay@cs.wisc.edu 2978721SN/A if (!phys_reg->isZeroReg()) 2988721SN/A intRegFile[phys_reg->index()] = val; 29910036SAli.Saidi@ARM.com } 3006928SN/A 3018721SN/A /** Sets a double precision floating point register to the given value. */ 3029864Snilay@cs.wisc.edu void setFloatReg(PhysRegIdPtr phys_reg, FloatReg val) 3039864Snilay@cs.wisc.edu { 3046928SN/A assert(phys_reg->isFloatPhysReg()); 3056928SN/A 3069605Snilay@cs.wisc.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 3078721SN/A phys_reg->index(), (uint64_t)val); 3088721SN/A 30910036SAli.Saidi@ARM.com if (!phys_reg->isZeroReg()) 3106928SN/A floatRegFile[phys_reg->index()].d = val; 3118721SN/A } 3129864Snilay@cs.wisc.edu 3139864Snilay@cs.wisc.edu void setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val) 3146928SN/A { 3156928SN/A assert(phys_reg->isFloatPhysReg()); 3169864Snilay@cs.wisc.edu 3179864Snilay@cs.wisc.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 3189864Snilay@cs.wisc.edu phys_reg->index(), (uint64_t)val); 31910036SAli.Saidi@ARM.com 3209864Snilay@cs.wisc.edu if (!phys_reg->isZeroReg()) 3219864Snilay@cs.wisc.edu floatRegFile[phys_reg->index()].q = val; 3229864Snilay@cs.wisc.edu } 3239864Snilay@cs.wisc.edu 3249864Snilay@cs.wisc.edu /** Sets a vector register to the given value. */ 3259864Snilay@cs.wisc.edu void setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val) 32610036SAli.Saidi@ARM.com { 3279864Snilay@cs.wisc.edu assert(phys_reg->isVectorPhysReg()); 3289864Snilay@cs.wisc.edu 3299864Snilay@cs.wisc.edu DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n", 3309864Snilay@cs.wisc.edu int(phys_reg->index()), val.print()); 3319864Snilay@cs.wisc.edu 3329864Snilay@cs.wisc.edu vectorRegFile[phys_reg->index()] = val; 33310036SAli.Saidi@ARM.com } 3349864Snilay@cs.wisc.edu 3359864Snilay@cs.wisc.edu /** Sets a vector register to the given value. */ 3369864Snilay@cs.wisc.edu void setVecElem(PhysRegIdPtr phys_reg, const VecElem val) 3378721SN/A { 3388721SN/A assert(phys_reg->isVectorPhysElem()); 3398721SN/A 3409864Snilay@cs.wisc.edu DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to" 34110036SAli.Saidi@ARM.com " %#x\n", phys_reg->elemIndex(), int(phys_reg->index()), val); 3428721SN/A 3438983Snate@binkert.org vectorRegFile[phys_reg->index()].as<VecElem>()[phys_reg->elemIndex()] = 3448983Snate@binkert.org val; 3458983Snate@binkert.org } 3468721SN/A 3478721SN/A /** Sets a condition-code register to the given value. */ 3488721SN/A void setCCReg(PhysRegIdPtr phys_reg, CCReg val) 3498983Snate@binkert.org { 3506928SN/A assert(phys_reg->isCCPhysReg()); 3519864Snilay@cs.wisc.edu 3529864Snilay@cs.wisc.edu DPRINTF(IEW, "RegFile: Setting cc register %i to %#x\n", 35310036SAli.Saidi@ARM.com phys_reg->index(), (uint64_t)val); 3549864Snilay@cs.wisc.edu 3559864Snilay@cs.wisc.edu ccRegFile[phys_reg->index()] = val; 356 } 357 358 /** Get the PhysRegIds of the elems of a vector register. 359 * Auxiliary function to transition from Full vector mode to Elem mode. 360 */ 361 IdRange getRegElemIds(PhysRegIdPtr reg); 362 363 /** 364 * Get the PhysRegIds of the elems of all vector registers. 365 * Auxiliary function to transition from Full vector mode to Elem mode 366 * and to initialise the rename map. 367 */ 368 IdRange getRegIds(RegClass cls); 369 370 /** 371 * Get the true physical register id. 372 * As many parts work with PhysRegIdPtr, we need to be able to produce 373 * the pointer out of just class and register idx. 374 */ 375 PhysRegIdPtr getTrueId(PhysRegIdPtr reg); 376}; 377 378 379#endif //__CPU_O3_REGFILE_HH__ 380