regfile.hh revision 3565
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292665Ssaidi@eecs.umich.edu * Gabe Black 301689SN/A */ 311689SN/A 322292SN/A#ifndef __CPU_O3_REGFILE_HH__ 332292SN/A#define __CPU_O3_REGFILE_HH__ 341060SN/A 352165SN/A#include "arch/isa_traits.hh" 362669Sktlim@umich.edu#include "arch/types.hh" 371681SN/A#include "base/trace.hh" 381858SN/A#include "config/full_system.hh" 391717SN/A#include "cpu/o3/comm.hh" 401060SN/A 411858SN/A#if FULL_SYSTEM 423565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 431681SN/A#endif 441063SN/A 452292SN/A#include <vector> 461060SN/A 472292SN/A/** 482292SN/A * Simple physical register file class. 492669Sktlim@umich.edu * Right now this is specific to Alpha until we decide if/how to make things 502669Sktlim@umich.edu * generic enough to support other ISAs. 512292SN/A */ 521061SN/Atemplate <class Impl> 531060SN/Aclass PhysRegFile 541060SN/A{ 552107SN/A protected: 562107SN/A typedef TheISA::IntReg IntReg; 572107SN/A typedef TheISA::FloatReg FloatReg; 582669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 592107SN/A typedef TheISA::MiscRegFile MiscRegFile; 602159SN/A typedef TheISA::MiscReg MiscReg; 612159SN/A 622669Sktlim@umich.edu typedef union { 632669Sktlim@umich.edu FloatReg d; 642669Sktlim@umich.edu FloatRegBits q; 652669Sktlim@umich.edu } PhysFloatReg; 661060SN/A 672292SN/A // Note that most of the definitions of the IntReg, FloatReg, etc. exist 682292SN/A // within the Impl/ISA class and not within this PhysRegFile class. 691060SN/A 702292SN/A // Will make these registers public for now, but they probably should 712292SN/A // be private eventually with some accessor functions. 721060SN/A public: 732733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 741060SN/A 752292SN/A /** 762292SN/A * Constructs a physical register file with the specified amount of 772292SN/A * integer and floating point registers. 782292SN/A */ 791060SN/A PhysRegFile(unsigned _numPhysicalIntRegs, 801060SN/A unsigned _numPhysicalFloatRegs); 811060SN/A 821060SN/A //Everything below should be pretty well identical to the normal 831060SN/A //register file that exists within AlphaISA class. 841060SN/A //The duplication is unfortunate but it's better than having 851060SN/A //different ways to access certain registers. 861060SN/A 872292SN/A /** Reads an integer register. */ 881060SN/A uint64_t readIntReg(PhysRegIndex reg_idx) 891060SN/A { 901061SN/A assert(reg_idx < numPhysicalIntRegs); 911061SN/A 921060SN/A DPRINTF(IEW, "RegFile: Access to int register %i, has data " 932690Sktlim@umich.edu "%#x\n", int(reg_idx), intRegFile[reg_idx]); 941060SN/A return intRegFile[reg_idx]; 951060SN/A } 961060SN/A 972455SN/A FloatReg readFloatReg(PhysRegIndex reg_idx, int width) 981060SN/A { 991060SN/A // Remove the base Float reg dependency. 1001060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1011060SN/A 1021062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1031061SN/A 1042669Sktlim@umich.edu FloatReg floatReg = floatRegFile[reg_idx].d; 1051060SN/A 1062455SN/A DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has " 1072690Sktlim@umich.edu "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q); 1082455SN/A 1092455SN/A return floatReg; 1101060SN/A } 1111060SN/A 1122292SN/A /** Reads a floating point register (double precision). */ 1132455SN/A FloatReg readFloatReg(PhysRegIndex reg_idx) 1141060SN/A { 1151060SN/A // Remove the base Float reg dependency. 1161060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1171060SN/A 1181062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1191061SN/A 1202669Sktlim@umich.edu FloatReg floatReg = floatRegFile[reg_idx].d; 1211060SN/A 1222455SN/A DPRINTF(IEW, "RegFile: Access to float register %i, has " 1232690Sktlim@umich.edu "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q); 1242455SN/A 1252455SN/A return floatReg; 1261060SN/A } 1271060SN/A 1282292SN/A /** Reads a floating point register as an integer. */ 1292455SN/A FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width) 1301060SN/A { 1311060SN/A // Remove the base Float reg dependency. 1321060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1331060SN/A 1341062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1351061SN/A 1362669Sktlim@umich.edu FloatRegBits floatRegBits = floatRegFile[reg_idx].q; 1371060SN/A 1382690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Access to float register %i as int, " 1392690Sktlim@umich.edu "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits); 1402455SN/A 1412455SN/A return floatRegBits; 1422455SN/A } 1432455SN/A 1442455SN/A FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) 1452455SN/A { 1462455SN/A // Remove the base Float reg dependency. 1472455SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1482455SN/A 1492455SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1502455SN/A 1512669Sktlim@umich.edu FloatRegBits floatRegBits = floatRegFile[reg_idx].q; 1522455SN/A 1532455SN/A DPRINTF(IEW, "RegFile: Access to float register %i as int, " 1542690Sktlim@umich.edu "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits); 1552455SN/A 1562455SN/A return floatRegBits; 1571060SN/A } 1581060SN/A 1592292SN/A /** Sets an integer register to the given value. */ 1601060SN/A void setIntReg(PhysRegIndex reg_idx, uint64_t val) 1611060SN/A { 1621061SN/A assert(reg_idx < numPhysicalIntRegs); 1631061SN/A 1642690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n", 1651060SN/A int(reg_idx), val); 1661060SN/A 1672292SN/A if (reg_idx != TheISA::ZeroReg) 1682292SN/A intRegFile[reg_idx] = val; 1691060SN/A } 1701060SN/A 1712292SN/A /** Sets a single precision floating point register to the given value. */ 1722455SN/A void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width) 1731060SN/A { 1741060SN/A // Remove the base Float reg dependency. 1751060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1761060SN/A 1771062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1781061SN/A 1792690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 1802690Sktlim@umich.edu int(reg_idx), (uint64_t)val); 1811060SN/A 1822292SN/A if (reg_idx != TheISA::ZeroReg) 1832690Sktlim@umich.edu floatRegFile[reg_idx].d = val; 1841060SN/A } 1851060SN/A 1862292SN/A /** Sets a double precision floating point register to the given value. */ 1872455SN/A void setFloatReg(PhysRegIndex reg_idx, FloatReg val) 1881060SN/A { 1891060SN/A // Remove the base Float reg dependency. 1901060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1911060SN/A 1921062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1931061SN/A 1942690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 1952690Sktlim@umich.edu int(reg_idx), (uint64_t)val); 1961060SN/A 1972292SN/A if (reg_idx != TheISA::ZeroReg) 1982669Sktlim@umich.edu floatRegFile[reg_idx].d = val; 1991060SN/A } 2001060SN/A 2012292SN/A /** Sets a floating point register to the given integer value. */ 2022455SN/A void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width) 2031060SN/A { 2041060SN/A // Remove the base Float reg dependency. 2051060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 2061060SN/A 2071062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 2081061SN/A 2092690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 2102455SN/A int(reg_idx), (uint64_t)val); 2111060SN/A 2122669Sktlim@umich.edu floatRegFile[reg_idx].q = val; 2132455SN/A } 2142455SN/A 2152455SN/A void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) 2162455SN/A { 2172455SN/A // Remove the base Float reg dependency. 2182455SN/A reg_idx = reg_idx - numPhysicalIntRegs; 2192455SN/A 2202455SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 2212455SN/A 2222690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 2232455SN/A int(reg_idx), (uint64_t)val); 2242455SN/A 2252669Sktlim@umich.edu floatRegFile[reg_idx].q = val; 2261060SN/A } 2271060SN/A 2282669Sktlim@umich.edu MiscReg readMiscReg(int misc_reg, unsigned thread_id) 2291060SN/A { 2302669Sktlim@umich.edu return miscRegs[thread_id].readReg(misc_reg); 2311060SN/A } 2321060SN/A 2333468Sgblack@eecs.umich.edu MiscReg readMiscRegWithEffect(int misc_reg, unsigned thread_id) 2341060SN/A { 2353468Sgblack@eecs.umich.edu return miscRegs[thread_id].readRegWithEffect(misc_reg, 2362680Sktlim@umich.edu cpu->tcBase(thread_id)); 2371060SN/A } 2381060SN/A 2393468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id) 2401060SN/A { 2413468Sgblack@eecs.umich.edu miscRegs[thread_id].setReg(misc_reg, val); 2421060SN/A } 2431060SN/A 2443468Sgblack@eecs.umich.edu void setMiscRegWithEffect(int misc_reg, const MiscReg &val, 2452292SN/A unsigned thread_id) 2461060SN/A { 2473468Sgblack@eecs.umich.edu miscRegs[thread_id].setRegWithEffect(misc_reg, val, 2482680Sktlim@umich.edu cpu->tcBase(thread_id)); 2491060SN/A } 2501060SN/A 2511060SN/A public: 2521060SN/A /** (signed) integer register file. */ 2532690Sktlim@umich.edu IntReg *intRegFile; 2541060SN/A 2551060SN/A /** Floating point register file. */ 2562690Sktlim@umich.edu PhysFloatReg *floatRegFile; 2571060SN/A 2581060SN/A /** Miscellaneous register file. */ 2592292SN/A MiscRegFile miscRegs[Impl::MaxThreads]; 2601060SN/A 2611858SN/A#if FULL_SYSTEM 2621060SN/A private: 2631681SN/A int intrflag; // interrupt flag 2641681SN/A#endif 2651681SN/A 2661681SN/A private: 2672292SN/A /** CPU pointer. */ 2682733Sktlim@umich.edu O3CPU *cpu; 2691681SN/A 2701681SN/A public: 2712292SN/A /** Sets the CPU pointer. */ 2722733Sktlim@umich.edu void setCPU(O3CPU *cpu_ptr) { cpu = cpu_ptr; } 2731681SN/A 2742292SN/A /** Number of physical integer registers. */ 2751060SN/A unsigned numPhysicalIntRegs; 2762292SN/A /** Number of physical floating point registers. */ 2771060SN/A unsigned numPhysicalFloatRegs; 2781060SN/A}; 2791060SN/A 2801061SN/Atemplate <class Impl> 2811060SN/APhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs, 2821060SN/A unsigned _numPhysicalFloatRegs) 2831060SN/A : numPhysicalIntRegs(_numPhysicalIntRegs), 2841060SN/A numPhysicalFloatRegs(_numPhysicalFloatRegs) 2851060SN/A{ 2862690Sktlim@umich.edu intRegFile = new IntReg[numPhysicalIntRegs]; 2872690Sktlim@umich.edu floatRegFile = new PhysFloatReg[numPhysicalFloatRegs]; 2881060SN/A 2892681Sktlim@umich.edu for (int i = 0; i < Impl::MaxThreads; ++i) { 2902681Sktlim@umich.edu miscRegs[i].clear(); 2912681Sktlim@umich.edu } 2922681Sktlim@umich.edu 2932690Sktlim@umich.edu memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs); 2942690Sktlim@umich.edu memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs); 2951060SN/A} 2961060SN/A 2972292SN/A#endif 298