regfile.hh revision 3468
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292665Ssaidi@eecs.umich.edu * Gabe Black 301689SN/A */ 311689SN/A 322292SN/A#ifndef __CPU_O3_REGFILE_HH__ 332292SN/A#define __CPU_O3_REGFILE_HH__ 341060SN/A 352165SN/A#include "arch/isa_traits.hh" 362669Sktlim@umich.edu#include "arch/types.hh" 371681SN/A#include "base/trace.hh" 381858SN/A#include "config/full_system.hh" 391717SN/A#include "cpu/o3/comm.hh" 401060SN/A 411858SN/A#if FULL_SYSTEM 421681SN/A#include "kern/kernel_stats.hh" 431681SN/A 441681SN/A#endif 451063SN/A 462292SN/A#include <vector> 471060SN/A 482292SN/A/** 492292SN/A * Simple physical register file class. 502669Sktlim@umich.edu * Right now this is specific to Alpha until we decide if/how to make things 512669Sktlim@umich.edu * generic enough to support other ISAs. 522292SN/A */ 531061SN/Atemplate <class Impl> 541060SN/Aclass PhysRegFile 551060SN/A{ 562107SN/A protected: 572107SN/A typedef TheISA::IntReg IntReg; 582107SN/A typedef TheISA::FloatReg FloatReg; 592669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 602107SN/A typedef TheISA::MiscRegFile MiscRegFile; 612159SN/A typedef TheISA::MiscReg MiscReg; 622159SN/A 632669Sktlim@umich.edu typedef union { 642669Sktlim@umich.edu FloatReg d; 652669Sktlim@umich.edu FloatRegBits q; 662669Sktlim@umich.edu } PhysFloatReg; 671060SN/A 682292SN/A // Note that most of the definitions of the IntReg, FloatReg, etc. exist 692292SN/A // within the Impl/ISA class and not within this PhysRegFile class. 701060SN/A 712292SN/A // Will make these registers public for now, but they probably should 722292SN/A // be private eventually with some accessor functions. 731060SN/A public: 742733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 751060SN/A 762292SN/A /** 772292SN/A * Constructs a physical register file with the specified amount of 782292SN/A * integer and floating point registers. 792292SN/A */ 801060SN/A PhysRegFile(unsigned _numPhysicalIntRegs, 811060SN/A unsigned _numPhysicalFloatRegs); 821060SN/A 831060SN/A //Everything below should be pretty well identical to the normal 841060SN/A //register file that exists within AlphaISA class. 851060SN/A //The duplication is unfortunate but it's better than having 861060SN/A //different ways to access certain registers. 871060SN/A 882292SN/A /** Reads an integer register. */ 891060SN/A uint64_t readIntReg(PhysRegIndex reg_idx) 901060SN/A { 911061SN/A assert(reg_idx < numPhysicalIntRegs); 921061SN/A 931060SN/A DPRINTF(IEW, "RegFile: Access to int register %i, has data " 942690Sktlim@umich.edu "%#x\n", int(reg_idx), intRegFile[reg_idx]); 951060SN/A return intRegFile[reg_idx]; 961060SN/A } 971060SN/A 982455SN/A FloatReg readFloatReg(PhysRegIndex reg_idx, int width) 991060SN/A { 1001060SN/A // Remove the base Float reg dependency. 1011060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1021060SN/A 1031062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1041061SN/A 1052669Sktlim@umich.edu FloatReg floatReg = floatRegFile[reg_idx].d; 1061060SN/A 1072455SN/A DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has " 1082690Sktlim@umich.edu "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q); 1092455SN/A 1102455SN/A return floatReg; 1111060SN/A } 1121060SN/A 1132292SN/A /** Reads a floating point register (double precision). */ 1142455SN/A FloatReg readFloatReg(PhysRegIndex reg_idx) 1151060SN/A { 1161060SN/A // Remove the base Float reg dependency. 1171060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1181060SN/A 1191062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1201061SN/A 1212669Sktlim@umich.edu FloatReg floatReg = floatRegFile[reg_idx].d; 1221060SN/A 1232455SN/A DPRINTF(IEW, "RegFile: Access to float register %i, has " 1242690Sktlim@umich.edu "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q); 1252455SN/A 1262455SN/A return floatReg; 1271060SN/A } 1281060SN/A 1292292SN/A /** Reads a floating point register as an integer. */ 1302455SN/A FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width) 1311060SN/A { 1321060SN/A // Remove the base Float reg dependency. 1331060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1341060SN/A 1351062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1361061SN/A 1372669Sktlim@umich.edu FloatRegBits floatRegBits = floatRegFile[reg_idx].q; 1381060SN/A 1392690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Access to float register %i as int, " 1402690Sktlim@umich.edu "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits); 1412455SN/A 1422455SN/A return floatRegBits; 1432455SN/A } 1442455SN/A 1452455SN/A FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) 1462455SN/A { 1472455SN/A // Remove the base Float reg dependency. 1482455SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1492455SN/A 1502455SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1512455SN/A 1522669Sktlim@umich.edu FloatRegBits floatRegBits = floatRegFile[reg_idx].q; 1532455SN/A 1542455SN/A DPRINTF(IEW, "RegFile: Access to float register %i as int, " 1552690Sktlim@umich.edu "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits); 1562455SN/A 1572455SN/A return floatRegBits; 1581060SN/A } 1591060SN/A 1602292SN/A /** Sets an integer register to the given value. */ 1611060SN/A void setIntReg(PhysRegIndex reg_idx, uint64_t val) 1621060SN/A { 1631061SN/A assert(reg_idx < numPhysicalIntRegs); 1641061SN/A 1652690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting int register %i to %#x\n", 1661060SN/A int(reg_idx), val); 1671060SN/A 1682292SN/A if (reg_idx != TheISA::ZeroReg) 1692292SN/A intRegFile[reg_idx] = val; 1701060SN/A } 1711060SN/A 1722292SN/A /** Sets a single precision floating point register to the given value. */ 1732455SN/A void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width) 1741060SN/A { 1751060SN/A // Remove the base Float reg dependency. 1761060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1771060SN/A 1781062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1791061SN/A 1802690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 1812690Sktlim@umich.edu int(reg_idx), (uint64_t)val); 1821060SN/A 1832292SN/A if (reg_idx != TheISA::ZeroReg) 1842690Sktlim@umich.edu floatRegFile[reg_idx].d = val; 1851060SN/A } 1861060SN/A 1872292SN/A /** Sets a double precision floating point register to the given value. */ 1882455SN/A void setFloatReg(PhysRegIndex reg_idx, FloatReg val) 1891060SN/A { 1901060SN/A // Remove the base Float reg dependency. 1911060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 1921060SN/A 1931062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 1941061SN/A 1952690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 1962690Sktlim@umich.edu int(reg_idx), (uint64_t)val); 1971060SN/A 1982292SN/A if (reg_idx != TheISA::ZeroReg) 1992669Sktlim@umich.edu floatRegFile[reg_idx].d = val; 2001060SN/A } 2011060SN/A 2022292SN/A /** Sets a floating point register to the given integer value. */ 2032455SN/A void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width) 2041060SN/A { 2051060SN/A // Remove the base Float reg dependency. 2061060SN/A reg_idx = reg_idx - numPhysicalIntRegs; 2071060SN/A 2081062SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 2091061SN/A 2102690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 2112455SN/A int(reg_idx), (uint64_t)val); 2121060SN/A 2132669Sktlim@umich.edu floatRegFile[reg_idx].q = val; 2142455SN/A } 2152455SN/A 2162455SN/A void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) 2172455SN/A { 2182455SN/A // Remove the base Float reg dependency. 2192455SN/A reg_idx = reg_idx - numPhysicalIntRegs; 2202455SN/A 2212455SN/A assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); 2222455SN/A 2232690Sktlim@umich.edu DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", 2242455SN/A int(reg_idx), (uint64_t)val); 2252455SN/A 2262669Sktlim@umich.edu floatRegFile[reg_idx].q = val; 2271060SN/A } 2281060SN/A 2292669Sktlim@umich.edu MiscReg readMiscReg(int misc_reg, unsigned thread_id) 2301060SN/A { 2312669Sktlim@umich.edu return miscRegs[thread_id].readReg(misc_reg); 2321060SN/A } 2331060SN/A 2343468Sgblack@eecs.umich.edu MiscReg readMiscRegWithEffect(int misc_reg, unsigned thread_id) 2351060SN/A { 2363468Sgblack@eecs.umich.edu return miscRegs[thread_id].readRegWithEffect(misc_reg, 2372680Sktlim@umich.edu cpu->tcBase(thread_id)); 2381060SN/A } 2391060SN/A 2403468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id) 2411060SN/A { 2423468Sgblack@eecs.umich.edu miscRegs[thread_id].setReg(misc_reg, val); 2431060SN/A } 2441060SN/A 2453468Sgblack@eecs.umich.edu void setMiscRegWithEffect(int misc_reg, const MiscReg &val, 2462292SN/A unsigned thread_id) 2471060SN/A { 2483468Sgblack@eecs.umich.edu miscRegs[thread_id].setRegWithEffect(misc_reg, val, 2492680Sktlim@umich.edu cpu->tcBase(thread_id)); 2501060SN/A } 2511060SN/A 2521060SN/A public: 2531060SN/A /** (signed) integer register file. */ 2542690Sktlim@umich.edu IntReg *intRegFile; 2551060SN/A 2561060SN/A /** Floating point register file. */ 2572690Sktlim@umich.edu PhysFloatReg *floatRegFile; 2581060SN/A 2591060SN/A /** Miscellaneous register file. */ 2602292SN/A MiscRegFile miscRegs[Impl::MaxThreads]; 2611060SN/A 2621858SN/A#if FULL_SYSTEM 2631060SN/A private: 2641681SN/A int intrflag; // interrupt flag 2651681SN/A#endif 2661681SN/A 2671681SN/A private: 2682292SN/A /** CPU pointer. */ 2692733Sktlim@umich.edu O3CPU *cpu; 2701681SN/A 2711681SN/A public: 2722292SN/A /** Sets the CPU pointer. */ 2732733Sktlim@umich.edu void setCPU(O3CPU *cpu_ptr) { cpu = cpu_ptr; } 2741681SN/A 2752292SN/A /** Number of physical integer registers. */ 2761060SN/A unsigned numPhysicalIntRegs; 2772292SN/A /** Number of physical floating point registers. */ 2781060SN/A unsigned numPhysicalFloatRegs; 2791060SN/A}; 2801060SN/A 2811061SN/Atemplate <class Impl> 2821060SN/APhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs, 2831060SN/A unsigned _numPhysicalFloatRegs) 2841060SN/A : numPhysicalIntRegs(_numPhysicalIntRegs), 2851060SN/A numPhysicalFloatRegs(_numPhysicalFloatRegs) 2861060SN/A{ 2872690Sktlim@umich.edu intRegFile = new IntReg[numPhysicalIntRegs]; 2882690Sktlim@umich.edu floatRegFile = new PhysFloatReg[numPhysicalFloatRegs]; 2891060SN/A 2902681Sktlim@umich.edu for (int i = 0; i < Impl::MaxThreads; ++i) { 2912681Sktlim@umich.edu miscRegs[i].clear(); 2922681Sktlim@umich.edu } 2932681Sktlim@umich.edu 2942690Sktlim@umich.edu memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs); 2952690Sktlim@umich.edu memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs); 2961060SN/A} 2971060SN/A 2982292SN/A#endif 299