regfile.cc revision 9920
19919Ssteve.reinhardt@amd.com/*
29919Ssteve.reinhardt@amd.com * Copyright (c) 2004-2005 The Regents of The University of Michigan
39919Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc.
49919Ssteve.reinhardt@amd.com * All rights reserved.
59919Ssteve.reinhardt@amd.com *
69919Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without
79919Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are
89919Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright
99919Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer;
109919Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright
119919Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the
129919Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution;
139919Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its
149919Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from
159919Ssteve.reinhardt@amd.com * this software without specific prior written permission.
169919Ssteve.reinhardt@amd.com *
179919Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
189919Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
199919Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
209919Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
219919Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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279919Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
289919Ssteve.reinhardt@amd.com *
299919Ssteve.reinhardt@amd.com * Authors: Kevin Lim
309919Ssteve.reinhardt@amd.com *          Gabe Black
319919Ssteve.reinhardt@amd.com *          Steve Reinhardt
329919Ssteve.reinhardt@amd.com */
339919Ssteve.reinhardt@amd.com
349919Ssteve.reinhardt@amd.com#include "cpu/o3/free_list.hh"
359919Ssteve.reinhardt@amd.com#include "cpu/o3/regfile.hh"
369919Ssteve.reinhardt@amd.com
379919Ssteve.reinhardt@amd.com
389919Ssteve.reinhardt@amd.comPhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs,
399920Syasuko.eckert@amd.com                         unsigned _numPhysicalFloatRegs,
409920Syasuko.eckert@amd.com                         unsigned _numPhysicalCCRegs)
419919Ssteve.reinhardt@amd.com    : intRegFile(_numPhysicalIntRegs),
429919Ssteve.reinhardt@amd.com      floatRegFile(_numPhysicalFloatRegs),
439920Syasuko.eckert@amd.com      ccRegFile(_numPhysicalCCRegs),
449919Ssteve.reinhardt@amd.com      baseFloatRegIndex(_numPhysicalIntRegs),
459920Syasuko.eckert@amd.com      baseCCRegIndex(_numPhysicalIntRegs + _numPhysicalFloatRegs),
469920Syasuko.eckert@amd.com      totalNumRegs(_numPhysicalIntRegs
479920Syasuko.eckert@amd.com                   + _numPhysicalFloatRegs
489920Syasuko.eckert@amd.com                   + _numPhysicalCCRegs)
499919Ssteve.reinhardt@amd.com{
509920Syasuko.eckert@amd.com    if (TheISA::NumCCRegs == 0 && _numPhysicalCCRegs != 0) {
519920Syasuko.eckert@amd.com        // Just make this a warning and go ahead and allocate them
529920Syasuko.eckert@amd.com        // anyway, to keep from having to add checks everywhere
539920Syasuko.eckert@amd.com        warn("Non-zero number of physical CC regs specified, even though\n"
549920Syasuko.eckert@amd.com             "    ISA does not use them.\n");
559920Syasuko.eckert@amd.com    }
569919Ssteve.reinhardt@amd.com}
579919Ssteve.reinhardt@amd.com
589919Ssteve.reinhardt@amd.com
599919Ssteve.reinhardt@amd.comvoid
609919Ssteve.reinhardt@amd.comPhysRegFile::initFreeList(UnifiedFreeList *freeList)
619919Ssteve.reinhardt@amd.com{
629919Ssteve.reinhardt@amd.com    // Initialize the free lists.
639919Ssteve.reinhardt@amd.com    PhysRegIndex reg_idx = 0;
649919Ssteve.reinhardt@amd.com
659919Ssteve.reinhardt@amd.com    // The initial batch of registers are the integer ones
669919Ssteve.reinhardt@amd.com    while (reg_idx < baseFloatRegIndex) {
679919Ssteve.reinhardt@amd.com        freeList->addIntReg(reg_idx++);
689919Ssteve.reinhardt@amd.com    }
699919Ssteve.reinhardt@amd.com
709920Syasuko.eckert@amd.com    // The next batch of the registers are the floating-point physical
719919Ssteve.reinhardt@amd.com    // registers; put them onto the floating-point free list.
729920Syasuko.eckert@amd.com    while (reg_idx < baseCCRegIndex) {
739919Ssteve.reinhardt@amd.com        freeList->addFloatReg(reg_idx++);
749919Ssteve.reinhardt@amd.com    }
759920Syasuko.eckert@amd.com
769920Syasuko.eckert@amd.com    // The rest of the registers are the condition-code physical
779920Syasuko.eckert@amd.com    // registers; put them onto the condition-code free list.
789920Syasuko.eckert@amd.com    while (reg_idx < totalNumRegs) {
799920Syasuko.eckert@amd.com        freeList->addCCReg(reg_idx++);
809920Syasuko.eckert@amd.com    }
819919Ssteve.reinhardt@amd.com}
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