regfile.cc revision 12105
19919Ssteve.reinhardt@amd.com/*
29919Ssteve.reinhardt@amd.com * Copyright (c) 2004-2005 The Regents of The University of Michigan
39919Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc.
49919Ssteve.reinhardt@amd.com * All rights reserved.
59919Ssteve.reinhardt@amd.com *
69919Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without
79919Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are
89919Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright
99919Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer;
109919Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright
119919Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the
129919Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution;
139919Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its
149919Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from
159919Ssteve.reinhardt@amd.com * this software without specific prior written permission.
169919Ssteve.reinhardt@amd.com *
179919Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
189919Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
199919Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
209919Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
219919Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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269919Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
279919Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
289919Ssteve.reinhardt@amd.com *
299919Ssteve.reinhardt@amd.com * Authors: Kevin Lim
309919Ssteve.reinhardt@amd.com *          Gabe Black
319919Ssteve.reinhardt@amd.com *          Steve Reinhardt
329919Ssteve.reinhardt@amd.com */
339919Ssteve.reinhardt@amd.com
349919Ssteve.reinhardt@amd.com#include "cpu/o3/regfile.hh"
359919Ssteve.reinhardt@amd.com
3611793Sbrandon.potter@amd.com#include "cpu/o3/free_list.hh"
379919Ssteve.reinhardt@amd.com
389919Ssteve.reinhardt@amd.comPhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs,
399920Syasuko.eckert@amd.com                         unsigned _numPhysicalFloatRegs,
4010935Snilay@cs.wisc.edu                         unsigned _numPhysicalCCRegs)
419919Ssteve.reinhardt@amd.com    : intRegFile(_numPhysicalIntRegs),
429919Ssteve.reinhardt@amd.com      floatRegFile(_numPhysicalFloatRegs),
439920Syasuko.eckert@amd.com      ccRegFile(_numPhysicalCCRegs),
4412105Snathanael.premillieu@arm.com      numPhysicalIntRegs(_numPhysicalIntRegs),
4512105Snathanael.premillieu@arm.com      numPhysicalFloatRegs(_numPhysicalFloatRegs),
4612105Snathanael.premillieu@arm.com      numPhysicalCCRegs(_numPhysicalCCRegs),
479920Syasuko.eckert@amd.com      totalNumRegs(_numPhysicalIntRegs
489920Syasuko.eckert@amd.com                   + _numPhysicalFloatRegs
4910935Snilay@cs.wisc.edu                   + _numPhysicalCCRegs)
509919Ssteve.reinhardt@amd.com{
5112105Snathanael.premillieu@arm.com    PhysRegIndex phys_reg;
5212105Snathanael.premillieu@arm.com    PhysRegIndex flat_reg_idx = 0;
5312105Snathanael.premillieu@arm.com
549920Syasuko.eckert@amd.com    if (TheISA::NumCCRegs == 0 && _numPhysicalCCRegs != 0) {
559920Syasuko.eckert@amd.com        // Just make this a warning and go ahead and allocate them
569920Syasuko.eckert@amd.com        // anyway, to keep from having to add checks everywhere
579920Syasuko.eckert@amd.com        warn("Non-zero number of physical CC regs specified, even though\n"
589920Syasuko.eckert@amd.com             "    ISA does not use them.\n");
599920Syasuko.eckert@amd.com    }
6012105Snathanael.premillieu@arm.com    // The initial batch of registers are the integer ones
6112105Snathanael.premillieu@arm.com    for (phys_reg = 0; phys_reg < numPhysicalIntRegs; phys_reg++) {
6212105Snathanael.premillieu@arm.com        intRegIds.emplace_back(IntRegClass, phys_reg, flat_reg_idx++);
6312105Snathanael.premillieu@arm.com    }
6412105Snathanael.premillieu@arm.com
6512105Snathanael.premillieu@arm.com    // The next batch of the registers are the floating-point physical
6612105Snathanael.premillieu@arm.com    // registers; put them onto the floating-point free list.
6712105Snathanael.premillieu@arm.com    for (phys_reg = 0; phys_reg < numPhysicalFloatRegs; phys_reg++) {
6812105Snathanael.premillieu@arm.com        floatRegIds.emplace_back(FloatRegClass, phys_reg, flat_reg_idx++);
6912105Snathanael.premillieu@arm.com    }
7012105Snathanael.premillieu@arm.com
7112105Snathanael.premillieu@arm.com    // The rest of the registers are the condition-code physical
7212105Snathanael.premillieu@arm.com    // registers; put them onto the condition-code free list.
7312105Snathanael.premillieu@arm.com    for (phys_reg = 0; phys_reg < numPhysicalCCRegs; phys_reg++) {
7412105Snathanael.premillieu@arm.com        ccRegIds.emplace_back(CCRegClass, phys_reg, flat_reg_idx++);
7512105Snathanael.premillieu@arm.com    }
7612105Snathanael.premillieu@arm.com
7712105Snathanael.premillieu@arm.com    // Misc regs have a fixed mapping but still need PhysRegIds.
7812105Snathanael.premillieu@arm.com    for (phys_reg = 0; phys_reg < TheISA::NumMiscRegs; phys_reg++) {
7912105Snathanael.premillieu@arm.com        miscRegIds.emplace_back(MiscRegClass, phys_reg, 0);
8012105Snathanael.premillieu@arm.com    }
819919Ssteve.reinhardt@amd.com}
829919Ssteve.reinhardt@amd.com
839919Ssteve.reinhardt@amd.com
849919Ssteve.reinhardt@amd.comvoid
859919Ssteve.reinhardt@amd.comPhysRegFile::initFreeList(UnifiedFreeList *freeList)
869919Ssteve.reinhardt@amd.com{
879919Ssteve.reinhardt@amd.com    // Initialize the free lists.
8812105Snathanael.premillieu@arm.com    int reg_idx = 0;
899919Ssteve.reinhardt@amd.com
909919Ssteve.reinhardt@amd.com    // The initial batch of registers are the integer ones
9112105Snathanael.premillieu@arm.com    for (reg_idx = 0; reg_idx < numPhysicalIntRegs; reg_idx++) {
9212105Snathanael.premillieu@arm.com        assert(intRegIds[reg_idx].regIdx == reg_idx);
9312105Snathanael.premillieu@arm.com        freeList->addIntReg(&intRegIds[reg_idx]);
949919Ssteve.reinhardt@amd.com    }
959919Ssteve.reinhardt@amd.com
969920Syasuko.eckert@amd.com    // The next batch of the registers are the floating-point physical
979919Ssteve.reinhardt@amd.com    // registers; put them onto the floating-point free list.
9812105Snathanael.premillieu@arm.com    for (reg_idx = 0; reg_idx < numPhysicalFloatRegs; reg_idx++) {
9912105Snathanael.premillieu@arm.com        assert(floatRegIds[reg_idx].regIdx == reg_idx);
10012105Snathanael.premillieu@arm.com        freeList->addFloatReg(&floatRegIds[reg_idx]);
1019919Ssteve.reinhardt@amd.com    }
1029920Syasuko.eckert@amd.com
10310935Snilay@cs.wisc.edu    // The rest of the registers are the condition-code physical
1049920Syasuko.eckert@amd.com    // registers; put them onto the condition-code free list.
10512105Snathanael.premillieu@arm.com    for (reg_idx = 0; reg_idx < numPhysicalCCRegs; reg_idx++) {
10612105Snathanael.premillieu@arm.com        assert(ccRegIds[reg_idx].regIdx == reg_idx);
10712105Snathanael.premillieu@arm.com        freeList->addCCReg(&ccRegIds[reg_idx]);
1089920Syasuko.eckert@amd.com    }
1099919Ssteve.reinhardt@amd.com}
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