mem_dep_unit_impl.hh revision 9444
1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#include <map> 44 45#include "cpu/o3/inst_queue.hh" 46#include "cpu/o3/mem_dep_unit.hh" 47#include "debug/MemDepUnit.hh" 48#include "params/DerivO3CPU.hh" 49 50template <class MemDepPred, class Impl> 51MemDepUnit<MemDepPred, Impl>::MemDepUnit() 52 : loadBarrier(false), loadBarrierSN(0), storeBarrier(false), 53 storeBarrierSN(0), iqPtr(NULL) 54{ 55} 56 57template <class MemDepPred, class Impl> 58MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params) 59 : _name(params->name + ".memdepunit"), 60 depPred(params->store_set_clear_period, params->SSITSize, 61 params->LFSTSize), 62 loadBarrier(false), loadBarrierSN(0), storeBarrier(false), 63 storeBarrierSN(0), iqPtr(NULL) 64{ 65 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n"); 66} 67 68template <class MemDepPred, class Impl> 69MemDepUnit<MemDepPred, Impl>::~MemDepUnit() 70{ 71 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 72 73 ListIt inst_list_it = instList[tid].begin(); 74 75 MemDepHashIt hash_it; 76 77 while (!instList[tid].empty()) { 78 hash_it = memDepHash.find((*inst_list_it)->seqNum); 79 80 assert(hash_it != memDepHash.end()); 81 82 memDepHash.erase(hash_it); 83 84 instList[tid].erase(inst_list_it++); 85 } 86 } 87 88#ifdef DEBUG 89 assert(MemDepEntry::memdep_count == 0); 90#endif 91} 92 93template <class MemDepPred, class Impl> 94void 95MemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, ThreadID tid) 96{ 97 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid); 98 99 _name = csprintf("%s.memDep%d", params->name, tid); 100 id = tid; 101 102 depPred.init(params->store_set_clear_period, params->SSITSize, 103 params->LFSTSize); 104} 105 106template <class MemDepPred, class Impl> 107void 108MemDepUnit<MemDepPred, Impl>::regStats() 109{ 110 insertedLoads 111 .name(name() + ".insertedLoads") 112 .desc("Number of loads inserted to the mem dependence unit."); 113 114 insertedStores 115 .name(name() + ".insertedStores") 116 .desc("Number of stores inserted to the mem dependence unit."); 117 118 conflictingLoads 119 .name(name() + ".conflictingLoads") 120 .desc("Number of conflicting loads."); 121 122 conflictingStores 123 .name(name() + ".conflictingStores") 124 .desc("Number of conflicting stores."); 125} 126 127template <class MemDepPred, class Impl> 128void 129MemDepUnit<MemDepPred, Impl>::drainSanityCheck() const 130{ 131 assert(instsToReplay.empty()); 132 assert(memDepHash.empty()); 133 for (int i = 0; i < Impl::MaxThreads; ++i) 134 assert(instList[i].empty()); 135 assert(instsToReplay.empty()); 136 assert(memDepHash.empty()); 137} 138 139template <class MemDepPred, class Impl> 140void 141MemDepUnit<MemDepPred, Impl>::takeOverFrom() 142{ 143 // Be sure to reset all state. 144 loadBarrier = storeBarrier = false; 145 loadBarrierSN = storeBarrierSN = 0; 146 depPred.clear(); 147} 148 149template <class MemDepPred, class Impl> 150void 151MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr) 152{ 153 iqPtr = iq_ptr; 154} 155 156template <class MemDepPred, class Impl> 157void 158MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst) 159{ 160 ThreadID tid = inst->threadNumber; 161 162 MemDepEntryPtr inst_entry = new MemDepEntry(inst); 163 164 // Add the MemDepEntry to the hash. 165 memDepHash.insert( 166 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 167#ifdef DEBUG 168 MemDepEntry::memdep_insert++; 169#endif 170 171 instList[tid].push_back(inst); 172 173 inst_entry->listIt = --(instList[tid].end()); 174 175 // Check any barriers and the dependence predictor for any 176 // producing memrefs/stores. 177 InstSeqNum producing_store; 178 if (inst->isLoad() && loadBarrier) { 179 DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n", 180 loadBarrierSN); 181 producing_store = loadBarrierSN; 182 } else if (inst->isStore() && storeBarrier) { 183 DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n", 184 storeBarrierSN); 185 producing_store = storeBarrierSN; 186 } else { 187 producing_store = depPred.checkInst(inst->instAddr()); 188 } 189 190 MemDepEntryPtr store_entry = NULL; 191 192 // If there is a producing store, try to find the entry. 193 if (producing_store != 0) { 194 DPRINTF(MemDepUnit, "Searching for producer\n"); 195 MemDepHashIt hash_it = memDepHash.find(producing_store); 196 197 if (hash_it != memDepHash.end()) { 198 store_entry = (*hash_it).second; 199 DPRINTF(MemDepUnit, "Proucer found\n"); 200 } 201 } 202 203 // If no store entry, then instruction can issue as soon as the registers 204 // are ready. 205 if (!store_entry) { 206 DPRINTF(MemDepUnit, "No dependency for inst PC " 207 "%s [sn:%lli].\n", inst->pcState(), inst->seqNum); 208 209 inst_entry->memDepReady = true; 210 211 if (inst->readyToIssue()) { 212 inst_entry->regsReady = true; 213 214 moveToReady(inst_entry); 215 } 216 } else { 217 // Otherwise make the instruction dependent on the store/barrier. 218 DPRINTF(MemDepUnit, "Adding to dependency list; " 219 "inst PC %s is dependent on [sn:%lli].\n", 220 inst->pcState(), producing_store); 221 222 if (inst->readyToIssue()) { 223 inst_entry->regsReady = true; 224 } 225 226 // Clear the bit saying this instruction can issue. 227 inst->clearCanIssue(); 228 229 // Add this instruction to the list of dependents. 230 store_entry->dependInsts.push_back(inst_entry); 231 232 if (inst->isLoad()) { 233 ++conflictingLoads; 234 } else { 235 ++conflictingStores; 236 } 237 } 238 239 if (inst->isStore()) { 240 DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n", 241 inst->pcState(), inst->seqNum); 242 243 depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber); 244 245 ++insertedStores; 246 } else if (inst->isLoad()) { 247 ++insertedLoads; 248 } else { 249 panic("Unknown type! (most likely a barrier)."); 250 } 251} 252 253template <class MemDepPred, class Impl> 254void 255MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst) 256{ 257 ThreadID tid = inst->threadNumber; 258 259 MemDepEntryPtr inst_entry = new MemDepEntry(inst); 260 261 // Insert the MemDepEntry into the hash. 262 memDepHash.insert( 263 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 264#ifdef DEBUG 265 MemDepEntry::memdep_insert++; 266#endif 267 268 // Add the instruction to the list. 269 instList[tid].push_back(inst); 270 271 inst_entry->listIt = --(instList[tid].end()); 272 273 // Might want to turn this part into an inline function or something. 274 // It's shared between both insert functions. 275 if (inst->isStore()) { 276 DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n", 277 inst->pcState(), inst->seqNum); 278 279 depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber); 280 281 ++insertedStores; 282 } else if (inst->isLoad()) { 283 ++insertedLoads; 284 } else { 285 panic("Unknown type! (most likely a barrier)."); 286 } 287} 288 289template <class MemDepPred, class Impl> 290void 291MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst) 292{ 293 InstSeqNum barr_sn = barr_inst->seqNum; 294 // Memory barriers block loads and stores, write barriers only stores. 295 if (barr_inst->isMemBarrier()) { 296 loadBarrier = true; 297 loadBarrierSN = barr_sn; 298 storeBarrier = true; 299 storeBarrierSN = barr_sn; 300 DPRINTF(MemDepUnit, "Inserted a memory barrier %s SN:%lli\n", 301 barr_inst->pcState(),barr_sn); 302 } else if (barr_inst->isWriteBarrier()) { 303 storeBarrier = true; 304 storeBarrierSN = barr_sn; 305 DPRINTF(MemDepUnit, "Inserted a write barrier\n"); 306 } 307 308 ThreadID tid = barr_inst->threadNumber; 309 310 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst); 311 312 // Add the MemDepEntry to the hash. 313 memDepHash.insert( 314 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry)); 315#ifdef DEBUG 316 MemDepEntry::memdep_insert++; 317#endif 318 319 // Add the instruction to the instruction list. 320 instList[tid].push_back(barr_inst); 321 322 inst_entry->listIt = --(instList[tid].end()); 323} 324 325template <class MemDepPred, class Impl> 326void 327MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst) 328{ 329 DPRINTF(MemDepUnit, "Marking registers as ready for " 330 "instruction PC %s [sn:%lli].\n", 331 inst->pcState(), inst->seqNum); 332 333 MemDepEntryPtr inst_entry = findInHash(inst); 334 335 inst_entry->regsReady = true; 336 337 if (inst_entry->memDepReady) { 338 DPRINTF(MemDepUnit, "Instruction has its memory " 339 "dependencies resolved, adding it to the ready list.\n"); 340 341 moveToReady(inst_entry); 342 } else { 343 DPRINTF(MemDepUnit, "Instruction still waiting on " 344 "memory dependency.\n"); 345 } 346} 347 348template <class MemDepPred, class Impl> 349void 350MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst) 351{ 352 DPRINTF(MemDepUnit, "Marking non speculative " 353 "instruction PC %s as ready [sn:%lli].\n", 354 inst->pcState(), inst->seqNum); 355 356 MemDepEntryPtr inst_entry = findInHash(inst); 357 358 moveToReady(inst_entry); 359} 360 361template <class MemDepPred, class Impl> 362void 363MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst) 364{ 365 instsToReplay.push_back(inst); 366} 367 368template <class MemDepPred, class Impl> 369void 370MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst) 371{ 372 DynInstPtr temp_inst; 373 374 // For now this replay function replays all waiting memory ops. 375 while (!instsToReplay.empty()) { 376 temp_inst = instsToReplay.front(); 377 378 MemDepEntryPtr inst_entry = findInHash(temp_inst); 379 380 DPRINTF(MemDepUnit, "Replaying mem instruction PC %s [sn:%lli].\n", 381 temp_inst->pcState(), temp_inst->seqNum); 382 383 moveToReady(inst_entry); 384 385 instsToReplay.pop_front(); 386 } 387} 388 389template <class MemDepPred, class Impl> 390void 391MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst) 392{ 393 DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n", 394 inst->pcState(), inst->seqNum); 395 396 ThreadID tid = inst->threadNumber; 397 398 // Remove the instruction from the hash and the list. 399 MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 400 401 assert(hash_it != memDepHash.end()); 402 403 instList[tid].erase((*hash_it).second->listIt); 404 405 (*hash_it).second = NULL; 406 407 memDepHash.erase(hash_it); 408#ifdef DEBUG 409 MemDepEntry::memdep_erase++; 410#endif 411} 412 413template <class MemDepPred, class Impl> 414void 415MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst) 416{ 417 wakeDependents(inst); 418 completed(inst); 419 420 InstSeqNum barr_sn = inst->seqNum; 421 DPRINTF(MemDepUnit, "barrier completed: %s SN:%lli\n", inst->pcState(), 422 inst->seqNum); 423 if (inst->isMemBarrier()) { 424 if (loadBarrierSN == barr_sn) 425 loadBarrier = false; 426 if (storeBarrierSN == barr_sn) 427 storeBarrier = false; 428 } else if (inst->isWriteBarrier()) { 429 if (storeBarrierSN == barr_sn) 430 storeBarrier = false; 431 } 432} 433 434template <class MemDepPred, class Impl> 435void 436MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst) 437{ 438 // Only stores and barriers have dependents. 439 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) { 440 return; 441 } 442 443 MemDepEntryPtr inst_entry = findInHash(inst); 444 445 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) { 446 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i]; 447 448 if (!woken_inst->inst) { 449 // Potentially removed mem dep entries could be on this list 450 continue; 451 } 452 453 DPRINTF(MemDepUnit, "Waking up a dependent inst, " 454 "[sn:%lli].\n", 455 woken_inst->inst->seqNum); 456 457 if (woken_inst->regsReady && !woken_inst->squashed) { 458 moveToReady(woken_inst); 459 } else { 460 woken_inst->memDepReady = true; 461 } 462 } 463 464 inst_entry->dependInsts.clear(); 465} 466 467template <class MemDepPred, class Impl> 468void 469MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num, 470 ThreadID tid) 471{ 472 if (!instsToReplay.empty()) { 473 ListIt replay_it = instsToReplay.begin(); 474 while (replay_it != instsToReplay.end()) { 475 if ((*replay_it)->threadNumber == tid && 476 (*replay_it)->seqNum > squashed_num) { 477 instsToReplay.erase(replay_it++); 478 } else { 479 ++replay_it; 480 } 481 } 482 } 483 484 ListIt squash_it = instList[tid].end(); 485 --squash_it; 486 487 MemDepHashIt hash_it; 488 489 while (!instList[tid].empty() && 490 (*squash_it)->seqNum > squashed_num) { 491 492 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n", 493 (*squash_it)->seqNum); 494 495 if ((*squash_it)->seqNum == loadBarrierSN) 496 loadBarrier = false; 497 498 if ((*squash_it)->seqNum == storeBarrierSN) 499 storeBarrier = false; 500 501 hash_it = memDepHash.find((*squash_it)->seqNum); 502 503 assert(hash_it != memDepHash.end()); 504 505 (*hash_it).second->squashed = true; 506 507 (*hash_it).second = NULL; 508 509 memDepHash.erase(hash_it); 510#ifdef DEBUG 511 MemDepEntry::memdep_erase++; 512#endif 513 514 instList[tid].erase(squash_it--); 515 } 516 517 // Tell the dependency predictor to squash as well. 518 depPred.squash(squashed_num, tid); 519} 520 521template <class MemDepPred, class Impl> 522void 523MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst, 524 DynInstPtr &violating_load) 525{ 526 DPRINTF(MemDepUnit, "Passing violating PCs to store sets," 527 " load: %#x, store: %#x\n", violating_load->instAddr(), 528 store_inst->instAddr()); 529 // Tell the memory dependence unit of the violation. 530 depPred.violation(store_inst->instAddr(), violating_load->instAddr()); 531} 532 533template <class MemDepPred, class Impl> 534void 535MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst) 536{ 537 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n", 538 inst->instAddr(), inst->seqNum); 539 540 depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore()); 541} 542 543template <class MemDepPred, class Impl> 544inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr & 545MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst) 546{ 547 MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 548 549 assert(hash_it != memDepHash.end()); 550 551 return (*hash_it).second; 552} 553 554template <class MemDepPred, class Impl> 555inline void 556MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry) 557{ 558 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] " 559 "to the ready list.\n", woken_inst_entry->inst->seqNum); 560 561 assert(!woken_inst_entry->squashed); 562 563 iqPtr->addReadyMemInst(woken_inst_entry->inst); 564} 565 566 567template <class MemDepPred, class Impl> 568void 569MemDepUnit<MemDepPred, Impl>::dumpLists() 570{ 571 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 572 cprintf("Instruction list %i size: %i\n", 573 tid, instList[tid].size()); 574 575 ListIt inst_list_it = instList[tid].begin(); 576 int num = 0; 577 578 while (inst_list_it != instList[tid].end()) { 579 cprintf("Instruction:%i\nPC: %s\n[sn:%i]\n[tid:%i]\nIssued:%i\n" 580 "Squashed:%i\n\n", 581 num, (*inst_list_it)->pcState(), 582 (*inst_list_it)->seqNum, 583 (*inst_list_it)->threadNumber, 584 (*inst_list_it)->isIssued(), 585 (*inst_list_it)->isSquashed()); 586 inst_list_it++; 587 ++num; 588 } 589 } 590 591 cprintf("Memory dependence hash size: %i\n", memDepHash.size()); 592 593#ifdef DEBUG 594 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count); 595#endif 596} 597