mem_dep_unit_impl.hh revision 8516:a9c0d2ab490a 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <map>
32
33#include "cpu/o3/inst_queue.hh"
34#include "cpu/o3/mem_dep_unit.hh"
35#include "debug/MemDepUnit.hh"
36#include "params/DerivO3CPU.hh"
37
38template <class MemDepPred, class Impl>
39MemDepUnit<MemDepPred, Impl>::MemDepUnit()
40    : loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
41      storeBarrierSN(0), iqPtr(NULL)
42{
43}
44
45template <class MemDepPred, class Impl>
46MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params)
47    : _name(params->name + ".memdepunit"),
48      depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
49      loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
50{
51    DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
52}
53
54template <class MemDepPred, class Impl>
55MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
56{
57    for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
58
59        ListIt inst_list_it = instList[tid].begin();
60
61        MemDepHashIt hash_it;
62
63        while (!instList[tid].empty()) {
64            hash_it = memDepHash.find((*inst_list_it)->seqNum);
65
66            assert(hash_it != memDepHash.end());
67
68            memDepHash.erase(hash_it);
69
70            instList[tid].erase(inst_list_it++);
71        }
72    }
73
74#ifdef DEBUG
75    assert(MemDepEntry::memdep_count == 0);
76#endif
77}
78
79template <class MemDepPred, class Impl>
80void
81MemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, ThreadID tid)
82{
83    DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
84
85    _name = csprintf("%s.memDep%d", params->name, tid);
86    id = tid;
87
88    depPred.init(params->SSITSize, params->LFSTSize);
89}
90
91template <class MemDepPred, class Impl>
92void
93MemDepUnit<MemDepPred, Impl>::regStats()
94{
95    insertedLoads
96        .name(name() + ".insertedLoads")
97        .desc("Number of loads inserted to the mem dependence unit.");
98
99    insertedStores
100        .name(name() + ".insertedStores")
101        .desc("Number of stores inserted to the mem dependence unit.");
102
103    conflictingLoads
104        .name(name() + ".conflictingLoads")
105        .desc("Number of conflicting loads.");
106
107    conflictingStores
108        .name(name() + ".conflictingStores")
109        .desc("Number of conflicting stores.");
110}
111
112template <class MemDepPred, class Impl>
113void
114MemDepUnit<MemDepPred, Impl>::switchOut()
115{
116    assert(instList[0].empty());
117    assert(instsToReplay.empty());
118    assert(memDepHash.empty());
119    // Clear any state.
120    for (int i = 0; i < Impl::MaxThreads; ++i) {
121        instList[i].clear();
122    }
123    instsToReplay.clear();
124    memDepHash.clear();
125}
126
127template <class MemDepPred, class Impl>
128void
129MemDepUnit<MemDepPred, Impl>::takeOverFrom()
130{
131    // Be sure to reset all state.
132    loadBarrier = storeBarrier = false;
133    loadBarrierSN = storeBarrierSN = 0;
134    depPred.clear();
135}
136
137template <class MemDepPred, class Impl>
138void
139MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
140{
141    iqPtr = iq_ptr;
142}
143
144template <class MemDepPred, class Impl>
145void
146MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
147{
148    ThreadID tid = inst->threadNumber;
149
150    MemDepEntryPtr inst_entry = new MemDepEntry(inst);
151
152    // Add the MemDepEntry to the hash.
153    memDepHash.insert(
154        std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
155#ifdef DEBUG
156    MemDepEntry::memdep_insert++;
157#endif
158
159    instList[tid].push_back(inst);
160
161    inst_entry->listIt = --(instList[tid].end());
162
163    // Check any barriers and the dependence predictor for any
164    // producing memrefs/stores.
165    InstSeqNum producing_store;
166    if (inst->isLoad() && loadBarrier) {
167        DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
168                loadBarrierSN);
169        producing_store = loadBarrierSN;
170    } else if (inst->isStore() && storeBarrier) {
171        DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
172                storeBarrierSN);
173        producing_store = storeBarrierSN;
174    } else {
175        producing_store = depPred.checkInst(inst->instAddr());
176    }
177
178    MemDepEntryPtr store_entry = NULL;
179
180    // If there is a producing store, try to find the entry.
181    if (producing_store != 0) {
182        DPRINTF(MemDepUnit, "Searching for producer\n");
183        MemDepHashIt hash_it = memDepHash.find(producing_store);
184
185        if (hash_it != memDepHash.end()) {
186            store_entry = (*hash_it).second;
187            DPRINTF(MemDepUnit, "Proucer found\n");
188        }
189    }
190
191    // If no store entry, then instruction can issue as soon as the registers
192    // are ready.
193    if (!store_entry) {
194        DPRINTF(MemDepUnit, "No dependency for inst PC "
195                "%s [sn:%lli].\n", inst->pcState(), inst->seqNum);
196
197        inst_entry->memDepReady = true;
198
199        if (inst->readyToIssue()) {
200            inst_entry->regsReady = true;
201
202            moveToReady(inst_entry);
203        }
204    } else {
205        // Otherwise make the instruction dependent on the store/barrier.
206        DPRINTF(MemDepUnit, "Adding to dependency list; "
207                "inst PC %s is dependent on [sn:%lli].\n",
208                inst->pcState(), producing_store);
209
210        if (inst->readyToIssue()) {
211            inst_entry->regsReady = true;
212        }
213
214        // Clear the bit saying this instruction can issue.
215        inst->clearCanIssue();
216
217        // Add this instruction to the list of dependents.
218        store_entry->dependInsts.push_back(inst_entry);
219
220        if (inst->isLoad()) {
221            ++conflictingLoads;
222        } else {
223            ++conflictingStores;
224        }
225    }
226
227    if (inst->isStore()) {
228        DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
229                inst->pcState(), inst->seqNum);
230
231        depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
232
233        ++insertedStores;
234    } else if (inst->isLoad()) {
235        ++insertedLoads;
236    } else {
237        panic("Unknown type! (most likely a barrier).");
238    }
239}
240
241template <class MemDepPred, class Impl>
242void
243MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
244{
245    ThreadID tid = inst->threadNumber;
246
247    MemDepEntryPtr inst_entry = new MemDepEntry(inst);
248
249    // Insert the MemDepEntry into the hash.
250    memDepHash.insert(
251        std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
252#ifdef DEBUG
253    MemDepEntry::memdep_insert++;
254#endif
255
256    // Add the instruction to the list.
257    instList[tid].push_back(inst);
258
259    inst_entry->listIt = --(instList[tid].end());
260
261    // Might want to turn this part into an inline function or something.
262    // It's shared between both insert functions.
263    if (inst->isStore()) {
264        DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
265                inst->pcState(), inst->seqNum);
266
267        depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
268
269        ++insertedStores;
270    } else if (inst->isLoad()) {
271        ++insertedLoads;
272    } else {
273        panic("Unknown type! (most likely a barrier).");
274    }
275}
276
277template <class MemDepPred, class Impl>
278void
279MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
280{
281    InstSeqNum barr_sn = barr_inst->seqNum;
282    // Memory barriers block loads and stores, write barriers only stores.
283    if (barr_inst->isMemBarrier()) {
284        loadBarrier = true;
285        loadBarrierSN = barr_sn;
286        storeBarrier = true;
287        storeBarrierSN = barr_sn;
288        DPRINTF(MemDepUnit, "Inserted a memory barrier %s SN:%lli\n",
289                barr_inst->pcState(),barr_sn);
290    } else if (barr_inst->isWriteBarrier()) {
291        storeBarrier = true;
292        storeBarrierSN = barr_sn;
293        DPRINTF(MemDepUnit, "Inserted a write barrier\n");
294    }
295
296    ThreadID tid = barr_inst->threadNumber;
297
298    MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
299
300    // Add the MemDepEntry to the hash.
301    memDepHash.insert(
302        std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
303#ifdef DEBUG
304    MemDepEntry::memdep_insert++;
305#endif
306
307    // Add the instruction to the instruction list.
308    instList[tid].push_back(barr_inst);
309
310    inst_entry->listIt = --(instList[tid].end());
311}
312
313template <class MemDepPred, class Impl>
314void
315MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
316{
317    DPRINTF(MemDepUnit, "Marking registers as ready for "
318            "instruction PC %s [sn:%lli].\n",
319            inst->pcState(), inst->seqNum);
320
321    MemDepEntryPtr inst_entry = findInHash(inst);
322
323    inst_entry->regsReady = true;
324
325    if (inst_entry->memDepReady) {
326        DPRINTF(MemDepUnit, "Instruction has its memory "
327                "dependencies resolved, adding it to the ready list.\n");
328
329        moveToReady(inst_entry);
330    } else {
331        DPRINTF(MemDepUnit, "Instruction still waiting on "
332                "memory dependency.\n");
333    }
334}
335
336template <class MemDepPred, class Impl>
337void
338MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
339{
340    DPRINTF(MemDepUnit, "Marking non speculative "
341            "instruction PC %s as ready [sn:%lli].\n",
342            inst->pcState(), inst->seqNum);
343
344    MemDepEntryPtr inst_entry = findInHash(inst);
345
346    moveToReady(inst_entry);
347}
348
349template <class MemDepPred, class Impl>
350void
351MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
352{
353    instsToReplay.push_back(inst);
354}
355
356template <class MemDepPred, class Impl>
357void
358MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
359{
360    DynInstPtr temp_inst;
361
362    // For now this replay function replays all waiting memory ops.
363    while (!instsToReplay.empty()) {
364        temp_inst = instsToReplay.front();
365
366        MemDepEntryPtr inst_entry = findInHash(temp_inst);
367
368        DPRINTF(MemDepUnit, "Replaying mem instruction PC %s [sn:%lli].\n",
369                temp_inst->pcState(), temp_inst->seqNum);
370
371        moveToReady(inst_entry);
372
373        instsToReplay.pop_front();
374    }
375}
376
377template <class MemDepPred, class Impl>
378void
379MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
380{
381    DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n",
382            inst->pcState(), inst->seqNum);
383
384    ThreadID tid = inst->threadNumber;
385
386    // Remove the instruction from the hash and the list.
387    MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
388
389    assert(hash_it != memDepHash.end());
390
391    instList[tid].erase((*hash_it).second->listIt);
392
393    (*hash_it).second = NULL;
394
395    memDepHash.erase(hash_it);
396#ifdef DEBUG
397    MemDepEntry::memdep_erase++;
398#endif
399}
400
401template <class MemDepPred, class Impl>
402void
403MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
404{
405    wakeDependents(inst);
406    completed(inst);
407
408    InstSeqNum barr_sn = inst->seqNum;
409    DPRINTF(MemDepUnit, "barrier completed: %s SN:%lli\n", inst->pcState(),
410            inst->seqNum);
411    if (inst->isMemBarrier()) {
412        if (loadBarrierSN == barr_sn)
413            loadBarrier = false;
414        if (storeBarrierSN == barr_sn)
415            storeBarrier = false;
416    } else if (inst->isWriteBarrier()) {
417        if (storeBarrierSN == barr_sn)
418            storeBarrier = false;
419    }
420}
421
422template <class MemDepPred, class Impl>
423void
424MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
425{
426    // Only stores and barriers have dependents.
427    if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
428        return;
429    }
430
431    MemDepEntryPtr inst_entry = findInHash(inst);
432
433    for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
434        MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
435
436        if (!woken_inst->inst) {
437            // Potentially removed mem dep entries could be on this list
438            continue;
439        }
440
441        DPRINTF(MemDepUnit, "Waking up a dependent inst, "
442                "[sn:%lli].\n",
443                woken_inst->inst->seqNum);
444
445        if (woken_inst->regsReady && !woken_inst->squashed) {
446            moveToReady(woken_inst);
447        } else {
448            woken_inst->memDepReady = true;
449        }
450    }
451
452    inst_entry->dependInsts.clear();
453}
454
455template <class MemDepPred, class Impl>
456void
457MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
458                                     ThreadID tid)
459{
460    if (!instsToReplay.empty()) {
461        ListIt replay_it = instsToReplay.begin();
462        while (replay_it != instsToReplay.end()) {
463            if ((*replay_it)->threadNumber == tid &&
464                (*replay_it)->seqNum > squashed_num) {
465                instsToReplay.erase(replay_it++);
466            } else {
467                ++replay_it;
468            }
469        }
470    }
471
472    ListIt squash_it = instList[tid].end();
473    --squash_it;
474
475    MemDepHashIt hash_it;
476
477    while (!instList[tid].empty() &&
478           (*squash_it)->seqNum > squashed_num) {
479
480        DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
481                (*squash_it)->seqNum);
482
483        if ((*squash_it)->seqNum == loadBarrierSN)
484              loadBarrier = false;
485
486        if ((*squash_it)->seqNum == storeBarrierSN)
487              storeBarrier = false;
488
489        hash_it = memDepHash.find((*squash_it)->seqNum);
490
491        assert(hash_it != memDepHash.end());
492
493        (*hash_it).second->squashed = true;
494
495        (*hash_it).second = NULL;
496
497        memDepHash.erase(hash_it);
498#ifdef DEBUG
499        MemDepEntry::memdep_erase++;
500#endif
501
502        instList[tid].erase(squash_it--);
503    }
504
505    // Tell the dependency predictor to squash as well.
506    depPred.squash(squashed_num, tid);
507}
508
509template <class MemDepPred, class Impl>
510void
511MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
512                                        DynInstPtr &violating_load)
513{
514    DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
515            " load: %#x, store: %#x\n", violating_load->instAddr(),
516            store_inst->instAddr());
517    // Tell the memory dependence unit of the violation.
518    depPred.violation(store_inst->instAddr(), violating_load->instAddr());
519}
520
521template <class MemDepPred, class Impl>
522void
523MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
524{
525    DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
526            inst->instAddr(), inst->seqNum);
527
528    depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore());
529}
530
531template <class MemDepPred, class Impl>
532inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
533MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
534{
535    MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
536
537    assert(hash_it != memDepHash.end());
538
539    return (*hash_it).second;
540}
541
542template <class MemDepPred, class Impl>
543inline void
544MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
545{
546    DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
547            "to the ready list.\n", woken_inst_entry->inst->seqNum);
548
549    assert(!woken_inst_entry->squashed);
550
551    iqPtr->addReadyMemInst(woken_inst_entry->inst);
552}
553
554
555template <class MemDepPred, class Impl>
556void
557MemDepUnit<MemDepPred, Impl>::dumpLists()
558{
559    for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
560        cprintf("Instruction list %i size: %i\n",
561                tid, instList[tid].size());
562
563        ListIt inst_list_it = instList[tid].begin();
564        int num = 0;
565
566        while (inst_list_it != instList[tid].end()) {
567            cprintf("Instruction:%i\nPC: %s\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
568                    "Squashed:%i\n\n",
569                    num, (*inst_list_it)->pcState(),
570                    (*inst_list_it)->seqNum,
571                    (*inst_list_it)->threadNumber,
572                    (*inst_list_it)->isIssued(),
573                    (*inst_list_it)->isSquashed());
574            inst_list_it++;
575            ++num;
576        }
577    }
578
579    cprintf("Memory dependence hash size: %i\n", memDepHash.size());
580
581#ifdef DEBUG
582    cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
583#endif
584}
585