mem_dep_unit_impl.hh revision 2670:9107b8bd08cd
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include <map> 32 33#include "cpu/o3/inst_queue.hh" 34#include "cpu/o3/mem_dep_unit.hh" 35 36template <class MemDepPred, class Impl> 37MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params) 38 : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false), 39 loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL) 40{ 41 DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n"); 42} 43 44template <class MemDepPred, class Impl> 45MemDepUnit<MemDepPred, Impl>::~MemDepUnit() 46{ 47 for (int tid=0; tid < Impl::MaxThreads; tid++) { 48 49 ListIt inst_list_it = instList[tid].begin(); 50 51 MemDepHashIt hash_it; 52 53 while (!instList[tid].empty()) { 54 hash_it = memDepHash.find((*inst_list_it)->seqNum); 55 56 assert(hash_it != memDepHash.end()); 57 58 memDepHash.erase(hash_it); 59 60 instList[tid].erase(inst_list_it++); 61 } 62 } 63 64 assert(MemDepEntry::memdep_count == 0); 65} 66 67template <class MemDepPred, class Impl> 68std::string 69MemDepUnit<MemDepPred, Impl>::name() const 70{ 71 return "memdepunit"; 72} 73 74template <class MemDepPred, class Impl> 75void 76MemDepUnit<MemDepPred, Impl>::init(Params *params, int tid) 77{ 78 DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid); 79 80 id = tid; 81 82 depPred.init(params->SSITSize, params->LFSTSize); 83} 84 85template <class MemDepPred, class Impl> 86void 87MemDepUnit<MemDepPred, Impl>::regStats() 88{ 89 insertedLoads 90 .name(name() + ".memDep.insertedLoads") 91 .desc("Number of loads inserted to the mem dependence unit."); 92 93 insertedStores 94 .name(name() + ".memDep.insertedStores") 95 .desc("Number of stores inserted to the mem dependence unit."); 96 97 conflictingLoads 98 .name(name() + ".memDep.conflictingLoads") 99 .desc("Number of conflicting loads."); 100 101 conflictingStores 102 .name(name() + ".memDep.conflictingStores") 103 .desc("Number of conflicting stores."); 104} 105 106template <class MemDepPred, class Impl> 107void 108MemDepUnit<MemDepPred, Impl>::switchOut() 109{ 110 for (int i = 0; i < Impl::MaxThreads; ++i) { 111 instList[i].clear(); 112 } 113 instsToReplay.clear(); 114 memDepHash.clear(); 115} 116 117template <class MemDepPred, class Impl> 118void 119MemDepUnit<MemDepPred, Impl>::takeOverFrom() 120{ 121 loadBarrier = storeBarrier = false; 122 loadBarrierSN = storeBarrierSN = 0; 123 depPred.clear(); 124} 125 126template <class MemDepPred, class Impl> 127void 128MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr) 129{ 130 iqPtr = iq_ptr; 131} 132 133template <class MemDepPred, class Impl> 134void 135MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst) 136{ 137 unsigned tid = inst->threadNumber; 138 139 MemDepEntryPtr inst_entry = new MemDepEntry(inst); 140 141 // Add the MemDepEntry to the hash. 142 memDepHash.insert( 143 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 144 MemDepEntry::memdep_insert++; 145 146 instList[tid].push_back(inst); 147 148 inst_entry->listIt = --(instList[tid].end()); 149 150 // Check any barriers and the dependence predictor for any 151 // producing stores. 152 InstSeqNum producing_store; 153 if (inst->isLoad() && loadBarrier) { 154 producing_store = loadBarrierSN; 155 } else if (inst->isStore() && storeBarrier) { 156 producing_store = storeBarrierSN; 157 } else { 158 producing_store = depPred.checkInst(inst->readPC()); 159 } 160 161 MemDepEntryPtr store_entry = NULL; 162 163 // If there is a producing store, try to find the entry. 164 if (producing_store != 0) { 165 MemDepHashIt hash_it = memDepHash.find(producing_store); 166 167 if (hash_it != memDepHash.end()) { 168 store_entry = (*hash_it).second; 169 } 170 } 171 172 // If no store entry, then instruction can issue as soon as the registers 173 // are ready. 174 if (!store_entry) { 175 DPRINTF(MemDepUnit, "No dependency for inst PC " 176 "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum); 177 178 inst_entry->memDepReady = true; 179 180 if (inst->readyToIssue()) { 181 inst_entry->regsReady = true; 182 183 moveToReady(inst_entry); 184 } 185 } else { 186 // Otherwise make the instruction dependent on the store/barrier. 187 DPRINTF(MemDepUnit, "Adding to dependency list; " 188 "inst PC %#x is dependent on [sn:%lli].\n", 189 inst->readPC(), producing_store); 190 191 if (inst->readyToIssue()) { 192 inst_entry->regsReady = true; 193 } 194 195 // Add this instruction to the list of dependents. 196 store_entry->dependInsts.push_back(inst_entry); 197 198 if (inst->isLoad()) { 199 ++conflictingLoads; 200 } else { 201 ++conflictingStores; 202 } 203 } 204 205 if (inst->isStore()) { 206 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n", 207 inst->readPC(), inst->seqNum); 208 209 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber); 210 211 ++insertedStores; 212 } else if (inst->isLoad()) { 213 ++insertedLoads; 214 } else { 215 panic("Unknown type! (most likely a barrier)."); 216 } 217} 218 219template <class MemDepPred, class Impl> 220void 221MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst) 222{ 223 unsigned tid = inst->threadNumber; 224 225 MemDepEntryPtr inst_entry = new MemDepEntry(inst); 226 227 // Insert the MemDepEntry into the hash. 228 memDepHash.insert( 229 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 230 MemDepEntry::memdep_insert++; 231 232 // Add the instruction to the list. 233 instList[tid].push_back(inst); 234 235 inst_entry->listIt = --(instList[tid].end()); 236 237 // Might want to turn this part into an inline function or something. 238 // It's shared between both insert functions. 239 if (inst->isStore()) { 240 DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n", 241 inst->readPC(), inst->seqNum); 242 243 depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber); 244 245 ++insertedStores; 246 } else if (inst->isLoad()) { 247 ++insertedLoads; 248 } else { 249 panic("Unknown type! (most likely a barrier)."); 250 } 251} 252 253template <class MemDepPred, class Impl> 254void 255MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst) 256{ 257 InstSeqNum barr_sn = barr_inst->seqNum; 258 if (barr_inst->isMemBarrier()) { 259 loadBarrier = true; 260 loadBarrierSN = barr_sn; 261 storeBarrier = true; 262 storeBarrierSN = barr_sn; 263 DPRINTF(MemDepUnit, "Inserted a memory barrier\n"); 264 } else if (barr_inst->isWriteBarrier()) { 265 storeBarrier = true; 266 storeBarrierSN = barr_sn; 267 DPRINTF(MemDepUnit, "Inserted a write barrier\n"); 268 } 269 270 unsigned tid = barr_inst->threadNumber; 271 272 MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst); 273 274 // Add the MemDepEntry to the hash. 275 memDepHash.insert( 276 std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry)); 277 MemDepEntry::memdep_insert++; 278 279 // Add the instruction to the instruction list. 280 instList[tid].push_back(barr_inst); 281 282 inst_entry->listIt = --(instList[tid].end()); 283} 284 285template <class MemDepPred, class Impl> 286void 287MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst) 288{ 289 DPRINTF(MemDepUnit, "Marking registers as ready for " 290 "instruction PC %#x [sn:%lli].\n", 291 inst->readPC(), inst->seqNum); 292 293 MemDepEntryPtr inst_entry = findInHash(inst); 294 295 inst_entry->regsReady = true; 296 297 if (inst_entry->memDepReady) { 298 DPRINTF(MemDepUnit, "Instruction has its memory " 299 "dependencies resolved, adding it to the ready list.\n"); 300 301 moveToReady(inst_entry); 302 } else { 303 DPRINTF(MemDepUnit, "Instruction still waiting on " 304 "memory dependency.\n"); 305 } 306} 307 308template <class MemDepPred, class Impl> 309void 310MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst) 311{ 312 DPRINTF(MemDepUnit, "Marking non speculative " 313 "instruction PC %#x as ready [sn:%lli].\n", 314 inst->readPC(), inst->seqNum); 315 316 MemDepEntryPtr inst_entry = findInHash(inst); 317 318 moveToReady(inst_entry); 319} 320 321template <class MemDepPred, class Impl> 322void 323MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst) 324{ 325 instsToReplay.push_back(inst); 326} 327 328template <class MemDepPred, class Impl> 329void 330MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst) 331{ 332 DynInstPtr temp_inst; 333 bool found_inst = false; 334 335 while (!instsToReplay.empty()) { 336 temp_inst = instsToReplay.front(); 337 338 MemDepEntryPtr inst_entry = findInHash(temp_inst); 339 340 DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x " 341 "[sn:%lli].\n", 342 temp_inst->readPC(), temp_inst->seqNum); 343 344 moveToReady(inst_entry); 345 346 if (temp_inst == inst) { 347 found_inst = true; 348 } 349 350 instsToReplay.pop_front(); 351 } 352 353 assert(found_inst); 354} 355 356template <class MemDepPred, class Impl> 357void 358MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst) 359{ 360 DPRINTF(MemDepUnit, "Completed mem instruction PC %#x " 361 "[sn:%lli].\n", 362 inst->readPC(), inst->seqNum); 363 364 unsigned tid = inst->threadNumber; 365 366 // Remove the instruction from the hash and the list. 367 MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 368 369 assert(hash_it != memDepHash.end()); 370 371 instList[tid].erase((*hash_it).second->listIt); 372 373 (*hash_it).second = NULL; 374 375 memDepHash.erase(hash_it); 376 MemDepEntry::memdep_erase++; 377} 378 379template <class MemDepPred, class Impl> 380void 381MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst) 382{ 383 wakeDependents(inst); 384 completed(inst); 385 386 InstSeqNum barr_sn = inst->seqNum; 387 388 if (inst->isMemBarrier()) { 389 assert(loadBarrier && storeBarrier); 390 if (loadBarrierSN == barr_sn) 391 loadBarrier = false; 392 if (storeBarrierSN == barr_sn) 393 storeBarrier = false; 394 } else if (inst->isWriteBarrier()) { 395 assert(storeBarrier); 396 if (storeBarrierSN == barr_sn) 397 storeBarrier = false; 398 } 399} 400 401template <class MemDepPred, class Impl> 402void 403MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst) 404{ 405 // Only stores and barriers have dependents. 406 if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) { 407 return; 408 } 409 410 MemDepEntryPtr inst_entry = findInHash(inst); 411 412 for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) { 413 MemDepEntryPtr woken_inst = inst_entry->dependInsts[i]; 414 415 if (!woken_inst->inst) { 416 // Potentially removed mem dep entries could be on this list 417 continue; 418 } 419 420 DPRINTF(MemDepUnit, "Waking up a dependent inst, " 421 "[sn:%lli].\n", 422 woken_inst->inst->seqNum); 423 424 if (woken_inst->regsReady && !woken_inst->squashed) { 425 moveToReady(woken_inst); 426 } else { 427 woken_inst->memDepReady = true; 428 } 429 } 430 431 inst_entry->dependInsts.clear(); 432} 433 434template <class MemDepPred, class Impl> 435void 436MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num, 437 unsigned tid) 438{ 439 if (!instsToReplay.empty()) { 440 ListIt replay_it = instsToReplay.begin(); 441 while (replay_it != instsToReplay.end()) { 442 if ((*replay_it)->threadNumber == tid && 443 (*replay_it)->seqNum > squashed_num) { 444 instsToReplay.erase(replay_it++); 445 } else { 446 ++replay_it; 447 } 448 } 449 } 450 451 ListIt squash_it = instList[tid].end(); 452 --squash_it; 453 454 MemDepHashIt hash_it; 455 456 while (!instList[tid].empty() && 457 (*squash_it)->seqNum > squashed_num) { 458 459 DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n", 460 (*squash_it)->seqNum); 461 462 hash_it = memDepHash.find((*squash_it)->seqNum); 463 464 assert(hash_it != memDepHash.end()); 465 466 (*hash_it).second->squashed = true; 467 468 (*hash_it).second = NULL; 469 470 memDepHash.erase(hash_it); 471 MemDepEntry::memdep_erase++; 472 473 instList[tid].erase(squash_it--); 474 } 475 476 // Tell the dependency predictor to squash as well. 477 depPred.squash(squashed_num, tid); 478} 479 480template <class MemDepPred, class Impl> 481void 482MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst, 483 DynInstPtr &violating_load) 484{ 485 DPRINTF(MemDepUnit, "Passing violating PCs to store sets," 486 " load: %#x, store: %#x\n", violating_load->readPC(), 487 store_inst->readPC()); 488 // Tell the memory dependence unit of the violation. 489 depPred.violation(violating_load->readPC(), store_inst->readPC()); 490} 491 492template <class MemDepPred, class Impl> 493void 494MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst) 495{ 496 DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n", 497 inst->readPC(), inst->seqNum); 498 499 depPred.issued(inst->readPC(), inst->seqNum, inst->isStore()); 500} 501 502template <class MemDepPred, class Impl> 503inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr & 504MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst) 505{ 506 MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 507 508 assert(hash_it != memDepHash.end()); 509 510 return (*hash_it).second; 511} 512 513template <class MemDepPred, class Impl> 514inline void 515MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry) 516{ 517 DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] " 518 "to the ready list.\n", woken_inst_entry->inst->seqNum); 519 520 assert(!woken_inst_entry->squashed); 521 522 iqPtr->addReadyMemInst(woken_inst_entry->inst); 523} 524 525 526template <class MemDepPred, class Impl> 527void 528MemDepUnit<MemDepPred, Impl>::dumpLists() 529{ 530 for (unsigned tid=0; tid < Impl::MaxThreads; tid++) { 531 cprintf("Instruction list %i size: %i\n", 532 tid, instList[tid].size()); 533 534 ListIt inst_list_it = instList[tid].begin(); 535 int num = 0; 536 537 while (inst_list_it != instList[tid].end()) { 538 cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n" 539 "Squashed:%i\n\n", 540 num, (*inst_list_it)->readPC(), 541 (*inst_list_it)->seqNum, 542 (*inst_list_it)->threadNumber, 543 (*inst_list_it)->isIssued(), 544 (*inst_list_it)->isSquashed()); 545 inst_list_it++; 546 ++num; 547 } 548 } 549 550 cprintf("Memory dependence hash size: %i\n", memDepHash.size()); 551 552 cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count); 553} 554