mem_dep_unit_impl.hh revision 2654:9559cfa91b9d 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <map>
30
31#include "cpu/o3/inst_queue.hh"
32#include "cpu/o3/mem_dep_unit.hh"
33
34template <class MemDepPred, class Impl>
35MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params)
36    : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
37      loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
38{
39    DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
40}
41
42template <class MemDepPred, class Impl>
43MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
44{
45    for (int tid=0; tid < Impl::MaxThreads; tid++) {
46
47        ListIt inst_list_it = instList[tid].begin();
48
49        MemDepHashIt hash_it;
50
51        while (!instList[tid].empty()) {
52            hash_it = memDepHash.find((*inst_list_it)->seqNum);
53
54            assert(hash_it != memDepHash.end());
55
56            memDepHash.erase(hash_it);
57
58            instList[tid].erase(inst_list_it++);
59        }
60    }
61
62    assert(MemDepEntry::memdep_count == 0);
63}
64
65template <class MemDepPred, class Impl>
66std::string
67MemDepUnit<MemDepPred, Impl>::name() const
68{
69    return "memdepunit";
70}
71
72template <class MemDepPred, class Impl>
73void
74MemDepUnit<MemDepPred, Impl>::init(Params *params, int tid)
75{
76    DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
77
78    id = tid;
79
80    depPred.init(params->SSITSize, params->LFSTSize);
81}
82
83template <class MemDepPred, class Impl>
84void
85MemDepUnit<MemDepPred, Impl>::regStats()
86{
87    insertedLoads
88        .name(name() + ".memDep.insertedLoads")
89        .desc("Number of loads inserted to the mem dependence unit.");
90
91    insertedStores
92        .name(name() + ".memDep.insertedStores")
93        .desc("Number of stores inserted to the mem dependence unit.");
94
95    conflictingLoads
96        .name(name() + ".memDep.conflictingLoads")
97        .desc("Number of conflicting loads.");
98
99    conflictingStores
100        .name(name() + ".memDep.conflictingStores")
101        .desc("Number of conflicting stores.");
102}
103
104template <class MemDepPred, class Impl>
105void
106MemDepUnit<MemDepPred, Impl>::switchOut()
107{
108    for (int i = 0; i < Impl::MaxThreads; ++i) {
109        instList[i].clear();
110    }
111    instsToReplay.clear();
112    memDepHash.clear();
113}
114
115template <class MemDepPred, class Impl>
116void
117MemDepUnit<MemDepPred, Impl>::takeOverFrom()
118{
119    loadBarrier = storeBarrier = false;
120    loadBarrierSN = storeBarrierSN = 0;
121    depPred.clear();
122}
123
124template <class MemDepPred, class Impl>
125void
126MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
127{
128    iqPtr = iq_ptr;
129}
130
131template <class MemDepPred, class Impl>
132void
133MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
134{
135    unsigned tid = inst->threadNumber;
136
137    MemDepEntryPtr inst_entry = new MemDepEntry(inst);
138
139    // Add the MemDepEntry to the hash.
140    memDepHash.insert(
141        std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
142    MemDepEntry::memdep_insert++;
143
144    instList[tid].push_back(inst);
145
146    inst_entry->listIt = --(instList[tid].end());
147
148    // Check any barriers and the dependence predictor for any
149    // producing stores.
150    InstSeqNum producing_store;
151    if (inst->isLoad() && loadBarrier) {
152        producing_store = loadBarrierSN;
153    } else if (inst->isStore() && storeBarrier) {
154        producing_store = storeBarrierSN;
155    } else {
156        producing_store = depPred.checkInst(inst->readPC());
157    }
158
159    MemDepEntryPtr store_entry = NULL;
160
161    // If there is a producing store, try to find the entry.
162    if (producing_store != 0) {
163        MemDepHashIt hash_it = memDepHash.find(producing_store);
164
165        if (hash_it != memDepHash.end()) {
166            store_entry = (*hash_it).second;
167        }
168    }
169
170    // If no store entry, then instruction can issue as soon as the registers
171    // are ready.
172    if (!store_entry) {
173        DPRINTF(MemDepUnit, "No dependency for inst PC "
174                "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum);
175
176        inst_entry->memDepReady = true;
177
178        if (inst->readyToIssue()) {
179            inst_entry->regsReady = true;
180
181            moveToReady(inst_entry);
182        }
183    } else {
184        // Otherwise make the instruction dependent on the store/barrier.
185        DPRINTF(MemDepUnit, "Adding to dependency list; "
186                "inst PC %#x is dependent on [sn:%lli].\n",
187                inst->readPC(), producing_store);
188
189        if (inst->readyToIssue()) {
190            inst_entry->regsReady = true;
191        }
192
193        // Add this instruction to the list of dependents.
194        store_entry->dependInsts.push_back(inst_entry);
195
196        if (inst->isLoad()) {
197            ++conflictingLoads;
198        } else {
199            ++conflictingStores;
200        }
201    }
202
203    if (inst->isStore()) {
204        DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
205                inst->readPC(), inst->seqNum);
206
207        depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
208
209        ++insertedStores;
210    } else if (inst->isLoad()) {
211        ++insertedLoads;
212    } else {
213        panic("Unknown type! (most likely a barrier).");
214    }
215}
216
217template <class MemDepPred, class Impl>
218void
219MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
220{
221    unsigned tid = inst->threadNumber;
222
223    MemDepEntryPtr inst_entry = new MemDepEntry(inst);
224
225    // Insert the MemDepEntry into the hash.
226    memDepHash.insert(
227        std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
228    MemDepEntry::memdep_insert++;
229
230    // Add the instruction to the list.
231    instList[tid].push_back(inst);
232
233    inst_entry->listIt = --(instList[tid].end());
234
235    // Might want to turn this part into an inline function or something.
236    // It's shared between both insert functions.
237    if (inst->isStore()) {
238        DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
239                inst->readPC(), inst->seqNum);
240
241        depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
242
243        ++insertedStores;
244    } else if (inst->isLoad()) {
245        ++insertedLoads;
246    } else {
247        panic("Unknown type! (most likely a barrier).");
248    }
249}
250
251template <class MemDepPred, class Impl>
252void
253MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
254{
255    InstSeqNum barr_sn = barr_inst->seqNum;
256    if (barr_inst->isMemBarrier()) {
257        loadBarrier = true;
258        loadBarrierSN = barr_sn;
259        storeBarrier = true;
260        storeBarrierSN = barr_sn;
261        DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
262    } else if (barr_inst->isWriteBarrier()) {
263        storeBarrier = true;
264        storeBarrierSN = barr_sn;
265        DPRINTF(MemDepUnit, "Inserted a write barrier\n");
266    }
267
268    unsigned tid = barr_inst->threadNumber;
269
270    MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
271
272    // Add the MemDepEntry to the hash.
273    memDepHash.insert(
274        std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
275    MemDepEntry::memdep_insert++;
276
277    // Add the instruction to the instruction list.
278    instList[tid].push_back(barr_inst);
279
280    inst_entry->listIt = --(instList[tid].end());
281}
282
283template <class MemDepPred, class Impl>
284void
285MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
286{
287    DPRINTF(MemDepUnit, "Marking registers as ready for "
288            "instruction PC %#x [sn:%lli].\n",
289            inst->readPC(), inst->seqNum);
290
291    MemDepEntryPtr inst_entry = findInHash(inst);
292
293    inst_entry->regsReady = true;
294
295    if (inst_entry->memDepReady) {
296        DPRINTF(MemDepUnit, "Instruction has its memory "
297                "dependencies resolved, adding it to the ready list.\n");
298
299        moveToReady(inst_entry);
300    } else {
301        DPRINTF(MemDepUnit, "Instruction still waiting on "
302                "memory dependency.\n");
303    }
304}
305
306template <class MemDepPred, class Impl>
307void
308MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
309{
310    DPRINTF(MemDepUnit, "Marking non speculative "
311            "instruction PC %#x as ready [sn:%lli].\n",
312            inst->readPC(), inst->seqNum);
313
314    MemDepEntryPtr inst_entry = findInHash(inst);
315
316    moveToReady(inst_entry);
317}
318
319template <class MemDepPred, class Impl>
320void
321MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
322{
323    instsToReplay.push_back(inst);
324}
325
326template <class MemDepPred, class Impl>
327void
328MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
329{
330    DynInstPtr temp_inst;
331    bool found_inst = false;
332
333    while (!instsToReplay.empty()) {
334        temp_inst = instsToReplay.front();
335
336        MemDepEntryPtr inst_entry = findInHash(temp_inst);
337
338        DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
339                "[sn:%lli].\n",
340                temp_inst->readPC(), temp_inst->seqNum);
341
342        moveToReady(inst_entry);
343
344        if (temp_inst == inst) {
345            found_inst = true;
346        }
347
348        instsToReplay.pop_front();
349    }
350
351    assert(found_inst);
352}
353
354template <class MemDepPred, class Impl>
355void
356MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
357{
358    DPRINTF(MemDepUnit, "Completed mem instruction PC %#x "
359            "[sn:%lli].\n",
360            inst->readPC(), inst->seqNum);
361
362    unsigned tid = inst->threadNumber;
363
364    // Remove the instruction from the hash and the list.
365    MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
366
367    assert(hash_it != memDepHash.end());
368
369    instList[tid].erase((*hash_it).second->listIt);
370
371    (*hash_it).second = NULL;
372
373    memDepHash.erase(hash_it);
374    MemDepEntry::memdep_erase++;
375}
376
377template <class MemDepPred, class Impl>
378void
379MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
380{
381    wakeDependents(inst);
382    completed(inst);
383
384    InstSeqNum barr_sn = inst->seqNum;
385
386    if (inst->isMemBarrier()) {
387        assert(loadBarrier && storeBarrier);
388        if (loadBarrierSN == barr_sn)
389            loadBarrier = false;
390        if (storeBarrierSN == barr_sn)
391            storeBarrier = false;
392    } else if (inst->isWriteBarrier()) {
393        assert(storeBarrier);
394        if (storeBarrierSN == barr_sn)
395            storeBarrier = false;
396    }
397}
398
399template <class MemDepPred, class Impl>
400void
401MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
402{
403    // Only stores and barriers have dependents.
404    if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
405        return;
406    }
407
408    MemDepEntryPtr inst_entry = findInHash(inst);
409
410    for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
411        MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
412
413        if (!woken_inst->inst) {
414            // Potentially removed mem dep entries could be on this list
415            continue;
416        }
417
418        DPRINTF(MemDepUnit, "Waking up a dependent inst, "
419                "[sn:%lli].\n",
420                woken_inst->inst->seqNum);
421
422        if (woken_inst->regsReady && !woken_inst->squashed) {
423            moveToReady(woken_inst);
424        } else {
425            woken_inst->memDepReady = true;
426        }
427    }
428
429    inst_entry->dependInsts.clear();
430}
431
432template <class MemDepPred, class Impl>
433void
434MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
435                                     unsigned tid)
436{
437    if (!instsToReplay.empty()) {
438        ListIt replay_it = instsToReplay.begin();
439        while (replay_it != instsToReplay.end()) {
440            if ((*replay_it)->threadNumber == tid &&
441                (*replay_it)->seqNum > squashed_num) {
442                instsToReplay.erase(replay_it++);
443            } else {
444                ++replay_it;
445            }
446        }
447    }
448
449    ListIt squash_it = instList[tid].end();
450    --squash_it;
451
452    MemDepHashIt hash_it;
453
454    while (!instList[tid].empty() &&
455           (*squash_it)->seqNum > squashed_num) {
456
457        DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
458                (*squash_it)->seqNum);
459
460        hash_it = memDepHash.find((*squash_it)->seqNum);
461
462        assert(hash_it != memDepHash.end());
463
464        (*hash_it).second->squashed = true;
465
466        (*hash_it).second = NULL;
467
468        memDepHash.erase(hash_it);
469        MemDepEntry::memdep_erase++;
470
471        instList[tid].erase(squash_it--);
472    }
473
474    // Tell the dependency predictor to squash as well.
475    depPred.squash(squashed_num, tid);
476}
477
478template <class MemDepPred, class Impl>
479void
480MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
481                                        DynInstPtr &violating_load)
482{
483    DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
484            " load: %#x, store: %#x\n", violating_load->readPC(),
485            store_inst->readPC());
486    // Tell the memory dependence unit of the violation.
487    depPred.violation(violating_load->readPC(), store_inst->readPC());
488}
489
490template <class MemDepPred, class Impl>
491void
492MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
493{
494    DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
495            inst->readPC(), inst->seqNum);
496
497    depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
498}
499
500template <class MemDepPred, class Impl>
501inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
502MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
503{
504    MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
505
506    assert(hash_it != memDepHash.end());
507
508    return (*hash_it).second;
509}
510
511template <class MemDepPred, class Impl>
512inline void
513MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
514{
515    DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
516            "to the ready list.\n", woken_inst_entry->inst->seqNum);
517
518    assert(!woken_inst_entry->squashed);
519
520    iqPtr->addReadyMemInst(woken_inst_entry->inst);
521}
522
523
524template <class MemDepPred, class Impl>
525void
526MemDepUnit<MemDepPred, Impl>::dumpLists()
527{
528    for (unsigned tid=0; tid < Impl::MaxThreads; tid++) {
529        cprintf("Instruction list %i size: %i\n",
530                tid, instList[tid].size());
531
532        ListIt inst_list_it = instList[tid].begin();
533        int num = 0;
534
535        while (inst_list_it != instList[tid].end()) {
536            cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
537                    "Squashed:%i\n\n",
538                    num, (*inst_list_it)->readPC(),
539                    (*inst_list_it)->seqNum,
540                    (*inst_list_it)->threadNumber,
541                    (*inst_list_it)->isIssued(),
542                    (*inst_list_it)->isSquashed());
543            inst_list_it++;
544            ++num;
545        }
546    }
547
548    cprintf("Memory dependence hash size: %i\n", memDepHash.size());
549
550    cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
551}
552