mem_dep_unit_impl.hh revision 10473:4cbe53150053 
1/*
2 * Copyright (c) 2012, 2014 ARM Limited
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4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
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18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
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26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_MEM_DEP_UNIT_IMPL_HH__
44#define __CPU_O3_MEM_DEP_UNIT_IMPL_HH__
45
46#include <map>
47
48#include "cpu/o3/inst_queue.hh"
49#include "cpu/o3/mem_dep_unit.hh"
50#include "debug/MemDepUnit.hh"
51#include "params/DerivO3CPU.hh"
52
53template <class MemDepPred, class Impl>
54MemDepUnit<MemDepPred, Impl>::MemDepUnit()
55    : loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
56      storeBarrierSN(0), iqPtr(NULL)
57{
58}
59
60template <class MemDepPred, class Impl>
61MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params)
62    : _name(params->name + ".memdepunit"),
63      depPred(params->store_set_clear_period, params->SSITSize,
64              params->LFSTSize),
65      loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
66      storeBarrierSN(0), iqPtr(NULL)
67{
68    DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
69}
70
71template <class MemDepPred, class Impl>
72MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
73{
74    for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
75
76        ListIt inst_list_it = instList[tid].begin();
77
78        MemDepHashIt hash_it;
79
80        while (!instList[tid].empty()) {
81            hash_it = memDepHash.find((*inst_list_it)->seqNum);
82
83            assert(hash_it != memDepHash.end());
84
85            memDepHash.erase(hash_it);
86
87            instList[tid].erase(inst_list_it++);
88        }
89    }
90
91#ifdef DEBUG
92    assert(MemDepEntry::memdep_count == 0);
93#endif
94}
95
96template <class MemDepPred, class Impl>
97void
98MemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, ThreadID tid)
99{
100    DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
101
102    _name = csprintf("%s.memDep%d", params->name, tid);
103    id = tid;
104
105    depPred.init(params->store_set_clear_period, params->SSITSize,
106            params->LFSTSize);
107}
108
109template <class MemDepPred, class Impl>
110void
111MemDepUnit<MemDepPred, Impl>::regStats()
112{
113    insertedLoads
114        .name(name() + ".insertedLoads")
115        .desc("Number of loads inserted to the mem dependence unit.");
116
117    insertedStores
118        .name(name() + ".insertedStores")
119        .desc("Number of stores inserted to the mem dependence unit.");
120
121    conflictingLoads
122        .name(name() + ".conflictingLoads")
123        .desc("Number of conflicting loads.");
124
125    conflictingStores
126        .name(name() + ".conflictingStores")
127        .desc("Number of conflicting stores.");
128}
129
130template <class MemDepPred, class Impl>
131void
132MemDepUnit<MemDepPred, Impl>::drainSanityCheck() const
133{
134    assert(instsToReplay.empty());
135    assert(memDepHash.empty());
136    for (int i = 0; i < Impl::MaxThreads; ++i)
137        assert(instList[i].empty());
138    assert(instsToReplay.empty());
139    assert(memDepHash.empty());
140}
141
142template <class MemDepPred, class Impl>
143void
144MemDepUnit<MemDepPred, Impl>::takeOverFrom()
145{
146    // Be sure to reset all state.
147    loadBarrier = storeBarrier = false;
148    loadBarrierSN = storeBarrierSN = 0;
149    depPred.clear();
150}
151
152template <class MemDepPred, class Impl>
153void
154MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
155{
156    iqPtr = iq_ptr;
157}
158
159template <class MemDepPred, class Impl>
160void
161MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
162{
163    ThreadID tid = inst->threadNumber;
164
165    MemDepEntryPtr inst_entry = std::make_shared<MemDepEntry>(inst);
166
167    // Add the MemDepEntry to the hash.
168    memDepHash.insert(
169        std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
170#ifdef DEBUG
171    MemDepEntry::memdep_insert++;
172#endif
173
174    instList[tid].push_back(inst);
175
176    inst_entry->listIt = --(instList[tid].end());
177
178    // Check any barriers and the dependence predictor for any
179    // producing memrefs/stores.
180    InstSeqNum producing_store;
181    if (inst->isLoad() && loadBarrier) {
182        DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
183                loadBarrierSN);
184        producing_store = loadBarrierSN;
185    } else if (inst->isStore() && storeBarrier) {
186        DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
187                storeBarrierSN);
188        producing_store = storeBarrierSN;
189    } else {
190        producing_store = depPred.checkInst(inst->instAddr());
191    }
192
193    MemDepEntryPtr store_entry = NULL;
194
195    // If there is a producing store, try to find the entry.
196    if (producing_store != 0) {
197        DPRINTF(MemDepUnit, "Searching for producer\n");
198        MemDepHashIt hash_it = memDepHash.find(producing_store);
199
200        if (hash_it != memDepHash.end()) {
201            store_entry = (*hash_it).second;
202            DPRINTF(MemDepUnit, "Proucer found\n");
203        }
204    }
205
206    // If no store entry, then instruction can issue as soon as the registers
207    // are ready.
208    if (!store_entry) {
209        DPRINTF(MemDepUnit, "No dependency for inst PC "
210                "%s [sn:%lli].\n", inst->pcState(), inst->seqNum);
211
212        inst_entry->memDepReady = true;
213
214        if (inst->readyToIssue()) {
215            inst_entry->regsReady = true;
216
217            moveToReady(inst_entry);
218        }
219    } else {
220        // Otherwise make the instruction dependent on the store/barrier.
221        DPRINTF(MemDepUnit, "Adding to dependency list; "
222                "inst PC %s is dependent on [sn:%lli].\n",
223                inst->pcState(), producing_store);
224
225        if (inst->readyToIssue()) {
226            inst_entry->regsReady = true;
227        }
228
229        // Clear the bit saying this instruction can issue.
230        inst->clearCanIssue();
231
232        // Add this instruction to the list of dependents.
233        store_entry->dependInsts.push_back(inst_entry);
234
235        if (inst->isLoad()) {
236            ++conflictingLoads;
237        } else {
238            ++conflictingStores;
239        }
240    }
241
242    if (inst->isStore()) {
243        DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
244                inst->pcState(), inst->seqNum);
245
246        depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
247
248        ++insertedStores;
249    } else if (inst->isLoad()) {
250        ++insertedLoads;
251    } else {
252        panic("Unknown type! (most likely a barrier).");
253    }
254}
255
256template <class MemDepPred, class Impl>
257void
258MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
259{
260    ThreadID tid = inst->threadNumber;
261
262    MemDepEntryPtr inst_entry = std::make_shared<MemDepEntry>(inst);
263
264    // Insert the MemDepEntry into the hash.
265    memDepHash.insert(
266        std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
267#ifdef DEBUG
268    MemDepEntry::memdep_insert++;
269#endif
270
271    // Add the instruction to the list.
272    instList[tid].push_back(inst);
273
274    inst_entry->listIt = --(instList[tid].end());
275
276    // Might want to turn this part into an inline function or something.
277    // It's shared between both insert functions.
278    if (inst->isStore()) {
279        DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n",
280                inst->pcState(), inst->seqNum);
281
282        depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
283
284        ++insertedStores;
285    } else if (inst->isLoad()) {
286        ++insertedLoads;
287    } else {
288        panic("Unknown type! (most likely a barrier).");
289    }
290}
291
292template <class MemDepPred, class Impl>
293void
294MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
295{
296    InstSeqNum barr_sn = barr_inst->seqNum;
297    // Memory barriers block loads and stores, write barriers only stores.
298    if (barr_inst->isMemBarrier()) {
299        loadBarrier = true;
300        loadBarrierSN = barr_sn;
301        storeBarrier = true;
302        storeBarrierSN = barr_sn;
303        DPRINTF(MemDepUnit, "Inserted a memory barrier %s SN:%lli\n",
304                barr_inst->pcState(),barr_sn);
305    } else if (barr_inst->isWriteBarrier()) {
306        storeBarrier = true;
307        storeBarrierSN = barr_sn;
308        DPRINTF(MemDepUnit, "Inserted a write barrier\n");
309    }
310
311    ThreadID tid = barr_inst->threadNumber;
312
313    MemDepEntryPtr inst_entry = std::make_shared<MemDepEntry>(barr_inst);
314
315    // Add the MemDepEntry to the hash.
316    memDepHash.insert(
317        std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
318#ifdef DEBUG
319    MemDepEntry::memdep_insert++;
320#endif
321
322    // Add the instruction to the instruction list.
323    instList[tid].push_back(barr_inst);
324
325    inst_entry->listIt = --(instList[tid].end());
326}
327
328template <class MemDepPred, class Impl>
329void
330MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
331{
332    DPRINTF(MemDepUnit, "Marking registers as ready for "
333            "instruction PC %s [sn:%lli].\n",
334            inst->pcState(), inst->seqNum);
335
336    MemDepEntryPtr inst_entry = findInHash(inst);
337
338    inst_entry->regsReady = true;
339
340    if (inst_entry->memDepReady) {
341        DPRINTF(MemDepUnit, "Instruction has its memory "
342                "dependencies resolved, adding it to the ready list.\n");
343
344        moveToReady(inst_entry);
345    } else {
346        DPRINTF(MemDepUnit, "Instruction still waiting on "
347                "memory dependency.\n");
348    }
349}
350
351template <class MemDepPred, class Impl>
352void
353MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
354{
355    DPRINTF(MemDepUnit, "Marking non speculative "
356            "instruction PC %s as ready [sn:%lli].\n",
357            inst->pcState(), inst->seqNum);
358
359    MemDepEntryPtr inst_entry = findInHash(inst);
360
361    moveToReady(inst_entry);
362}
363
364template <class MemDepPred, class Impl>
365void
366MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
367{
368    instsToReplay.push_back(inst);
369}
370
371template <class MemDepPred, class Impl>
372void
373MemDepUnit<MemDepPred, Impl>::replay()
374{
375    DynInstPtr temp_inst;
376
377    // For now this replay function replays all waiting memory ops.
378    while (!instsToReplay.empty()) {
379        temp_inst = instsToReplay.front();
380
381        MemDepEntryPtr inst_entry = findInHash(temp_inst);
382
383        DPRINTF(MemDepUnit, "Replaying mem instruction PC %s [sn:%lli].\n",
384                temp_inst->pcState(), temp_inst->seqNum);
385
386        moveToReady(inst_entry);
387
388        instsToReplay.pop_front();
389    }
390}
391
392template <class MemDepPred, class Impl>
393void
394MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
395{
396    DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n",
397            inst->pcState(), inst->seqNum);
398
399    ThreadID tid = inst->threadNumber;
400
401    // Remove the instruction from the hash and the list.
402    MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
403
404    assert(hash_it != memDepHash.end());
405
406    instList[tid].erase((*hash_it).second->listIt);
407
408    (*hash_it).second = NULL;
409
410    memDepHash.erase(hash_it);
411#ifdef DEBUG
412    MemDepEntry::memdep_erase++;
413#endif
414}
415
416template <class MemDepPred, class Impl>
417void
418MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
419{
420    wakeDependents(inst);
421    completed(inst);
422
423    InstSeqNum barr_sn = inst->seqNum;
424    DPRINTF(MemDepUnit, "barrier completed: %s SN:%lli\n", inst->pcState(),
425            inst->seqNum);
426    if (inst->isMemBarrier()) {
427        if (loadBarrierSN == barr_sn)
428            loadBarrier = false;
429        if (storeBarrierSN == barr_sn)
430            storeBarrier = false;
431    } else if (inst->isWriteBarrier()) {
432        if (storeBarrierSN == barr_sn)
433            storeBarrier = false;
434    }
435}
436
437template <class MemDepPred, class Impl>
438void
439MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
440{
441    // Only stores and barriers have dependents.
442    if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
443        return;
444    }
445
446    MemDepEntryPtr inst_entry = findInHash(inst);
447
448    for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
449        MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
450
451        if (!woken_inst->inst) {
452            // Potentially removed mem dep entries could be on this list
453            continue;
454        }
455
456        DPRINTF(MemDepUnit, "Waking up a dependent inst, "
457                "[sn:%lli].\n",
458                woken_inst->inst->seqNum);
459
460        if (woken_inst->regsReady && !woken_inst->squashed) {
461            moveToReady(woken_inst);
462        } else {
463            woken_inst->memDepReady = true;
464        }
465    }
466
467    inst_entry->dependInsts.clear();
468}
469
470template <class MemDepPred, class Impl>
471void
472MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
473                                     ThreadID tid)
474{
475    if (!instsToReplay.empty()) {
476        ListIt replay_it = instsToReplay.begin();
477        while (replay_it != instsToReplay.end()) {
478            if ((*replay_it)->threadNumber == tid &&
479                (*replay_it)->seqNum > squashed_num) {
480                instsToReplay.erase(replay_it++);
481            } else {
482                ++replay_it;
483            }
484        }
485    }
486
487    ListIt squash_it = instList[tid].end();
488    --squash_it;
489
490    MemDepHashIt hash_it;
491
492    while (!instList[tid].empty() &&
493           (*squash_it)->seqNum > squashed_num) {
494
495        DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
496                (*squash_it)->seqNum);
497
498        if ((*squash_it)->seqNum == loadBarrierSN)
499              loadBarrier = false;
500
501        if ((*squash_it)->seqNum == storeBarrierSN)
502              storeBarrier = false;
503
504        hash_it = memDepHash.find((*squash_it)->seqNum);
505
506        assert(hash_it != memDepHash.end());
507
508        (*hash_it).second->squashed = true;
509
510        (*hash_it).second = NULL;
511
512        memDepHash.erase(hash_it);
513#ifdef DEBUG
514        MemDepEntry::memdep_erase++;
515#endif
516
517        instList[tid].erase(squash_it--);
518    }
519
520    // Tell the dependency predictor to squash as well.
521    depPred.squash(squashed_num, tid);
522}
523
524template <class MemDepPred, class Impl>
525void
526MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
527                                        DynInstPtr &violating_load)
528{
529    DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
530            " load: %#x, store: %#x\n", violating_load->instAddr(),
531            store_inst->instAddr());
532    // Tell the memory dependence unit of the violation.
533    depPred.violation(store_inst->instAddr(), violating_load->instAddr());
534}
535
536template <class MemDepPred, class Impl>
537void
538MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
539{
540    DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
541            inst->instAddr(), inst->seqNum);
542
543    depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore());
544}
545
546template <class MemDepPred, class Impl>
547inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
548MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
549{
550    MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
551
552    assert(hash_it != memDepHash.end());
553
554    return (*hash_it).second;
555}
556
557template <class MemDepPred, class Impl>
558inline void
559MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
560{
561    DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
562            "to the ready list.\n", woken_inst_entry->inst->seqNum);
563
564    assert(!woken_inst_entry->squashed);
565
566    iqPtr->addReadyMemInst(woken_inst_entry->inst);
567}
568
569
570template <class MemDepPred, class Impl>
571void
572MemDepUnit<MemDepPred, Impl>::dumpLists()
573{
574    for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
575        cprintf("Instruction list %i size: %i\n",
576                tid, instList[tid].size());
577
578        ListIt inst_list_it = instList[tid].begin();
579        int num = 0;
580
581        while (inst_list_it != instList[tid].end()) {
582            cprintf("Instruction:%i\nPC: %s\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
583                    "Squashed:%i\n\n",
584                    num, (*inst_list_it)->pcState(),
585                    (*inst_list_it)->seqNum,
586                    (*inst_list_it)->threadNumber,
587                    (*inst_list_it)->isIssued(),
588                    (*inst_list_it)->isSquashed());
589            inst_list_it++;
590            ++num;
591        }
592    }
593
594    cprintf("Memory dependence hash size: %i\n", memDepHash.size());
595
596#ifdef DEBUG
597    cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
598#endif
599}
600
601#endif//__CPU_O3_MEM_DEP_UNIT_IMPL_HH__
602