mem_dep_unit_impl.hh revision 9444
11689SN/A/* 29444SAndreas.Sandberg@ARM.com * Copyright (c) 2012 ARM Limited 39444SAndreas.Sandberg@ARM.com * All rights reserved 49444SAndreas.Sandberg@ARM.com * 59444SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69444SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79444SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89444SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99444SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109444SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119444SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129444SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139444SAndreas.Sandberg@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421061SN/A 431061SN/A#include <map> 441061SN/A 452292SN/A#include "cpu/o3/inst_queue.hh" 461717SN/A#include "cpu/o3/mem_dep_unit.hh" 478232Snate@binkert.org#include "debug/MemDepUnit.hh" 485529Snate@binkert.org#include "params/DerivO3CPU.hh" 495529Snate@binkert.org 501061SN/Atemplate <class MemDepPred, class Impl> 513500Sktlim@umich.eduMemDepUnit<MemDepPred, Impl>::MemDepUnit() 523500Sktlim@umich.edu : loadBarrier(false), loadBarrierSN(0), storeBarrier(false), 533500Sktlim@umich.edu storeBarrierSN(0), iqPtr(NULL) 543500Sktlim@umich.edu{ 553500Sktlim@umich.edu} 563500Sktlim@umich.edu 573500Sktlim@umich.edutemplate <class MemDepPred, class Impl> 585529Snate@binkert.orgMemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params) 596005Snate@binkert.org : _name(params->name + ".memdepunit"), 608519SAli.Saidi@ARM.com depPred(params->store_set_clear_period, params->SSITSize, 618519SAli.Saidi@ARM.com params->LFSTSize), 628519SAli.Saidi@ARM.com loadBarrier(false), loadBarrierSN(0), storeBarrier(false), 638519SAli.Saidi@ARM.com storeBarrierSN(0), iqPtr(NULL) 641061SN/A{ 652292SN/A DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n"); 662292SN/A} 672292SN/A 682292SN/Atemplate <class MemDepPred, class Impl> 692292SN/AMemDepUnit<MemDepPred, Impl>::~MemDepUnit() 702292SN/A{ 716221Snate@binkert.org for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 722292SN/A 732292SN/A ListIt inst_list_it = instList[tid].begin(); 742292SN/A 752292SN/A MemDepHashIt hash_it; 762292SN/A 772292SN/A while (!instList[tid].empty()) { 782292SN/A hash_it = memDepHash.find((*inst_list_it)->seqNum); 792292SN/A 802292SN/A assert(hash_it != memDepHash.end()); 812292SN/A 822292SN/A memDepHash.erase(hash_it); 832292SN/A 842292SN/A instList[tid].erase(inst_list_it++); 852292SN/A } 862292SN/A } 872292SN/A 882678Sktlim@umich.edu#ifdef DEBUG 892292SN/A assert(MemDepEntry::memdep_count == 0); 902678Sktlim@umich.edu#endif 912292SN/A} 922292SN/A 932292SN/Atemplate <class MemDepPred, class Impl> 942292SN/Avoid 956221Snate@binkert.orgMemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, ThreadID tid) 962292SN/A{ 972292SN/A DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid); 982292SN/A 996005Snate@binkert.org _name = csprintf("%s.memDep%d", params->name, tid); 1002292SN/A id = tid; 1012292SN/A 1028519SAli.Saidi@ARM.com depPred.init(params->store_set_clear_period, params->SSITSize, 1038519SAli.Saidi@ARM.com params->LFSTSize); 1041061SN/A} 1051061SN/A 1061061SN/Atemplate <class MemDepPred, class Impl> 1071061SN/Avoid 1081062SN/AMemDepUnit<MemDepPred, Impl>::regStats() 1091062SN/A{ 1101062SN/A insertedLoads 1116005Snate@binkert.org .name(name() + ".insertedLoads") 1121062SN/A .desc("Number of loads inserted to the mem dependence unit."); 1131062SN/A 1141062SN/A insertedStores 1156005Snate@binkert.org .name(name() + ".insertedStores") 1161062SN/A .desc("Number of stores inserted to the mem dependence unit."); 1171062SN/A 1181062SN/A conflictingLoads 1196005Snate@binkert.org .name(name() + ".conflictingLoads") 1201062SN/A .desc("Number of conflicting loads."); 1211062SN/A 1221062SN/A conflictingStores 1236005Snate@binkert.org .name(name() + ".conflictingStores") 1241062SN/A .desc("Number of conflicting stores."); 1251062SN/A} 1261062SN/A 1271062SN/Atemplate <class MemDepPred, class Impl> 1281062SN/Avoid 1299444SAndreas.Sandberg@ARM.comMemDepUnit<MemDepPred, Impl>::drainSanityCheck() const 1302307SN/A{ 1312367SN/A assert(instsToReplay.empty()); 1322367SN/A assert(memDepHash.empty()); 1339444SAndreas.Sandberg@ARM.com for (int i = 0; i < Impl::MaxThreads; ++i) 1349444SAndreas.Sandberg@ARM.com assert(instList[i].empty()); 1359444SAndreas.Sandberg@ARM.com assert(instsToReplay.empty()); 1369444SAndreas.Sandberg@ARM.com assert(memDepHash.empty()); 1372307SN/A} 1382307SN/A 1392307SN/Atemplate <class MemDepPred, class Impl> 1402307SN/Avoid 1412307SN/AMemDepUnit<MemDepPred, Impl>::takeOverFrom() 1422307SN/A{ 1432348SN/A // Be sure to reset all state. 1442307SN/A loadBarrier = storeBarrier = false; 1452307SN/A loadBarrierSN = storeBarrierSN = 0; 1462307SN/A depPred.clear(); 1472307SN/A} 1482307SN/A 1492307SN/Atemplate <class MemDepPred, class Impl> 1502307SN/Avoid 1512292SN/AMemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr) 1522292SN/A{ 1532292SN/A iqPtr = iq_ptr; 1542292SN/A} 1552292SN/A 1562292SN/Atemplate <class MemDepPred, class Impl> 1572292SN/Avoid 1581061SN/AMemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst) 1591061SN/A{ 1606221Snate@binkert.org ThreadID tid = inst->threadNumber; 1611061SN/A 1622292SN/A MemDepEntryPtr inst_entry = new MemDepEntry(inst); 1631061SN/A 1642292SN/A // Add the MemDepEntry to the hash. 1652292SN/A memDepHash.insert( 1662292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 1672678Sktlim@umich.edu#ifdef DEBUG 1682292SN/A MemDepEntry::memdep_insert++; 1692678Sktlim@umich.edu#endif 1701061SN/A 1712292SN/A instList[tid].push_back(inst); 1721062SN/A 1732292SN/A inst_entry->listIt = --(instList[tid].end()); 1741062SN/A 1752329SN/A // Check any barriers and the dependence predictor for any 1762348SN/A // producing memrefs/stores. 1772292SN/A InstSeqNum producing_store; 1782292SN/A if (inst->isLoad() && loadBarrier) { 1793500Sktlim@umich.edu DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n", 1803500Sktlim@umich.edu loadBarrierSN); 1812292SN/A producing_store = loadBarrierSN; 1822292SN/A } else if (inst->isStore() && storeBarrier) { 1833500Sktlim@umich.edu DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n", 1843500Sktlim@umich.edu storeBarrierSN); 1852292SN/A producing_store = storeBarrierSN; 1862292SN/A } else { 1877720Sgblack@eecs.umich.edu producing_store = depPred.checkInst(inst->instAddr()); 1882292SN/A } 1892292SN/A 1902292SN/A MemDepEntryPtr store_entry = NULL; 1912292SN/A 1922292SN/A // If there is a producing store, try to find the entry. 1932292SN/A if (producing_store != 0) { 1943500Sktlim@umich.edu DPRINTF(MemDepUnit, "Searching for producer\n"); 1952292SN/A MemDepHashIt hash_it = memDepHash.find(producing_store); 1962292SN/A 1972292SN/A if (hash_it != memDepHash.end()) { 1982292SN/A store_entry = (*hash_it).second; 1993500Sktlim@umich.edu DPRINTF(MemDepUnit, "Proucer found\n"); 2002292SN/A } 2012292SN/A } 2022292SN/A 2032292SN/A // If no store entry, then instruction can issue as soon as the registers 2042292SN/A // are ready. 2052292SN/A if (!store_entry) { 2062292SN/A DPRINTF(MemDepUnit, "No dependency for inst PC " 2077720Sgblack@eecs.umich.edu "%s [sn:%lli].\n", inst->pcState(), inst->seqNum); 2082292SN/A 2092292SN/A inst_entry->memDepReady = true; 2101062SN/A 2111062SN/A if (inst->readyToIssue()) { 2122292SN/A inst_entry->regsReady = true; 2131062SN/A 2142292SN/A moveToReady(inst_entry); 2151062SN/A } 2161061SN/A } else { 2172329SN/A // Otherwise make the instruction dependent on the store/barrier. 2182292SN/A DPRINTF(MemDepUnit, "Adding to dependency list; " 2197720Sgblack@eecs.umich.edu "inst PC %s is dependent on [sn:%lli].\n", 2207720Sgblack@eecs.umich.edu inst->pcState(), producing_store); 2211062SN/A 2221062SN/A if (inst->readyToIssue()) { 2232292SN/A inst_entry->regsReady = true; 2241062SN/A } 2251062SN/A 2264033Sktlim@umich.edu // Clear the bit saying this instruction can issue. 2274033Sktlim@umich.edu inst->clearCanIssue(); 2284033Sktlim@umich.edu 2291062SN/A // Add this instruction to the list of dependents. 2302292SN/A store_entry->dependInsts.push_back(inst_entry); 2311062SN/A 2321062SN/A if (inst->isLoad()) { 2331062SN/A ++conflictingLoads; 2341062SN/A } else { 2351062SN/A ++conflictingStores; 2361062SN/A } 2371061SN/A } 2381061SN/A 2391061SN/A if (inst->isStore()) { 2407720Sgblack@eecs.umich.edu DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n", 2417720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 2421062SN/A 2437720Sgblack@eecs.umich.edu depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber); 2441062SN/A 2451062SN/A ++insertedStores; 2461062SN/A } else if (inst->isLoad()) { 2471062SN/A ++insertedLoads; 2481062SN/A } else { 2492292SN/A panic("Unknown type! (most likely a barrier)."); 2501061SN/A } 2511062SN/A} 2521062SN/A 2531062SN/Atemplate <class MemDepPred, class Impl> 2541062SN/Avoid 2551062SN/AMemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst) 2561062SN/A{ 2576221Snate@binkert.org ThreadID tid = inst->threadNumber; 2581062SN/A 2592292SN/A MemDepEntryPtr inst_entry = new MemDepEntry(inst); 2601062SN/A 2612292SN/A // Insert the MemDepEntry into the hash. 2622292SN/A memDepHash.insert( 2632292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 2642678Sktlim@umich.edu#ifdef DEBUG 2652292SN/A MemDepEntry::memdep_insert++; 2662678Sktlim@umich.edu#endif 2671062SN/A 2682292SN/A // Add the instruction to the list. 2692292SN/A instList[tid].push_back(inst); 2702292SN/A 2712292SN/A inst_entry->listIt = --(instList[tid].end()); 2721062SN/A 2731062SN/A // Might want to turn this part into an inline function or something. 2741062SN/A // It's shared between both insert functions. 2751062SN/A if (inst->isStore()) { 2767720Sgblack@eecs.umich.edu DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n", 2777720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 2781062SN/A 2797720Sgblack@eecs.umich.edu depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber); 2801062SN/A 2811062SN/A ++insertedStores; 2821062SN/A } else if (inst->isLoad()) { 2831062SN/A ++insertedLoads; 2841062SN/A } else { 2852292SN/A panic("Unknown type! (most likely a barrier)."); 2861062SN/A } 2871062SN/A} 2881062SN/A 2891062SN/Atemplate <class MemDepPred, class Impl> 2901062SN/Avoid 2912292SN/AMemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst) 2921062SN/A{ 2932292SN/A InstSeqNum barr_sn = barr_inst->seqNum; 2942348SN/A // Memory barriers block loads and stores, write barriers only stores. 2952292SN/A if (barr_inst->isMemBarrier()) { 2962292SN/A loadBarrier = true; 2972292SN/A loadBarrierSN = barr_sn; 2982292SN/A storeBarrier = true; 2992292SN/A storeBarrierSN = barr_sn; 3008516SMrinmoy.Ghosh@arm.com DPRINTF(MemDepUnit, "Inserted a memory barrier %s SN:%lli\n", 3018516SMrinmoy.Ghosh@arm.com barr_inst->pcState(),barr_sn); 3022292SN/A } else if (barr_inst->isWriteBarrier()) { 3032292SN/A storeBarrier = true; 3042292SN/A storeBarrierSN = barr_sn; 3052292SN/A DPRINTF(MemDepUnit, "Inserted a write barrier\n"); 3062292SN/A } 3071062SN/A 3086221Snate@binkert.org ThreadID tid = barr_inst->threadNumber; 3091062SN/A 3102292SN/A MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst); 3111062SN/A 3122292SN/A // Add the MemDepEntry to the hash. 3132292SN/A memDepHash.insert( 3142292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry)); 3152678Sktlim@umich.edu#ifdef DEBUG 3162292SN/A MemDepEntry::memdep_insert++; 3172678Sktlim@umich.edu#endif 3181062SN/A 3192292SN/A // Add the instruction to the instruction list. 3202292SN/A instList[tid].push_back(barr_inst); 3212292SN/A 3222292SN/A inst_entry->listIt = --(instList[tid].end()); 3231062SN/A} 3241062SN/A 3251062SN/Atemplate <class MemDepPred, class Impl> 3261062SN/Avoid 3271062SN/AMemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst) 3281062SN/A{ 3292292SN/A DPRINTF(MemDepUnit, "Marking registers as ready for " 3307720Sgblack@eecs.umich.edu "instruction PC %s [sn:%lli].\n", 3317720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 3321062SN/A 3332292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 3341062SN/A 3352292SN/A inst_entry->regsReady = true; 3361062SN/A 3372292SN/A if (inst_entry->memDepReady) { 3382292SN/A DPRINTF(MemDepUnit, "Instruction has its memory " 3391062SN/A "dependencies resolved, adding it to the ready list.\n"); 3401062SN/A 3412292SN/A moveToReady(inst_entry); 3421062SN/A } else { 3432292SN/A DPRINTF(MemDepUnit, "Instruction still waiting on " 3441062SN/A "memory dependency.\n"); 3451062SN/A } 3461061SN/A} 3471061SN/A 3481061SN/Atemplate <class MemDepPred, class Impl> 3491062SN/Avoid 3501062SN/AMemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst) 3511061SN/A{ 3522292SN/A DPRINTF(MemDepUnit, "Marking non speculative " 3537720Sgblack@eecs.umich.edu "instruction PC %s as ready [sn:%lli].\n", 3547720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 3551062SN/A 3562292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 3571061SN/A 3582292SN/A moveToReady(inst_entry); 3591061SN/A} 3601061SN/A 3611061SN/Atemplate <class MemDepPred, class Impl> 3621061SN/Avoid 3632292SN/AMemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst) 3641061SN/A{ 3652292SN/A instsToReplay.push_back(inst); 3662292SN/A} 3671061SN/A 3682292SN/Atemplate <class MemDepPred, class Impl> 3692292SN/Avoid 3702292SN/AMemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst) 3712292SN/A{ 3722292SN/A DynInstPtr temp_inst; 3731062SN/A 3742348SN/A // For now this replay function replays all waiting memory ops. 3752292SN/A while (!instsToReplay.empty()) { 3762292SN/A temp_inst = instsToReplay.front(); 3771062SN/A 3782292SN/A MemDepEntryPtr inst_entry = findInHash(temp_inst); 3792292SN/A 3807720Sgblack@eecs.umich.edu DPRINTF(MemDepUnit, "Replaying mem instruction PC %s [sn:%lli].\n", 3817720Sgblack@eecs.umich.edu temp_inst->pcState(), temp_inst->seqNum); 3822292SN/A 3832292SN/A moveToReady(inst_entry); 3842292SN/A 3852292SN/A instsToReplay.pop_front(); 3862292SN/A } 3872292SN/A} 3882292SN/A 3892292SN/Atemplate <class MemDepPred, class Impl> 3902292SN/Avoid 3912292SN/AMemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst) 3922292SN/A{ 3937720Sgblack@eecs.umich.edu DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n", 3947720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 3952292SN/A 3966221Snate@binkert.org ThreadID tid = inst->threadNumber; 3972292SN/A 3982292SN/A // Remove the instruction from the hash and the list. 3992292SN/A MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 4002292SN/A 4012292SN/A assert(hash_it != memDepHash.end()); 4022292SN/A 4032292SN/A instList[tid].erase((*hash_it).second->listIt); 4042292SN/A 4052292SN/A (*hash_it).second = NULL; 4062292SN/A 4072292SN/A memDepHash.erase(hash_it); 4082678Sktlim@umich.edu#ifdef DEBUG 4092292SN/A MemDepEntry::memdep_erase++; 4102678Sktlim@umich.edu#endif 4112292SN/A} 4122292SN/A 4132292SN/Atemplate <class MemDepPred, class Impl> 4142292SN/Avoid 4152292SN/AMemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst) 4162292SN/A{ 4172292SN/A wakeDependents(inst); 4182292SN/A completed(inst); 4192292SN/A 4202292SN/A InstSeqNum barr_sn = inst->seqNum; 4218515SMrinmoy.Ghosh@arm.com DPRINTF(MemDepUnit, "barrier completed: %s SN:%lli\n", inst->pcState(), 4228515SMrinmoy.Ghosh@arm.com inst->seqNum); 4232292SN/A if (inst->isMemBarrier()) { 4242292SN/A if (loadBarrierSN == barr_sn) 4252292SN/A loadBarrier = false; 4262292SN/A if (storeBarrierSN == barr_sn) 4272292SN/A storeBarrier = false; 4282292SN/A } else if (inst->isWriteBarrier()) { 4292292SN/A if (storeBarrierSN == barr_sn) 4302292SN/A storeBarrier = false; 4312292SN/A } 4321061SN/A} 4331061SN/A 4341061SN/Atemplate <class MemDepPred, class Impl> 4351061SN/Avoid 4361061SN/AMemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst) 4371061SN/A{ 4382292SN/A // Only stores and barriers have dependents. 4392292SN/A if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) { 4401062SN/A return; 4411062SN/A } 4421062SN/A 4432292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 4441061SN/A 4452292SN/A for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) { 4462292SN/A MemDepEntryPtr woken_inst = inst_entry->dependInsts[i]; 4471062SN/A 4482292SN/A if (!woken_inst->inst) { 4492292SN/A // Potentially removed mem dep entries could be on this list 4502292SN/A continue; 4512292SN/A } 4521061SN/A 4532292SN/A DPRINTF(MemDepUnit, "Waking up a dependent inst, " 4542292SN/A "[sn:%lli].\n", 4552292SN/A woken_inst->inst->seqNum); 4561061SN/A 4572292SN/A if (woken_inst->regsReady && !woken_inst->squashed) { 4581062SN/A moveToReady(woken_inst); 4591062SN/A } else { 4602292SN/A woken_inst->memDepReady = true; 4611062SN/A } 4621061SN/A } 4631061SN/A 4642292SN/A inst_entry->dependInsts.clear(); 4651061SN/A} 4661061SN/A 4671061SN/Atemplate <class MemDepPred, class Impl> 4681061SN/Avoid 4692292SN/AMemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num, 4706221Snate@binkert.org ThreadID tid) 4711061SN/A{ 4722292SN/A if (!instsToReplay.empty()) { 4732292SN/A ListIt replay_it = instsToReplay.begin(); 4742292SN/A while (replay_it != instsToReplay.end()) { 4752292SN/A if ((*replay_it)->threadNumber == tid && 4762292SN/A (*replay_it)->seqNum > squashed_num) { 4772292SN/A instsToReplay.erase(replay_it++); 4782292SN/A } else { 4792292SN/A ++replay_it; 4801062SN/A } 4811061SN/A } 4821061SN/A } 4831061SN/A 4842292SN/A ListIt squash_it = instList[tid].end(); 4852292SN/A --squash_it; 4861061SN/A 4872292SN/A MemDepHashIt hash_it; 4881061SN/A 4892292SN/A while (!instList[tid].empty() && 4902292SN/A (*squash_it)->seqNum > squashed_num) { 4911061SN/A 4922292SN/A DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n", 4932292SN/A (*squash_it)->seqNum); 4941061SN/A 4958515SMrinmoy.Ghosh@arm.com if ((*squash_it)->seqNum == loadBarrierSN) 4968515SMrinmoy.Ghosh@arm.com loadBarrier = false; 4978515SMrinmoy.Ghosh@arm.com 4988515SMrinmoy.Ghosh@arm.com if ((*squash_it)->seqNum == storeBarrierSN) 4998515SMrinmoy.Ghosh@arm.com storeBarrier = false; 5008515SMrinmoy.Ghosh@arm.com 5012292SN/A hash_it = memDepHash.find((*squash_it)->seqNum); 5021061SN/A 5032292SN/A assert(hash_it != memDepHash.end()); 5041062SN/A 5052292SN/A (*hash_it).second->squashed = true; 5061717SN/A 5072292SN/A (*hash_it).second = NULL; 5081717SN/A 5092292SN/A memDepHash.erase(hash_it); 5102678Sktlim@umich.edu#ifdef DEBUG 5112292SN/A MemDepEntry::memdep_erase++; 5122678Sktlim@umich.edu#endif 5131717SN/A 5142292SN/A instList[tid].erase(squash_it--); 5151061SN/A } 5161061SN/A 5171061SN/A // Tell the dependency predictor to squash as well. 5182292SN/A depPred.squash(squashed_num, tid); 5191061SN/A} 5201061SN/A 5211061SN/Atemplate <class MemDepPred, class Impl> 5221061SN/Avoid 5231061SN/AMemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst, 5241061SN/A DynInstPtr &violating_load) 5251061SN/A{ 5262292SN/A DPRINTF(MemDepUnit, "Passing violating PCs to store sets," 5277720Sgblack@eecs.umich.edu " load: %#x, store: %#x\n", violating_load->instAddr(), 5287720Sgblack@eecs.umich.edu store_inst->instAddr()); 5291061SN/A // Tell the memory dependence unit of the violation. 5308515SMrinmoy.Ghosh@arm.com depPred.violation(store_inst->instAddr(), violating_load->instAddr()); 5311061SN/A} 5321062SN/A 5331062SN/Atemplate <class MemDepPred, class Impl> 5342292SN/Avoid 5352292SN/AMemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst) 5362292SN/A{ 5372292SN/A DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n", 5387720Sgblack@eecs.umich.edu inst->instAddr(), inst->seqNum); 5392292SN/A 5407720Sgblack@eecs.umich.edu depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore()); 5412292SN/A} 5422292SN/A 5432292SN/Atemplate <class MemDepPred, class Impl> 5442292SN/Ainline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr & 5452292SN/AMemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst) 5462292SN/A{ 5472292SN/A MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 5482292SN/A 5492292SN/A assert(hash_it != memDepHash.end()); 5502292SN/A 5512292SN/A return (*hash_it).second; 5522292SN/A} 5532292SN/A 5542292SN/Atemplate <class MemDepPred, class Impl> 5551062SN/Ainline void 5562292SN/AMemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry) 5571062SN/A{ 5582292SN/A DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] " 5592292SN/A "to the ready list.\n", woken_inst_entry->inst->seqNum); 5601062SN/A 5612292SN/A assert(!woken_inst_entry->squashed); 5621062SN/A 5632292SN/A iqPtr->addReadyMemInst(woken_inst_entry->inst); 5641062SN/A} 5652292SN/A 5662292SN/A 5672292SN/Atemplate <class MemDepPred, class Impl> 5682292SN/Avoid 5692292SN/AMemDepUnit<MemDepPred, Impl>::dumpLists() 5702292SN/A{ 5716221Snate@binkert.org for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 5722292SN/A cprintf("Instruction list %i size: %i\n", 5732292SN/A tid, instList[tid].size()); 5742292SN/A 5752292SN/A ListIt inst_list_it = instList[tid].begin(); 5762292SN/A int num = 0; 5772292SN/A 5782292SN/A while (inst_list_it != instList[tid].end()) { 5797720Sgblack@eecs.umich.edu cprintf("Instruction:%i\nPC: %s\n[sn:%i]\n[tid:%i]\nIssued:%i\n" 5802292SN/A "Squashed:%i\n\n", 5817720Sgblack@eecs.umich.edu num, (*inst_list_it)->pcState(), 5822292SN/A (*inst_list_it)->seqNum, 5832292SN/A (*inst_list_it)->threadNumber, 5842292SN/A (*inst_list_it)->isIssued(), 5852292SN/A (*inst_list_it)->isSquashed()); 5862292SN/A inst_list_it++; 5872292SN/A ++num; 5882292SN/A } 5892292SN/A } 5902292SN/A 5912292SN/A cprintf("Memory dependence hash size: %i\n", memDepHash.size()); 5922292SN/A 5932678Sktlim@umich.edu#ifdef DEBUG 5942292SN/A cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count); 5952678Sktlim@umich.edu#endif 5962292SN/A} 597