mem_dep_unit_impl.hh revision 8232
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301061SN/A 311061SN/A#include <map> 321061SN/A 332292SN/A#include "cpu/o3/inst_queue.hh" 341717SN/A#include "cpu/o3/mem_dep_unit.hh" 358232Snate@binkert.org#include "debug/MemDepUnit.hh" 365529Snate@binkert.org#include "params/DerivO3CPU.hh" 375529Snate@binkert.org 381061SN/Atemplate <class MemDepPred, class Impl> 393500Sktlim@umich.eduMemDepUnit<MemDepPred, Impl>::MemDepUnit() 403500Sktlim@umich.edu : loadBarrier(false), loadBarrierSN(0), storeBarrier(false), 413500Sktlim@umich.edu storeBarrierSN(0), iqPtr(NULL) 423500Sktlim@umich.edu{ 433500Sktlim@umich.edu} 443500Sktlim@umich.edu 453500Sktlim@umich.edutemplate <class MemDepPred, class Impl> 465529Snate@binkert.orgMemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params) 476005Snate@binkert.org : _name(params->name + ".memdepunit"), 486005Snate@binkert.org depPred(params->SSITSize, params->LFSTSize), loadBarrier(false), 492292SN/A loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL) 501061SN/A{ 512292SN/A DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n"); 522292SN/A} 532292SN/A 542292SN/Atemplate <class MemDepPred, class Impl> 552292SN/AMemDepUnit<MemDepPred, Impl>::~MemDepUnit() 562292SN/A{ 576221Snate@binkert.org for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 582292SN/A 592292SN/A ListIt inst_list_it = instList[tid].begin(); 602292SN/A 612292SN/A MemDepHashIt hash_it; 622292SN/A 632292SN/A while (!instList[tid].empty()) { 642292SN/A hash_it = memDepHash.find((*inst_list_it)->seqNum); 652292SN/A 662292SN/A assert(hash_it != memDepHash.end()); 672292SN/A 682292SN/A memDepHash.erase(hash_it); 692292SN/A 702292SN/A instList[tid].erase(inst_list_it++); 712292SN/A } 722292SN/A } 732292SN/A 742678Sktlim@umich.edu#ifdef DEBUG 752292SN/A assert(MemDepEntry::memdep_count == 0); 762678Sktlim@umich.edu#endif 772292SN/A} 782292SN/A 792292SN/Atemplate <class MemDepPred, class Impl> 802292SN/Avoid 816221Snate@binkert.orgMemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, ThreadID tid) 822292SN/A{ 832292SN/A DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid); 842292SN/A 856005Snate@binkert.org _name = csprintf("%s.memDep%d", params->name, tid); 862292SN/A id = tid; 872292SN/A 882292SN/A depPred.init(params->SSITSize, params->LFSTSize); 891061SN/A} 901061SN/A 911061SN/Atemplate <class MemDepPred, class Impl> 921061SN/Avoid 931062SN/AMemDepUnit<MemDepPred, Impl>::regStats() 941062SN/A{ 951062SN/A insertedLoads 966005Snate@binkert.org .name(name() + ".insertedLoads") 971062SN/A .desc("Number of loads inserted to the mem dependence unit."); 981062SN/A 991062SN/A insertedStores 1006005Snate@binkert.org .name(name() + ".insertedStores") 1011062SN/A .desc("Number of stores inserted to the mem dependence unit."); 1021062SN/A 1031062SN/A conflictingLoads 1046005Snate@binkert.org .name(name() + ".conflictingLoads") 1051062SN/A .desc("Number of conflicting loads."); 1061062SN/A 1071062SN/A conflictingStores 1086005Snate@binkert.org .name(name() + ".conflictingStores") 1091062SN/A .desc("Number of conflicting stores."); 1101062SN/A} 1111062SN/A 1121062SN/Atemplate <class MemDepPred, class Impl> 1131062SN/Avoid 1142307SN/AMemDepUnit<MemDepPred, Impl>::switchOut() 1152307SN/A{ 1162367SN/A assert(instList[0].empty()); 1172367SN/A assert(instsToReplay.empty()); 1182367SN/A assert(memDepHash.empty()); 1192348SN/A // Clear any state. 1202307SN/A for (int i = 0; i < Impl::MaxThreads; ++i) { 1212307SN/A instList[i].clear(); 1222307SN/A } 1232307SN/A instsToReplay.clear(); 1242307SN/A memDepHash.clear(); 1252307SN/A} 1262307SN/A 1272307SN/Atemplate <class MemDepPred, class Impl> 1282307SN/Avoid 1292307SN/AMemDepUnit<MemDepPred, Impl>::takeOverFrom() 1302307SN/A{ 1312348SN/A // Be sure to reset all state. 1322307SN/A loadBarrier = storeBarrier = false; 1332307SN/A loadBarrierSN = storeBarrierSN = 0; 1342307SN/A depPred.clear(); 1352307SN/A} 1362307SN/A 1372307SN/Atemplate <class MemDepPred, class Impl> 1382307SN/Avoid 1392292SN/AMemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr) 1402292SN/A{ 1412292SN/A iqPtr = iq_ptr; 1422292SN/A} 1432292SN/A 1442292SN/Atemplate <class MemDepPred, class Impl> 1452292SN/Avoid 1461061SN/AMemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst) 1471061SN/A{ 1486221Snate@binkert.org ThreadID tid = inst->threadNumber; 1491061SN/A 1502292SN/A MemDepEntryPtr inst_entry = new MemDepEntry(inst); 1511061SN/A 1522292SN/A // Add the MemDepEntry to the hash. 1532292SN/A memDepHash.insert( 1542292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 1552678Sktlim@umich.edu#ifdef DEBUG 1562292SN/A MemDepEntry::memdep_insert++; 1572678Sktlim@umich.edu#endif 1581061SN/A 1592292SN/A instList[tid].push_back(inst); 1601062SN/A 1612292SN/A inst_entry->listIt = --(instList[tid].end()); 1621062SN/A 1632329SN/A // Check any barriers and the dependence predictor for any 1642348SN/A // producing memrefs/stores. 1652292SN/A InstSeqNum producing_store; 1662292SN/A if (inst->isLoad() && loadBarrier) { 1673500Sktlim@umich.edu DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n", 1683500Sktlim@umich.edu loadBarrierSN); 1692292SN/A producing_store = loadBarrierSN; 1702292SN/A } else if (inst->isStore() && storeBarrier) { 1713500Sktlim@umich.edu DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n", 1723500Sktlim@umich.edu storeBarrierSN); 1732292SN/A producing_store = storeBarrierSN; 1742292SN/A } else { 1757720Sgblack@eecs.umich.edu producing_store = depPred.checkInst(inst->instAddr()); 1762292SN/A } 1772292SN/A 1782292SN/A MemDepEntryPtr store_entry = NULL; 1792292SN/A 1802292SN/A // If there is a producing store, try to find the entry. 1812292SN/A if (producing_store != 0) { 1823500Sktlim@umich.edu DPRINTF(MemDepUnit, "Searching for producer\n"); 1832292SN/A MemDepHashIt hash_it = memDepHash.find(producing_store); 1842292SN/A 1852292SN/A if (hash_it != memDepHash.end()) { 1862292SN/A store_entry = (*hash_it).second; 1873500Sktlim@umich.edu DPRINTF(MemDepUnit, "Proucer found\n"); 1882292SN/A } 1892292SN/A } 1902292SN/A 1912292SN/A // If no store entry, then instruction can issue as soon as the registers 1922292SN/A // are ready. 1932292SN/A if (!store_entry) { 1942292SN/A DPRINTF(MemDepUnit, "No dependency for inst PC " 1957720Sgblack@eecs.umich.edu "%s [sn:%lli].\n", inst->pcState(), inst->seqNum); 1962292SN/A 1972292SN/A inst_entry->memDepReady = true; 1981062SN/A 1991062SN/A if (inst->readyToIssue()) { 2002292SN/A inst_entry->regsReady = true; 2011062SN/A 2022292SN/A moveToReady(inst_entry); 2031062SN/A } 2041061SN/A } else { 2052329SN/A // Otherwise make the instruction dependent on the store/barrier. 2062292SN/A DPRINTF(MemDepUnit, "Adding to dependency list; " 2077720Sgblack@eecs.umich.edu "inst PC %s is dependent on [sn:%lli].\n", 2087720Sgblack@eecs.umich.edu inst->pcState(), producing_store); 2091062SN/A 2101062SN/A if (inst->readyToIssue()) { 2112292SN/A inst_entry->regsReady = true; 2121062SN/A } 2131062SN/A 2144033Sktlim@umich.edu // Clear the bit saying this instruction can issue. 2154033Sktlim@umich.edu inst->clearCanIssue(); 2164033Sktlim@umich.edu 2171062SN/A // Add this instruction to the list of dependents. 2182292SN/A store_entry->dependInsts.push_back(inst_entry); 2191062SN/A 2201062SN/A if (inst->isLoad()) { 2211062SN/A ++conflictingLoads; 2221062SN/A } else { 2231062SN/A ++conflictingStores; 2241062SN/A } 2251061SN/A } 2261061SN/A 2271061SN/A if (inst->isStore()) { 2287720Sgblack@eecs.umich.edu DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n", 2297720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 2301062SN/A 2317720Sgblack@eecs.umich.edu depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber); 2321062SN/A 2331062SN/A ++insertedStores; 2341062SN/A } else if (inst->isLoad()) { 2351062SN/A ++insertedLoads; 2361062SN/A } else { 2372292SN/A panic("Unknown type! (most likely a barrier)."); 2381061SN/A } 2391062SN/A} 2401062SN/A 2411062SN/Atemplate <class MemDepPred, class Impl> 2421062SN/Avoid 2431062SN/AMemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst) 2441062SN/A{ 2456221Snate@binkert.org ThreadID tid = inst->threadNumber; 2461062SN/A 2472292SN/A MemDepEntryPtr inst_entry = new MemDepEntry(inst); 2481062SN/A 2492292SN/A // Insert the MemDepEntry into the hash. 2502292SN/A memDepHash.insert( 2512292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 2522678Sktlim@umich.edu#ifdef DEBUG 2532292SN/A MemDepEntry::memdep_insert++; 2542678Sktlim@umich.edu#endif 2551062SN/A 2562292SN/A // Add the instruction to the list. 2572292SN/A instList[tid].push_back(inst); 2582292SN/A 2592292SN/A inst_entry->listIt = --(instList[tid].end()); 2601062SN/A 2611062SN/A // Might want to turn this part into an inline function or something. 2621062SN/A // It's shared between both insert functions. 2631062SN/A if (inst->isStore()) { 2647720Sgblack@eecs.umich.edu DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n", 2657720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 2661062SN/A 2677720Sgblack@eecs.umich.edu depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber); 2681062SN/A 2691062SN/A ++insertedStores; 2701062SN/A } else if (inst->isLoad()) { 2711062SN/A ++insertedLoads; 2721062SN/A } else { 2732292SN/A panic("Unknown type! (most likely a barrier)."); 2741062SN/A } 2751062SN/A} 2761062SN/A 2771062SN/Atemplate <class MemDepPred, class Impl> 2781062SN/Avoid 2792292SN/AMemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst) 2801062SN/A{ 2812292SN/A InstSeqNum barr_sn = barr_inst->seqNum; 2822348SN/A // Memory barriers block loads and stores, write barriers only stores. 2832292SN/A if (barr_inst->isMemBarrier()) { 2842292SN/A loadBarrier = true; 2852292SN/A loadBarrierSN = barr_sn; 2862292SN/A storeBarrier = true; 2872292SN/A storeBarrierSN = barr_sn; 2882292SN/A DPRINTF(MemDepUnit, "Inserted a memory barrier\n"); 2892292SN/A } else if (barr_inst->isWriteBarrier()) { 2902292SN/A storeBarrier = true; 2912292SN/A storeBarrierSN = barr_sn; 2922292SN/A DPRINTF(MemDepUnit, "Inserted a write barrier\n"); 2932292SN/A } 2941062SN/A 2956221Snate@binkert.org ThreadID tid = barr_inst->threadNumber; 2961062SN/A 2972292SN/A MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst); 2981062SN/A 2992292SN/A // Add the MemDepEntry to the hash. 3002292SN/A memDepHash.insert( 3012292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry)); 3022678Sktlim@umich.edu#ifdef DEBUG 3032292SN/A MemDepEntry::memdep_insert++; 3042678Sktlim@umich.edu#endif 3051062SN/A 3062292SN/A // Add the instruction to the instruction list. 3072292SN/A instList[tid].push_back(barr_inst); 3082292SN/A 3092292SN/A inst_entry->listIt = --(instList[tid].end()); 3101062SN/A} 3111062SN/A 3121062SN/Atemplate <class MemDepPred, class Impl> 3131062SN/Avoid 3141062SN/AMemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst) 3151062SN/A{ 3162292SN/A DPRINTF(MemDepUnit, "Marking registers as ready for " 3177720Sgblack@eecs.umich.edu "instruction PC %s [sn:%lli].\n", 3187720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 3191062SN/A 3202292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 3211062SN/A 3222292SN/A inst_entry->regsReady = true; 3231062SN/A 3242292SN/A if (inst_entry->memDepReady) { 3252292SN/A DPRINTF(MemDepUnit, "Instruction has its memory " 3261062SN/A "dependencies resolved, adding it to the ready list.\n"); 3271062SN/A 3282292SN/A moveToReady(inst_entry); 3291062SN/A } else { 3302292SN/A DPRINTF(MemDepUnit, "Instruction still waiting on " 3311062SN/A "memory dependency.\n"); 3321062SN/A } 3331061SN/A} 3341061SN/A 3351061SN/Atemplate <class MemDepPred, class Impl> 3361062SN/Avoid 3371062SN/AMemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst) 3381061SN/A{ 3392292SN/A DPRINTF(MemDepUnit, "Marking non speculative " 3407720Sgblack@eecs.umich.edu "instruction PC %s as ready [sn:%lli].\n", 3417720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 3421062SN/A 3432292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 3441061SN/A 3452292SN/A moveToReady(inst_entry); 3461061SN/A} 3471061SN/A 3481061SN/Atemplate <class MemDepPred, class Impl> 3491061SN/Avoid 3502292SN/AMemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst) 3511061SN/A{ 3522292SN/A instsToReplay.push_back(inst); 3532292SN/A} 3541061SN/A 3552292SN/Atemplate <class MemDepPred, class Impl> 3562292SN/Avoid 3572292SN/AMemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst) 3582292SN/A{ 3592292SN/A DynInstPtr temp_inst; 3601062SN/A 3612348SN/A // For now this replay function replays all waiting memory ops. 3622292SN/A while (!instsToReplay.empty()) { 3632292SN/A temp_inst = instsToReplay.front(); 3641062SN/A 3652292SN/A MemDepEntryPtr inst_entry = findInHash(temp_inst); 3662292SN/A 3677720Sgblack@eecs.umich.edu DPRINTF(MemDepUnit, "Replaying mem instruction PC %s [sn:%lli].\n", 3687720Sgblack@eecs.umich.edu temp_inst->pcState(), temp_inst->seqNum); 3692292SN/A 3702292SN/A moveToReady(inst_entry); 3712292SN/A 3722292SN/A instsToReplay.pop_front(); 3732292SN/A } 3742292SN/A} 3752292SN/A 3762292SN/Atemplate <class MemDepPred, class Impl> 3772292SN/Avoid 3782292SN/AMemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst) 3792292SN/A{ 3807720Sgblack@eecs.umich.edu DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n", 3817720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 3822292SN/A 3836221Snate@binkert.org ThreadID tid = inst->threadNumber; 3842292SN/A 3852292SN/A // Remove the instruction from the hash and the list. 3862292SN/A MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 3872292SN/A 3882292SN/A assert(hash_it != memDepHash.end()); 3892292SN/A 3902292SN/A instList[tid].erase((*hash_it).second->listIt); 3912292SN/A 3922292SN/A (*hash_it).second = NULL; 3932292SN/A 3942292SN/A memDepHash.erase(hash_it); 3952678Sktlim@umich.edu#ifdef DEBUG 3962292SN/A MemDepEntry::memdep_erase++; 3972678Sktlim@umich.edu#endif 3982292SN/A} 3992292SN/A 4002292SN/Atemplate <class MemDepPred, class Impl> 4012292SN/Avoid 4022292SN/AMemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst) 4032292SN/A{ 4042292SN/A wakeDependents(inst); 4052292SN/A completed(inst); 4062292SN/A 4072292SN/A InstSeqNum barr_sn = inst->seqNum; 4082292SN/A 4092292SN/A if (inst->isMemBarrier()) { 4102292SN/A assert(loadBarrier && storeBarrier); 4112292SN/A if (loadBarrierSN == barr_sn) 4122292SN/A loadBarrier = false; 4132292SN/A if (storeBarrierSN == barr_sn) 4142292SN/A storeBarrier = false; 4152292SN/A } else if (inst->isWriteBarrier()) { 4162292SN/A assert(storeBarrier); 4172292SN/A if (storeBarrierSN == barr_sn) 4182292SN/A storeBarrier = false; 4192292SN/A } 4201061SN/A} 4211061SN/A 4221061SN/Atemplate <class MemDepPred, class Impl> 4231061SN/Avoid 4241061SN/AMemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst) 4251061SN/A{ 4262292SN/A // Only stores and barriers have dependents. 4272292SN/A if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) { 4281062SN/A return; 4291062SN/A } 4301062SN/A 4312292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 4321061SN/A 4332292SN/A for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) { 4342292SN/A MemDepEntryPtr woken_inst = inst_entry->dependInsts[i]; 4351062SN/A 4362292SN/A if (!woken_inst->inst) { 4372292SN/A // Potentially removed mem dep entries could be on this list 4382292SN/A continue; 4392292SN/A } 4401061SN/A 4412292SN/A DPRINTF(MemDepUnit, "Waking up a dependent inst, " 4422292SN/A "[sn:%lli].\n", 4432292SN/A woken_inst->inst->seqNum); 4441061SN/A 4452292SN/A if (woken_inst->regsReady && !woken_inst->squashed) { 4461062SN/A moveToReady(woken_inst); 4471062SN/A } else { 4482292SN/A woken_inst->memDepReady = true; 4491062SN/A } 4501061SN/A } 4511061SN/A 4522292SN/A inst_entry->dependInsts.clear(); 4531061SN/A} 4541061SN/A 4551061SN/Atemplate <class MemDepPred, class Impl> 4561061SN/Avoid 4572292SN/AMemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num, 4586221Snate@binkert.org ThreadID tid) 4591061SN/A{ 4602292SN/A if (!instsToReplay.empty()) { 4612292SN/A ListIt replay_it = instsToReplay.begin(); 4622292SN/A while (replay_it != instsToReplay.end()) { 4632292SN/A if ((*replay_it)->threadNumber == tid && 4642292SN/A (*replay_it)->seqNum > squashed_num) { 4652292SN/A instsToReplay.erase(replay_it++); 4662292SN/A } else { 4672292SN/A ++replay_it; 4681062SN/A } 4691061SN/A } 4701061SN/A } 4711061SN/A 4722292SN/A ListIt squash_it = instList[tid].end(); 4732292SN/A --squash_it; 4741061SN/A 4752292SN/A MemDepHashIt hash_it; 4761061SN/A 4772292SN/A while (!instList[tid].empty() && 4782292SN/A (*squash_it)->seqNum > squashed_num) { 4791061SN/A 4802292SN/A DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n", 4812292SN/A (*squash_it)->seqNum); 4821061SN/A 4832292SN/A hash_it = memDepHash.find((*squash_it)->seqNum); 4841061SN/A 4852292SN/A assert(hash_it != memDepHash.end()); 4861062SN/A 4872292SN/A (*hash_it).second->squashed = true; 4881717SN/A 4892292SN/A (*hash_it).second = NULL; 4901717SN/A 4912292SN/A memDepHash.erase(hash_it); 4922678Sktlim@umich.edu#ifdef DEBUG 4932292SN/A MemDepEntry::memdep_erase++; 4942678Sktlim@umich.edu#endif 4951717SN/A 4962292SN/A instList[tid].erase(squash_it--); 4971061SN/A } 4981061SN/A 4991061SN/A // Tell the dependency predictor to squash as well. 5002292SN/A depPred.squash(squashed_num, tid); 5011061SN/A} 5021061SN/A 5031061SN/Atemplate <class MemDepPred, class Impl> 5041061SN/Avoid 5051061SN/AMemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst, 5061061SN/A DynInstPtr &violating_load) 5071061SN/A{ 5082292SN/A DPRINTF(MemDepUnit, "Passing violating PCs to store sets," 5097720Sgblack@eecs.umich.edu " load: %#x, store: %#x\n", violating_load->instAddr(), 5107720Sgblack@eecs.umich.edu store_inst->instAddr()); 5111061SN/A // Tell the memory dependence unit of the violation. 5127720Sgblack@eecs.umich.edu depPred.violation(violating_load->instAddr(), store_inst->instAddr()); 5131061SN/A} 5141062SN/A 5151062SN/Atemplate <class MemDepPred, class Impl> 5162292SN/Avoid 5172292SN/AMemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst) 5182292SN/A{ 5192292SN/A DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n", 5207720Sgblack@eecs.umich.edu inst->instAddr(), inst->seqNum); 5212292SN/A 5227720Sgblack@eecs.umich.edu depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore()); 5232292SN/A} 5242292SN/A 5252292SN/Atemplate <class MemDepPred, class Impl> 5262292SN/Ainline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr & 5272292SN/AMemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst) 5282292SN/A{ 5292292SN/A MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 5302292SN/A 5312292SN/A assert(hash_it != memDepHash.end()); 5322292SN/A 5332292SN/A return (*hash_it).second; 5342292SN/A} 5352292SN/A 5362292SN/Atemplate <class MemDepPred, class Impl> 5371062SN/Ainline void 5382292SN/AMemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry) 5391062SN/A{ 5402292SN/A DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] " 5412292SN/A "to the ready list.\n", woken_inst_entry->inst->seqNum); 5421062SN/A 5432292SN/A assert(!woken_inst_entry->squashed); 5441062SN/A 5452292SN/A iqPtr->addReadyMemInst(woken_inst_entry->inst); 5461062SN/A} 5472292SN/A 5482292SN/A 5492292SN/Atemplate <class MemDepPred, class Impl> 5502292SN/Avoid 5512292SN/AMemDepUnit<MemDepPred, Impl>::dumpLists() 5522292SN/A{ 5536221Snate@binkert.org for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 5542292SN/A cprintf("Instruction list %i size: %i\n", 5552292SN/A tid, instList[tid].size()); 5562292SN/A 5572292SN/A ListIt inst_list_it = instList[tid].begin(); 5582292SN/A int num = 0; 5592292SN/A 5602292SN/A while (inst_list_it != instList[tid].end()) { 5617720Sgblack@eecs.umich.edu cprintf("Instruction:%i\nPC: %s\n[sn:%i]\n[tid:%i]\nIssued:%i\n" 5622292SN/A "Squashed:%i\n\n", 5637720Sgblack@eecs.umich.edu num, (*inst_list_it)->pcState(), 5642292SN/A (*inst_list_it)->seqNum, 5652292SN/A (*inst_list_it)->threadNumber, 5662292SN/A (*inst_list_it)->isIssued(), 5672292SN/A (*inst_list_it)->isSquashed()); 5682292SN/A inst_list_it++; 5692292SN/A ++num; 5702292SN/A } 5712292SN/A } 5722292SN/A 5732292SN/A cprintf("Memory dependence hash size: %i\n", memDepHash.size()); 5742292SN/A 5752678Sktlim@umich.edu#ifdef DEBUG 5762292SN/A cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count); 5772678Sktlim@umich.edu#endif 5782292SN/A} 579