mem_dep_unit_impl.hh revision 7720
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301061SN/A 311061SN/A#include <map> 321061SN/A 332292SN/A#include "cpu/o3/inst_queue.hh" 341717SN/A#include "cpu/o3/mem_dep_unit.hh" 355529Snate@binkert.org#include "params/DerivO3CPU.hh" 365529Snate@binkert.org 371061SN/Atemplate <class MemDepPred, class Impl> 383500Sktlim@umich.eduMemDepUnit<MemDepPred, Impl>::MemDepUnit() 393500Sktlim@umich.edu : loadBarrier(false), loadBarrierSN(0), storeBarrier(false), 403500Sktlim@umich.edu storeBarrierSN(0), iqPtr(NULL) 413500Sktlim@umich.edu{ 423500Sktlim@umich.edu} 433500Sktlim@umich.edu 443500Sktlim@umich.edutemplate <class MemDepPred, class Impl> 455529Snate@binkert.orgMemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params) 466005Snate@binkert.org : _name(params->name + ".memdepunit"), 476005Snate@binkert.org depPred(params->SSITSize, params->LFSTSize), loadBarrier(false), 482292SN/A loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL) 491061SN/A{ 502292SN/A DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n"); 512292SN/A} 522292SN/A 532292SN/Atemplate <class MemDepPred, class Impl> 542292SN/AMemDepUnit<MemDepPred, Impl>::~MemDepUnit() 552292SN/A{ 566221Snate@binkert.org for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 572292SN/A 582292SN/A ListIt inst_list_it = instList[tid].begin(); 592292SN/A 602292SN/A MemDepHashIt hash_it; 612292SN/A 622292SN/A while (!instList[tid].empty()) { 632292SN/A hash_it = memDepHash.find((*inst_list_it)->seqNum); 642292SN/A 652292SN/A assert(hash_it != memDepHash.end()); 662292SN/A 672292SN/A memDepHash.erase(hash_it); 682292SN/A 692292SN/A instList[tid].erase(inst_list_it++); 702292SN/A } 712292SN/A } 722292SN/A 732678Sktlim@umich.edu#ifdef DEBUG 742292SN/A assert(MemDepEntry::memdep_count == 0); 752678Sktlim@umich.edu#endif 762292SN/A} 772292SN/A 782292SN/Atemplate <class MemDepPred, class Impl> 792292SN/Avoid 806221Snate@binkert.orgMemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, ThreadID tid) 812292SN/A{ 822292SN/A DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid); 832292SN/A 846005Snate@binkert.org _name = csprintf("%s.memDep%d", params->name, tid); 852292SN/A id = tid; 862292SN/A 872292SN/A depPred.init(params->SSITSize, params->LFSTSize); 881061SN/A} 891061SN/A 901061SN/Atemplate <class MemDepPred, class Impl> 911061SN/Avoid 921062SN/AMemDepUnit<MemDepPred, Impl>::regStats() 931062SN/A{ 941062SN/A insertedLoads 956005Snate@binkert.org .name(name() + ".insertedLoads") 961062SN/A .desc("Number of loads inserted to the mem dependence unit."); 971062SN/A 981062SN/A insertedStores 996005Snate@binkert.org .name(name() + ".insertedStores") 1001062SN/A .desc("Number of stores inserted to the mem dependence unit."); 1011062SN/A 1021062SN/A conflictingLoads 1036005Snate@binkert.org .name(name() + ".conflictingLoads") 1041062SN/A .desc("Number of conflicting loads."); 1051062SN/A 1061062SN/A conflictingStores 1076005Snate@binkert.org .name(name() + ".conflictingStores") 1081062SN/A .desc("Number of conflicting stores."); 1091062SN/A} 1101062SN/A 1111062SN/Atemplate <class MemDepPred, class Impl> 1121062SN/Avoid 1132307SN/AMemDepUnit<MemDepPred, Impl>::switchOut() 1142307SN/A{ 1152367SN/A assert(instList[0].empty()); 1162367SN/A assert(instsToReplay.empty()); 1172367SN/A assert(memDepHash.empty()); 1182348SN/A // Clear any state. 1192307SN/A for (int i = 0; i < Impl::MaxThreads; ++i) { 1202307SN/A instList[i].clear(); 1212307SN/A } 1222307SN/A instsToReplay.clear(); 1232307SN/A memDepHash.clear(); 1242307SN/A} 1252307SN/A 1262307SN/Atemplate <class MemDepPred, class Impl> 1272307SN/Avoid 1282307SN/AMemDepUnit<MemDepPred, Impl>::takeOverFrom() 1292307SN/A{ 1302348SN/A // Be sure to reset all state. 1312307SN/A loadBarrier = storeBarrier = false; 1322307SN/A loadBarrierSN = storeBarrierSN = 0; 1332307SN/A depPred.clear(); 1342307SN/A} 1352307SN/A 1362307SN/Atemplate <class MemDepPred, class Impl> 1372307SN/Avoid 1382292SN/AMemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr) 1392292SN/A{ 1402292SN/A iqPtr = iq_ptr; 1412292SN/A} 1422292SN/A 1432292SN/Atemplate <class MemDepPred, class Impl> 1442292SN/Avoid 1451061SN/AMemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst) 1461061SN/A{ 1476221Snate@binkert.org ThreadID tid = inst->threadNumber; 1481061SN/A 1492292SN/A MemDepEntryPtr inst_entry = new MemDepEntry(inst); 1501061SN/A 1512292SN/A // Add the MemDepEntry to the hash. 1522292SN/A memDepHash.insert( 1532292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 1542678Sktlim@umich.edu#ifdef DEBUG 1552292SN/A MemDepEntry::memdep_insert++; 1562678Sktlim@umich.edu#endif 1571061SN/A 1582292SN/A instList[tid].push_back(inst); 1591062SN/A 1602292SN/A inst_entry->listIt = --(instList[tid].end()); 1611062SN/A 1622329SN/A // Check any barriers and the dependence predictor for any 1632348SN/A // producing memrefs/stores. 1642292SN/A InstSeqNum producing_store; 1652292SN/A if (inst->isLoad() && loadBarrier) { 1663500Sktlim@umich.edu DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n", 1673500Sktlim@umich.edu loadBarrierSN); 1682292SN/A producing_store = loadBarrierSN; 1692292SN/A } else if (inst->isStore() && storeBarrier) { 1703500Sktlim@umich.edu DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n", 1713500Sktlim@umich.edu storeBarrierSN); 1722292SN/A producing_store = storeBarrierSN; 1732292SN/A } else { 1747720Sgblack@eecs.umich.edu producing_store = depPred.checkInst(inst->instAddr()); 1752292SN/A } 1762292SN/A 1772292SN/A MemDepEntryPtr store_entry = NULL; 1782292SN/A 1792292SN/A // If there is a producing store, try to find the entry. 1802292SN/A if (producing_store != 0) { 1813500Sktlim@umich.edu DPRINTF(MemDepUnit, "Searching for producer\n"); 1822292SN/A MemDepHashIt hash_it = memDepHash.find(producing_store); 1832292SN/A 1842292SN/A if (hash_it != memDepHash.end()) { 1852292SN/A store_entry = (*hash_it).second; 1863500Sktlim@umich.edu DPRINTF(MemDepUnit, "Proucer found\n"); 1872292SN/A } 1882292SN/A } 1892292SN/A 1902292SN/A // If no store entry, then instruction can issue as soon as the registers 1912292SN/A // are ready. 1922292SN/A if (!store_entry) { 1932292SN/A DPRINTF(MemDepUnit, "No dependency for inst PC " 1947720Sgblack@eecs.umich.edu "%s [sn:%lli].\n", inst->pcState(), inst->seqNum); 1952292SN/A 1962292SN/A inst_entry->memDepReady = true; 1971062SN/A 1981062SN/A if (inst->readyToIssue()) { 1992292SN/A inst_entry->regsReady = true; 2001062SN/A 2012292SN/A moveToReady(inst_entry); 2021062SN/A } 2031061SN/A } else { 2042329SN/A // Otherwise make the instruction dependent on the store/barrier. 2052292SN/A DPRINTF(MemDepUnit, "Adding to dependency list; " 2067720Sgblack@eecs.umich.edu "inst PC %s is dependent on [sn:%lli].\n", 2077720Sgblack@eecs.umich.edu inst->pcState(), producing_store); 2081062SN/A 2091062SN/A if (inst->readyToIssue()) { 2102292SN/A inst_entry->regsReady = true; 2111062SN/A } 2121062SN/A 2134033Sktlim@umich.edu // Clear the bit saying this instruction can issue. 2144033Sktlim@umich.edu inst->clearCanIssue(); 2154033Sktlim@umich.edu 2161062SN/A // Add this instruction to the list of dependents. 2172292SN/A store_entry->dependInsts.push_back(inst_entry); 2181062SN/A 2191062SN/A if (inst->isLoad()) { 2201062SN/A ++conflictingLoads; 2211062SN/A } else { 2221062SN/A ++conflictingStores; 2231062SN/A } 2241061SN/A } 2251061SN/A 2261061SN/A if (inst->isStore()) { 2277720Sgblack@eecs.umich.edu DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n", 2287720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 2291062SN/A 2307720Sgblack@eecs.umich.edu depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber); 2311062SN/A 2321062SN/A ++insertedStores; 2331062SN/A } else if (inst->isLoad()) { 2341062SN/A ++insertedLoads; 2351062SN/A } else { 2362292SN/A panic("Unknown type! (most likely a barrier)."); 2371061SN/A } 2381062SN/A} 2391062SN/A 2401062SN/Atemplate <class MemDepPred, class Impl> 2411062SN/Avoid 2421062SN/AMemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst) 2431062SN/A{ 2446221Snate@binkert.org ThreadID tid = inst->threadNumber; 2451062SN/A 2462292SN/A MemDepEntryPtr inst_entry = new MemDepEntry(inst); 2471062SN/A 2482292SN/A // Insert the MemDepEntry into the hash. 2492292SN/A memDepHash.insert( 2502292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 2512678Sktlim@umich.edu#ifdef DEBUG 2522292SN/A MemDepEntry::memdep_insert++; 2532678Sktlim@umich.edu#endif 2541062SN/A 2552292SN/A // Add the instruction to the list. 2562292SN/A instList[tid].push_back(inst); 2572292SN/A 2582292SN/A inst_entry->listIt = --(instList[tid].end()); 2591062SN/A 2601062SN/A // Might want to turn this part into an inline function or something. 2611062SN/A // It's shared between both insert functions. 2621062SN/A if (inst->isStore()) { 2637720Sgblack@eecs.umich.edu DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n", 2647720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 2651062SN/A 2667720Sgblack@eecs.umich.edu depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber); 2671062SN/A 2681062SN/A ++insertedStores; 2691062SN/A } else if (inst->isLoad()) { 2701062SN/A ++insertedLoads; 2711062SN/A } else { 2722292SN/A panic("Unknown type! (most likely a barrier)."); 2731062SN/A } 2741062SN/A} 2751062SN/A 2761062SN/Atemplate <class MemDepPred, class Impl> 2771062SN/Avoid 2782292SN/AMemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst) 2791062SN/A{ 2802292SN/A InstSeqNum barr_sn = barr_inst->seqNum; 2812348SN/A // Memory barriers block loads and stores, write barriers only stores. 2822292SN/A if (barr_inst->isMemBarrier()) { 2832292SN/A loadBarrier = true; 2842292SN/A loadBarrierSN = barr_sn; 2852292SN/A storeBarrier = true; 2862292SN/A storeBarrierSN = barr_sn; 2872292SN/A DPRINTF(MemDepUnit, "Inserted a memory barrier\n"); 2882292SN/A } else if (barr_inst->isWriteBarrier()) { 2892292SN/A storeBarrier = true; 2902292SN/A storeBarrierSN = barr_sn; 2912292SN/A DPRINTF(MemDepUnit, "Inserted a write barrier\n"); 2922292SN/A } 2931062SN/A 2946221Snate@binkert.org ThreadID tid = barr_inst->threadNumber; 2951062SN/A 2962292SN/A MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst); 2971062SN/A 2982292SN/A // Add the MemDepEntry to the hash. 2992292SN/A memDepHash.insert( 3002292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry)); 3012678Sktlim@umich.edu#ifdef DEBUG 3022292SN/A MemDepEntry::memdep_insert++; 3032678Sktlim@umich.edu#endif 3041062SN/A 3052292SN/A // Add the instruction to the instruction list. 3062292SN/A instList[tid].push_back(barr_inst); 3072292SN/A 3082292SN/A inst_entry->listIt = --(instList[tid].end()); 3091062SN/A} 3101062SN/A 3111062SN/Atemplate <class MemDepPred, class Impl> 3121062SN/Avoid 3131062SN/AMemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst) 3141062SN/A{ 3152292SN/A DPRINTF(MemDepUnit, "Marking registers as ready for " 3167720Sgblack@eecs.umich.edu "instruction PC %s [sn:%lli].\n", 3177720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 3181062SN/A 3192292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 3201062SN/A 3212292SN/A inst_entry->regsReady = true; 3221062SN/A 3232292SN/A if (inst_entry->memDepReady) { 3242292SN/A DPRINTF(MemDepUnit, "Instruction has its memory " 3251062SN/A "dependencies resolved, adding it to the ready list.\n"); 3261062SN/A 3272292SN/A moveToReady(inst_entry); 3281062SN/A } else { 3292292SN/A DPRINTF(MemDepUnit, "Instruction still waiting on " 3301062SN/A "memory dependency.\n"); 3311062SN/A } 3321061SN/A} 3331061SN/A 3341061SN/Atemplate <class MemDepPred, class Impl> 3351062SN/Avoid 3361062SN/AMemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst) 3371061SN/A{ 3382292SN/A DPRINTF(MemDepUnit, "Marking non speculative " 3397720Sgblack@eecs.umich.edu "instruction PC %s as ready [sn:%lli].\n", 3407720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 3411062SN/A 3422292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 3431061SN/A 3442292SN/A moveToReady(inst_entry); 3451061SN/A} 3461061SN/A 3471061SN/Atemplate <class MemDepPred, class Impl> 3481061SN/Avoid 3492292SN/AMemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst) 3501061SN/A{ 3512292SN/A instsToReplay.push_back(inst); 3522292SN/A} 3531061SN/A 3542292SN/Atemplate <class MemDepPred, class Impl> 3552292SN/Avoid 3562292SN/AMemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst) 3572292SN/A{ 3582292SN/A DynInstPtr temp_inst; 3591062SN/A 3602348SN/A // For now this replay function replays all waiting memory ops. 3612292SN/A while (!instsToReplay.empty()) { 3622292SN/A temp_inst = instsToReplay.front(); 3631062SN/A 3642292SN/A MemDepEntryPtr inst_entry = findInHash(temp_inst); 3652292SN/A 3667720Sgblack@eecs.umich.edu DPRINTF(MemDepUnit, "Replaying mem instruction PC %s [sn:%lli].\n", 3677720Sgblack@eecs.umich.edu temp_inst->pcState(), temp_inst->seqNum); 3682292SN/A 3692292SN/A moveToReady(inst_entry); 3702292SN/A 3712292SN/A instsToReplay.pop_front(); 3722292SN/A } 3732292SN/A} 3742292SN/A 3752292SN/Atemplate <class MemDepPred, class Impl> 3762292SN/Avoid 3772292SN/AMemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst) 3782292SN/A{ 3797720Sgblack@eecs.umich.edu DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n", 3807720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 3812292SN/A 3826221Snate@binkert.org ThreadID tid = inst->threadNumber; 3832292SN/A 3842292SN/A // Remove the instruction from the hash and the list. 3852292SN/A MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 3862292SN/A 3872292SN/A assert(hash_it != memDepHash.end()); 3882292SN/A 3892292SN/A instList[tid].erase((*hash_it).second->listIt); 3902292SN/A 3912292SN/A (*hash_it).second = NULL; 3922292SN/A 3932292SN/A memDepHash.erase(hash_it); 3942678Sktlim@umich.edu#ifdef DEBUG 3952292SN/A MemDepEntry::memdep_erase++; 3962678Sktlim@umich.edu#endif 3972292SN/A} 3982292SN/A 3992292SN/Atemplate <class MemDepPred, class Impl> 4002292SN/Avoid 4012292SN/AMemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst) 4022292SN/A{ 4032292SN/A wakeDependents(inst); 4042292SN/A completed(inst); 4052292SN/A 4062292SN/A InstSeqNum barr_sn = inst->seqNum; 4072292SN/A 4082292SN/A if (inst->isMemBarrier()) { 4092292SN/A assert(loadBarrier && storeBarrier); 4102292SN/A if (loadBarrierSN == barr_sn) 4112292SN/A loadBarrier = false; 4122292SN/A if (storeBarrierSN == barr_sn) 4132292SN/A storeBarrier = false; 4142292SN/A } else if (inst->isWriteBarrier()) { 4152292SN/A assert(storeBarrier); 4162292SN/A if (storeBarrierSN == barr_sn) 4172292SN/A storeBarrier = false; 4182292SN/A } 4191061SN/A} 4201061SN/A 4211061SN/Atemplate <class MemDepPred, class Impl> 4221061SN/Avoid 4231061SN/AMemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst) 4241061SN/A{ 4252292SN/A // Only stores and barriers have dependents. 4262292SN/A if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) { 4271062SN/A return; 4281062SN/A } 4291062SN/A 4302292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 4311061SN/A 4322292SN/A for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) { 4332292SN/A MemDepEntryPtr woken_inst = inst_entry->dependInsts[i]; 4341062SN/A 4352292SN/A if (!woken_inst->inst) { 4362292SN/A // Potentially removed mem dep entries could be on this list 4372292SN/A continue; 4382292SN/A } 4391061SN/A 4402292SN/A DPRINTF(MemDepUnit, "Waking up a dependent inst, " 4412292SN/A "[sn:%lli].\n", 4422292SN/A woken_inst->inst->seqNum); 4431061SN/A 4442292SN/A if (woken_inst->regsReady && !woken_inst->squashed) { 4451062SN/A moveToReady(woken_inst); 4461062SN/A } else { 4472292SN/A woken_inst->memDepReady = true; 4481062SN/A } 4491061SN/A } 4501061SN/A 4512292SN/A inst_entry->dependInsts.clear(); 4521061SN/A} 4531061SN/A 4541061SN/Atemplate <class MemDepPred, class Impl> 4551061SN/Avoid 4562292SN/AMemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num, 4576221Snate@binkert.org ThreadID tid) 4581061SN/A{ 4592292SN/A if (!instsToReplay.empty()) { 4602292SN/A ListIt replay_it = instsToReplay.begin(); 4612292SN/A while (replay_it != instsToReplay.end()) { 4622292SN/A if ((*replay_it)->threadNumber == tid && 4632292SN/A (*replay_it)->seqNum > squashed_num) { 4642292SN/A instsToReplay.erase(replay_it++); 4652292SN/A } else { 4662292SN/A ++replay_it; 4671062SN/A } 4681061SN/A } 4691061SN/A } 4701061SN/A 4712292SN/A ListIt squash_it = instList[tid].end(); 4722292SN/A --squash_it; 4731061SN/A 4742292SN/A MemDepHashIt hash_it; 4751061SN/A 4762292SN/A while (!instList[tid].empty() && 4772292SN/A (*squash_it)->seqNum > squashed_num) { 4781061SN/A 4792292SN/A DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n", 4802292SN/A (*squash_it)->seqNum); 4811061SN/A 4822292SN/A hash_it = memDepHash.find((*squash_it)->seqNum); 4831061SN/A 4842292SN/A assert(hash_it != memDepHash.end()); 4851062SN/A 4862292SN/A (*hash_it).second->squashed = true; 4871717SN/A 4882292SN/A (*hash_it).second = NULL; 4891717SN/A 4902292SN/A memDepHash.erase(hash_it); 4912678Sktlim@umich.edu#ifdef DEBUG 4922292SN/A MemDepEntry::memdep_erase++; 4932678Sktlim@umich.edu#endif 4941717SN/A 4952292SN/A instList[tid].erase(squash_it--); 4961061SN/A } 4971061SN/A 4981061SN/A // Tell the dependency predictor to squash as well. 4992292SN/A depPred.squash(squashed_num, tid); 5001061SN/A} 5011061SN/A 5021061SN/Atemplate <class MemDepPred, class Impl> 5031061SN/Avoid 5041061SN/AMemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst, 5051061SN/A DynInstPtr &violating_load) 5061061SN/A{ 5072292SN/A DPRINTF(MemDepUnit, "Passing violating PCs to store sets," 5087720Sgblack@eecs.umich.edu " load: %#x, store: %#x\n", violating_load->instAddr(), 5097720Sgblack@eecs.umich.edu store_inst->instAddr()); 5101061SN/A // Tell the memory dependence unit of the violation. 5117720Sgblack@eecs.umich.edu depPred.violation(violating_load->instAddr(), store_inst->instAddr()); 5121061SN/A} 5131062SN/A 5141062SN/Atemplate <class MemDepPred, class Impl> 5152292SN/Avoid 5162292SN/AMemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst) 5172292SN/A{ 5182292SN/A DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n", 5197720Sgblack@eecs.umich.edu inst->instAddr(), inst->seqNum); 5202292SN/A 5217720Sgblack@eecs.umich.edu depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore()); 5222292SN/A} 5232292SN/A 5242292SN/Atemplate <class MemDepPred, class Impl> 5252292SN/Ainline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr & 5262292SN/AMemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst) 5272292SN/A{ 5282292SN/A MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 5292292SN/A 5302292SN/A assert(hash_it != memDepHash.end()); 5312292SN/A 5322292SN/A return (*hash_it).second; 5332292SN/A} 5342292SN/A 5352292SN/Atemplate <class MemDepPred, class Impl> 5361062SN/Ainline void 5372292SN/AMemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry) 5381062SN/A{ 5392292SN/A DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] " 5402292SN/A "to the ready list.\n", woken_inst_entry->inst->seqNum); 5411062SN/A 5422292SN/A assert(!woken_inst_entry->squashed); 5431062SN/A 5442292SN/A iqPtr->addReadyMemInst(woken_inst_entry->inst); 5451062SN/A} 5462292SN/A 5472292SN/A 5482292SN/Atemplate <class MemDepPred, class Impl> 5492292SN/Avoid 5502292SN/AMemDepUnit<MemDepPred, Impl>::dumpLists() 5512292SN/A{ 5526221Snate@binkert.org for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 5532292SN/A cprintf("Instruction list %i size: %i\n", 5542292SN/A tid, instList[tid].size()); 5552292SN/A 5562292SN/A ListIt inst_list_it = instList[tid].begin(); 5572292SN/A int num = 0; 5582292SN/A 5592292SN/A while (inst_list_it != instList[tid].end()) { 5607720Sgblack@eecs.umich.edu cprintf("Instruction:%i\nPC: %s\n[sn:%i]\n[tid:%i]\nIssued:%i\n" 5612292SN/A "Squashed:%i\n\n", 5627720Sgblack@eecs.umich.edu num, (*inst_list_it)->pcState(), 5632292SN/A (*inst_list_it)->seqNum, 5642292SN/A (*inst_list_it)->threadNumber, 5652292SN/A (*inst_list_it)->isIssued(), 5662292SN/A (*inst_list_it)->isSquashed()); 5672292SN/A inst_list_it++; 5682292SN/A ++num; 5692292SN/A } 5702292SN/A } 5712292SN/A 5722292SN/A cprintf("Memory dependence hash size: %i\n", memDepHash.size()); 5732292SN/A 5742678Sktlim@umich.edu#ifdef DEBUG 5752292SN/A cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count); 5762678Sktlim@umich.edu#endif 5772292SN/A} 578