mem_dep_unit_impl.hh revision 2307 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <map>
30
31#include "cpu/o3/inst_queue.hh"
32#include "cpu/o3/mem_dep_unit.hh"
33
34template <class MemDepPred, class Impl>
35MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params)
36    : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
37      loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
38{
39    DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
40}
41
42template <class MemDepPred, class Impl>
43MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
44{
45    for (int tid=0; tid < Impl::MaxThreads; tid++) {
46
47        ListIt inst_list_it = instList[tid].begin();
48
49        MemDepHashIt hash_it;
50
51        while (!instList[tid].empty()) {
52            hash_it = memDepHash.find((*inst_list_it)->seqNum);
53
54            assert(hash_it != memDepHash.end());
55
56            memDepHash.erase(hash_it);
57
58            instList[tid].erase(inst_list_it++);
59        }
60    }
61
62    assert(MemDepEntry::memdep_count == 0);
63}
64
65template <class MemDepPred, class Impl>
66std::string
67MemDepUnit<MemDepPred, Impl>::name() const
68{
69    return "memdepunit";
70}
71
72template <class MemDepPred, class Impl>
73void
74MemDepUnit<MemDepPred, Impl>::init(Params *params, int tid)
75{
76    DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
77
78    id = tid;
79
80    depPred.init(params->SSITSize, params->LFSTSize);
81}
82
83template <class MemDepPred, class Impl>
84void
85MemDepUnit<MemDepPred, Impl>::regStats()
86{
87    insertedLoads
88        .name(name() + ".memDep.insertedLoads")
89        .desc("Number of loads inserted to the mem dependence unit.");
90
91    insertedStores
92        .name(name() + ".memDep.insertedStores")
93        .desc("Number of stores inserted to the mem dependence unit.");
94
95    conflictingLoads
96        .name(name() + ".memDep.conflictingLoads")
97        .desc("Number of conflicting loads.");
98
99    conflictingStores
100        .name(name() + ".memDep.conflictingStores")
101        .desc("Number of conflicting stores.");
102}
103
104template <class MemDepPred, class Impl>
105void
106MemDepUnit<MemDepPred, Impl>::switchOut()
107{
108    for (int i = 0; i < Impl::MaxThreads; ++i) {
109        instList[i].clear();
110    }
111    instsToReplay.clear();
112    memDepHash.clear();
113}
114
115template <class MemDepPred, class Impl>
116void
117MemDepUnit<MemDepPred, Impl>::takeOverFrom()
118{
119    loadBarrier = storeBarrier = false;
120    loadBarrierSN = storeBarrierSN = 0;
121    depPred.clear();
122}
123
124template <class MemDepPred, class Impl>
125void
126MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
127{
128    iqPtr = iq_ptr;
129}
130
131template <class MemDepPred, class Impl>
132void
133MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
134{
135    unsigned tid = inst->threadNumber;
136
137    MemDepEntryPtr inst_entry = new MemDepEntry(inst);
138
139    // Add the MemDepEntry to the hash.
140    memDepHash.insert(
141        std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
142    MemDepEntry::memdep_insert++;
143
144    // Add the instruction to the instruction list.
145    instList[tid].push_back(inst);
146
147    inst_entry->listIt = --(instList[tid].end());
148
149    // Check the dependence predictor for any producing stores.
150    InstSeqNum producing_store;
151    if (inst->isLoad() && loadBarrier) {
152        producing_store = loadBarrierSN;
153    } else if (inst->isStore() && storeBarrier) {
154        producing_store = storeBarrierSN;
155    } else {
156        producing_store = depPred.checkInst(inst->readPC());
157    }
158
159    MemDepEntryPtr store_entry = NULL;
160
161    // If there is a producing store, try to find the entry.
162    if (producing_store != 0) {
163        MemDepHashIt hash_it = memDepHash.find(producing_store);
164
165        if (hash_it != memDepHash.end()) {
166            store_entry = (*hash_it).second;
167        }
168    }
169
170    // If no store entry, then instruction can issue as soon as the registers
171    // are ready.
172    if (!store_entry) {
173        DPRINTF(MemDepUnit, "No dependency for inst PC "
174                "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum);
175
176        inst_entry->memDepReady = true;
177
178        if (inst->readyToIssue()) {
179            inst_entry->regsReady = true;
180
181            moveToReady(inst_entry);
182        }
183    } else {
184        // Otherwise make the instruction dependent on the store.
185        DPRINTF(MemDepUnit, "Adding to dependency list; "
186                "inst PC %#x is dependent on [sn:%lli].\n",
187                inst->readPC(), producing_store);
188
189        if (inst->readyToIssue()) {
190            inst_entry->regsReady = true;
191        }
192
193        // Add this instruction to the list of dependents.
194        store_entry->dependInsts.push_back(inst_entry);
195
196//        inst_entry->producingStore = store_entry;
197
198        if (inst->isLoad()) {
199            ++conflictingLoads;
200        } else {
201            ++conflictingStores;
202        }
203    }
204
205    if (inst->isStore()) {
206        DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
207                inst->readPC(), inst->seqNum);
208
209        depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
210
211        ++insertedStores;
212    } else if (inst->isLoad()) {
213        ++insertedLoads;
214    } else {
215        panic("Unknown type! (most likely a barrier).");
216    }
217}
218
219template <class MemDepPred, class Impl>
220void
221MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
222{
223    unsigned tid = inst->threadNumber;
224
225    MemDepEntryPtr inst_entry = new MemDepEntry(inst);
226
227    // Insert the MemDepEntry into the hash.
228    memDepHash.insert(
229        std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
230    MemDepEntry::memdep_insert++;
231
232    // Add the instruction to the list.
233    instList[tid].push_back(inst);
234
235    inst_entry->listIt = --(instList[tid].end());
236
237    // Might want to turn this part into an inline function or something.
238    // It's shared between both insert functions.
239    if (inst->isStore()) {
240        DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
241                inst->readPC(), inst->seqNum);
242
243        depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
244
245        ++insertedStores;
246    } else if (inst->isLoad()) {
247        ++insertedLoads;
248    } else {
249        panic("Unknown type! (most likely a barrier).");
250    }
251}
252
253template <class MemDepPred, class Impl>
254void
255MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
256{
257    InstSeqNum barr_sn = barr_inst->seqNum;
258    if (barr_inst->isMemBarrier()) {
259        loadBarrier = true;
260        loadBarrierSN = barr_sn;
261        storeBarrier = true;
262        storeBarrierSN = barr_sn;
263        DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
264    } else if (barr_inst->isWriteBarrier()) {
265        storeBarrier = true;
266        storeBarrierSN = barr_sn;
267        DPRINTF(MemDepUnit, "Inserted a write barrier\n");
268    }
269
270    unsigned tid = barr_inst->threadNumber;
271
272    MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
273
274    // Add the MemDepEntry to the hash.
275    memDepHash.insert(
276        std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
277    MemDepEntry::memdep_insert++;
278
279    // Add the instruction to the instruction list.
280    instList[tid].push_back(barr_inst);
281
282    inst_entry->listIt = --(instList[tid].end());
283}
284
285template <class MemDepPred, class Impl>
286void
287MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
288{
289    DPRINTF(MemDepUnit, "Marking registers as ready for "
290            "instruction PC %#x [sn:%lli].\n",
291            inst->readPC(), inst->seqNum);
292
293    MemDepEntryPtr inst_entry = findInHash(inst);
294
295    inst_entry->regsReady = true;
296
297    if (inst_entry->memDepReady) {
298        DPRINTF(MemDepUnit, "Instruction has its memory "
299                "dependencies resolved, adding it to the ready list.\n");
300
301        moveToReady(inst_entry);
302    } else {
303        DPRINTF(MemDepUnit, "Instruction still waiting on "
304                "memory dependency.\n");
305    }
306}
307
308template <class MemDepPred, class Impl>
309void
310MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
311{
312    DPRINTF(MemDepUnit, "Marking non speculative "
313            "instruction PC %#x as ready [sn:%lli].\n",
314            inst->readPC(), inst->seqNum);
315
316    MemDepEntryPtr inst_entry = findInHash(inst);
317
318    moveToReady(inst_entry);
319}
320
321template <class MemDepPred, class Impl>
322void
323MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
324{
325    instsToReplay.push_back(inst);
326}
327
328template <class MemDepPred, class Impl>
329void
330MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
331{
332    DynInstPtr temp_inst;
333    bool found_inst = false;
334
335    while (!instsToReplay.empty()) {
336        temp_inst = instsToReplay.front();
337
338        MemDepEntryPtr inst_entry = findInHash(temp_inst);
339
340        DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
341                "[sn:%lli].\n",
342                temp_inst->readPC(), temp_inst->seqNum);
343
344        moveToReady(inst_entry);
345
346        if (temp_inst == inst) {
347            found_inst = true;
348        }
349
350        instsToReplay.pop_front();
351    }
352
353    assert(found_inst);
354}
355
356template <class MemDepPred, class Impl>
357void
358MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
359{
360    DPRINTF(MemDepUnit, "Completed mem instruction PC %#x "
361            "[sn:%lli].\n",
362            inst->readPC(), inst->seqNum);
363
364    unsigned tid = inst->threadNumber;
365
366    // Remove the instruction from the hash and the list.
367    MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
368
369    assert(hash_it != memDepHash.end());
370
371    instList[tid].erase((*hash_it).second->listIt);
372
373//    (*hash_it).second->inst = NULL;
374
375    (*hash_it).second = NULL;
376
377    memDepHash.erase(hash_it);
378    MemDepEntry::memdep_erase++;
379}
380
381template <class MemDepPred, class Impl>
382void
383MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
384{
385    wakeDependents(inst);
386    completed(inst);
387
388    InstSeqNum barr_sn = inst->seqNum;
389
390    if (inst->isMemBarrier()) {
391        assert(loadBarrier && storeBarrier);
392        if (loadBarrierSN == barr_sn)
393            loadBarrier = false;
394        if (storeBarrierSN == barr_sn)
395            storeBarrier = false;
396    } else if (inst->isWriteBarrier()) {
397        assert(storeBarrier);
398        if (storeBarrierSN == barr_sn)
399            storeBarrier = false;
400    }
401}
402
403template <class MemDepPred, class Impl>
404void
405MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
406{
407    // Only stores and barriers have dependents.
408    if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
409        return;
410    }
411
412    MemDepEntryPtr inst_entry = findInHash(inst);
413
414    for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
415        MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
416
417        if (!woken_inst->inst) {
418            // Potentially removed mem dep entries could be on this list
419//            inst_entry->dependInsts[i] = NULL;
420            continue;
421        }
422
423        DPRINTF(MemDepUnit, "Waking up a dependent inst, "
424                "[sn:%lli].\n",
425                woken_inst->inst->seqNum);
426
427        if (woken_inst->regsReady && !woken_inst->squashed) {
428            moveToReady(woken_inst);
429        } else {
430            woken_inst->memDepReady = true;
431        }
432//        inst_entry->dependInsts[i] = NULL;
433    }
434
435    inst_entry->dependInsts.clear();
436}
437
438template <class MemDepPred, class Impl>
439void
440MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
441                                     unsigned tid)
442{
443    if (!instsToReplay.empty()) {
444        ListIt replay_it = instsToReplay.begin();
445        while (replay_it != instsToReplay.end()) {
446            if ((*replay_it)->threadNumber == tid &&
447                (*replay_it)->seqNum > squashed_num) {
448                instsToReplay.erase(replay_it++);
449            } else {
450                ++replay_it;
451            }
452        }
453    }
454
455    ListIt squash_it = instList[tid].end();
456    --squash_it;
457
458    MemDepHashIt hash_it;
459
460    while (!instList[tid].empty() &&
461           (*squash_it)->seqNum > squashed_num) {
462
463        DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
464                (*squash_it)->seqNum);
465
466        hash_it = memDepHash.find((*squash_it)->seqNum);
467
468        assert(hash_it != memDepHash.end());
469
470        (*hash_it).second->squashed = true;
471/*
472        for (int i = 0; i < (*hash_it).second->dependInsts.size(); ++i) {
473            (*hash_it).second->dependInsts[i] = NULL;
474        }
475
476        (*hash_it).second->inst = NULL;
477*/
478        (*hash_it).second = NULL;
479
480        memDepHash.erase(hash_it);
481        MemDepEntry::memdep_erase++;
482
483        instList[tid].erase(squash_it--);
484    }
485
486    // Tell the dependency predictor to squash as well.
487    depPred.squash(squashed_num, tid);
488}
489
490template <class MemDepPred, class Impl>
491void
492MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
493                                        DynInstPtr &violating_load)
494{
495    DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
496            " load: %#x, store: %#x\n", violating_load->readPC(),
497            store_inst->readPC());
498    // Tell the memory dependence unit of the violation.
499    depPred.violation(violating_load->readPC(), store_inst->readPC());
500}
501
502template <class MemDepPred, class Impl>
503void
504MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
505{
506    DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
507            inst->readPC(), inst->seqNum);
508
509    depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
510}
511
512template <class MemDepPred, class Impl>
513inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
514MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
515{
516    MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
517
518    assert(hash_it != memDepHash.end());
519
520    return (*hash_it).second;
521}
522
523template <class MemDepPred, class Impl>
524inline void
525MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
526{
527    DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
528            "to the ready list.\n", woken_inst_entry->inst->seqNum);
529
530    assert(!woken_inst_entry->squashed);
531
532    iqPtr->addReadyMemInst(woken_inst_entry->inst);
533}
534
535
536template <class MemDepPred, class Impl>
537void
538MemDepUnit<MemDepPred, Impl>::dumpLists()
539{
540    for (unsigned tid=0; tid < Impl::MaxThreads; tid++) {
541        cprintf("Instruction list %i size: %i\n",
542                tid, instList[tid].size());
543
544        ListIt inst_list_it = instList[tid].begin();
545        int num = 0;
546
547        while (inst_list_it != instList[tid].end()) {
548            cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
549                    "Squashed:%i\n\n",
550                    num, (*inst_list_it)->readPC(),
551                    (*inst_list_it)->seqNum,
552                    (*inst_list_it)->threadNumber,
553                    (*inst_list_it)->isIssued(),
554                    (*inst_list_it)->isSquashed());
555            inst_list_it++;
556            ++num;
557        }
558    }
559
560    cprintf("Memory dependence hash size: %i\n", memDepHash.size());
561
562    cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
563}
564