mem_dep_unit_impl.hh revision 10473
11689SN/A/* 210333Smitch.hayenga@arm.com * Copyright (c) 2012, 2014 ARM Limited 39444SAndreas.Sandberg@ARM.com * All rights reserved 49444SAndreas.Sandberg@ARM.com * 59444SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69444SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79444SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89444SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99444SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109444SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119444SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129444SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139444SAndreas.Sandberg@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421061SN/A 439944Smatt.horsnell@ARM.com#ifndef __CPU_O3_MEM_DEP_UNIT_IMPL_HH__ 449944Smatt.horsnell@ARM.com#define __CPU_O3_MEM_DEP_UNIT_IMPL_HH__ 459944Smatt.horsnell@ARM.com 461061SN/A#include <map> 471061SN/A 482292SN/A#include "cpu/o3/inst_queue.hh" 491717SN/A#include "cpu/o3/mem_dep_unit.hh" 508232Snate@binkert.org#include "debug/MemDepUnit.hh" 515529Snate@binkert.org#include "params/DerivO3CPU.hh" 525529Snate@binkert.org 531061SN/Atemplate <class MemDepPred, class Impl> 543500Sktlim@umich.eduMemDepUnit<MemDepPred, Impl>::MemDepUnit() 553500Sktlim@umich.edu : loadBarrier(false), loadBarrierSN(0), storeBarrier(false), 563500Sktlim@umich.edu storeBarrierSN(0), iqPtr(NULL) 573500Sktlim@umich.edu{ 583500Sktlim@umich.edu} 593500Sktlim@umich.edu 603500Sktlim@umich.edutemplate <class MemDepPred, class Impl> 615529Snate@binkert.orgMemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params) 626005Snate@binkert.org : _name(params->name + ".memdepunit"), 638519SAli.Saidi@ARM.com depPred(params->store_set_clear_period, params->SSITSize, 648519SAli.Saidi@ARM.com params->LFSTSize), 658519SAli.Saidi@ARM.com loadBarrier(false), loadBarrierSN(0), storeBarrier(false), 668519SAli.Saidi@ARM.com storeBarrierSN(0), iqPtr(NULL) 671061SN/A{ 682292SN/A DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n"); 692292SN/A} 702292SN/A 712292SN/Atemplate <class MemDepPred, class Impl> 722292SN/AMemDepUnit<MemDepPred, Impl>::~MemDepUnit() 732292SN/A{ 746221Snate@binkert.org for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 752292SN/A 762292SN/A ListIt inst_list_it = instList[tid].begin(); 772292SN/A 782292SN/A MemDepHashIt hash_it; 792292SN/A 802292SN/A while (!instList[tid].empty()) { 812292SN/A hash_it = memDepHash.find((*inst_list_it)->seqNum); 822292SN/A 832292SN/A assert(hash_it != memDepHash.end()); 842292SN/A 852292SN/A memDepHash.erase(hash_it); 862292SN/A 872292SN/A instList[tid].erase(inst_list_it++); 882292SN/A } 892292SN/A } 902292SN/A 912678Sktlim@umich.edu#ifdef DEBUG 922292SN/A assert(MemDepEntry::memdep_count == 0); 932678Sktlim@umich.edu#endif 942292SN/A} 952292SN/A 962292SN/Atemplate <class MemDepPred, class Impl> 972292SN/Avoid 986221Snate@binkert.orgMemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, ThreadID tid) 992292SN/A{ 1002292SN/A DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid); 1012292SN/A 1026005Snate@binkert.org _name = csprintf("%s.memDep%d", params->name, tid); 1032292SN/A id = tid; 1042292SN/A 1058519SAli.Saidi@ARM.com depPred.init(params->store_set_clear_period, params->SSITSize, 1068519SAli.Saidi@ARM.com params->LFSTSize); 1071061SN/A} 1081061SN/A 1091061SN/Atemplate <class MemDepPred, class Impl> 1101061SN/Avoid 1111062SN/AMemDepUnit<MemDepPred, Impl>::regStats() 1121062SN/A{ 1131062SN/A insertedLoads 1146005Snate@binkert.org .name(name() + ".insertedLoads") 1151062SN/A .desc("Number of loads inserted to the mem dependence unit."); 1161062SN/A 1171062SN/A insertedStores 1186005Snate@binkert.org .name(name() + ".insertedStores") 1191062SN/A .desc("Number of stores inserted to the mem dependence unit."); 1201062SN/A 1211062SN/A conflictingLoads 1226005Snate@binkert.org .name(name() + ".conflictingLoads") 1231062SN/A .desc("Number of conflicting loads."); 1241062SN/A 1251062SN/A conflictingStores 1266005Snate@binkert.org .name(name() + ".conflictingStores") 1271062SN/A .desc("Number of conflicting stores."); 1281062SN/A} 1291062SN/A 1301062SN/Atemplate <class MemDepPred, class Impl> 1311062SN/Avoid 1329444SAndreas.Sandberg@ARM.comMemDepUnit<MemDepPred, Impl>::drainSanityCheck() const 1332307SN/A{ 1342367SN/A assert(instsToReplay.empty()); 1352367SN/A assert(memDepHash.empty()); 1369444SAndreas.Sandberg@ARM.com for (int i = 0; i < Impl::MaxThreads; ++i) 1379444SAndreas.Sandberg@ARM.com assert(instList[i].empty()); 1389444SAndreas.Sandberg@ARM.com assert(instsToReplay.empty()); 1399444SAndreas.Sandberg@ARM.com assert(memDepHash.empty()); 1402307SN/A} 1412307SN/A 1422307SN/Atemplate <class MemDepPred, class Impl> 1432307SN/Avoid 1442307SN/AMemDepUnit<MemDepPred, Impl>::takeOverFrom() 1452307SN/A{ 1462348SN/A // Be sure to reset all state. 1472307SN/A loadBarrier = storeBarrier = false; 1482307SN/A loadBarrierSN = storeBarrierSN = 0; 1492307SN/A depPred.clear(); 1502307SN/A} 1512307SN/A 1522307SN/Atemplate <class MemDepPred, class Impl> 1532307SN/Avoid 1542292SN/AMemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr) 1552292SN/A{ 1562292SN/A iqPtr = iq_ptr; 1572292SN/A} 1582292SN/A 1592292SN/Atemplate <class MemDepPred, class Impl> 1602292SN/Avoid 1611061SN/AMemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst) 1621061SN/A{ 1636221Snate@binkert.org ThreadID tid = inst->threadNumber; 1641061SN/A 16510473Sandreas.hansson@arm.com MemDepEntryPtr inst_entry = std::make_shared<MemDepEntry>(inst); 1661061SN/A 1672292SN/A // Add the MemDepEntry to the hash. 1682292SN/A memDepHash.insert( 1692292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 1702678Sktlim@umich.edu#ifdef DEBUG 1712292SN/A MemDepEntry::memdep_insert++; 1722678Sktlim@umich.edu#endif 1731061SN/A 1742292SN/A instList[tid].push_back(inst); 1751062SN/A 1762292SN/A inst_entry->listIt = --(instList[tid].end()); 1771062SN/A 1782329SN/A // Check any barriers and the dependence predictor for any 1792348SN/A // producing memrefs/stores. 1802292SN/A InstSeqNum producing_store; 1812292SN/A if (inst->isLoad() && loadBarrier) { 1823500Sktlim@umich.edu DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n", 1833500Sktlim@umich.edu loadBarrierSN); 1842292SN/A producing_store = loadBarrierSN; 1852292SN/A } else if (inst->isStore() && storeBarrier) { 1863500Sktlim@umich.edu DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n", 1873500Sktlim@umich.edu storeBarrierSN); 1882292SN/A producing_store = storeBarrierSN; 1892292SN/A } else { 1907720Sgblack@eecs.umich.edu producing_store = depPred.checkInst(inst->instAddr()); 1912292SN/A } 1922292SN/A 1932292SN/A MemDepEntryPtr store_entry = NULL; 1942292SN/A 1952292SN/A // If there is a producing store, try to find the entry. 1962292SN/A if (producing_store != 0) { 1973500Sktlim@umich.edu DPRINTF(MemDepUnit, "Searching for producer\n"); 1982292SN/A MemDepHashIt hash_it = memDepHash.find(producing_store); 1992292SN/A 2002292SN/A if (hash_it != memDepHash.end()) { 2012292SN/A store_entry = (*hash_it).second; 2023500Sktlim@umich.edu DPRINTF(MemDepUnit, "Proucer found\n"); 2032292SN/A } 2042292SN/A } 2052292SN/A 2062292SN/A // If no store entry, then instruction can issue as soon as the registers 2072292SN/A // are ready. 2082292SN/A if (!store_entry) { 2092292SN/A DPRINTF(MemDepUnit, "No dependency for inst PC " 2107720Sgblack@eecs.umich.edu "%s [sn:%lli].\n", inst->pcState(), inst->seqNum); 2112292SN/A 2122292SN/A inst_entry->memDepReady = true; 2131062SN/A 2141062SN/A if (inst->readyToIssue()) { 2152292SN/A inst_entry->regsReady = true; 2161062SN/A 2172292SN/A moveToReady(inst_entry); 2181062SN/A } 2191061SN/A } else { 2202329SN/A // Otherwise make the instruction dependent on the store/barrier. 2212292SN/A DPRINTF(MemDepUnit, "Adding to dependency list; " 2227720Sgblack@eecs.umich.edu "inst PC %s is dependent on [sn:%lli].\n", 2237720Sgblack@eecs.umich.edu inst->pcState(), producing_store); 2241062SN/A 2251062SN/A if (inst->readyToIssue()) { 2262292SN/A inst_entry->regsReady = true; 2271062SN/A } 2281062SN/A 2294033Sktlim@umich.edu // Clear the bit saying this instruction can issue. 2304033Sktlim@umich.edu inst->clearCanIssue(); 2314033Sktlim@umich.edu 2321062SN/A // Add this instruction to the list of dependents. 2332292SN/A store_entry->dependInsts.push_back(inst_entry); 2341062SN/A 2351062SN/A if (inst->isLoad()) { 2361062SN/A ++conflictingLoads; 2371062SN/A } else { 2381062SN/A ++conflictingStores; 2391062SN/A } 2401061SN/A } 2411061SN/A 2421061SN/A if (inst->isStore()) { 2437720Sgblack@eecs.umich.edu DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n", 2447720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 2451062SN/A 2467720Sgblack@eecs.umich.edu depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber); 2471062SN/A 2481062SN/A ++insertedStores; 2491062SN/A } else if (inst->isLoad()) { 2501062SN/A ++insertedLoads; 2511062SN/A } else { 2522292SN/A panic("Unknown type! (most likely a barrier)."); 2531061SN/A } 2541062SN/A} 2551062SN/A 2561062SN/Atemplate <class MemDepPred, class Impl> 2571062SN/Avoid 2581062SN/AMemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst) 2591062SN/A{ 2606221Snate@binkert.org ThreadID tid = inst->threadNumber; 2611062SN/A 26210473Sandreas.hansson@arm.com MemDepEntryPtr inst_entry = std::make_shared<MemDepEntry>(inst); 2631062SN/A 2642292SN/A // Insert the MemDepEntry into the hash. 2652292SN/A memDepHash.insert( 2662292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry)); 2672678Sktlim@umich.edu#ifdef DEBUG 2682292SN/A MemDepEntry::memdep_insert++; 2692678Sktlim@umich.edu#endif 2701062SN/A 2712292SN/A // Add the instruction to the list. 2722292SN/A instList[tid].push_back(inst); 2732292SN/A 2742292SN/A inst_entry->listIt = --(instList[tid].end()); 2751062SN/A 2761062SN/A // Might want to turn this part into an inline function or something. 2771062SN/A // It's shared between both insert functions. 2781062SN/A if (inst->isStore()) { 2797720Sgblack@eecs.umich.edu DPRINTF(MemDepUnit, "Inserting store PC %s [sn:%lli].\n", 2807720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 2811062SN/A 2827720Sgblack@eecs.umich.edu depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber); 2831062SN/A 2841062SN/A ++insertedStores; 2851062SN/A } else if (inst->isLoad()) { 2861062SN/A ++insertedLoads; 2871062SN/A } else { 2882292SN/A panic("Unknown type! (most likely a barrier)."); 2891062SN/A } 2901062SN/A} 2911062SN/A 2921062SN/Atemplate <class MemDepPred, class Impl> 2931062SN/Avoid 2942292SN/AMemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst) 2951062SN/A{ 2962292SN/A InstSeqNum barr_sn = barr_inst->seqNum; 2972348SN/A // Memory barriers block loads and stores, write barriers only stores. 2982292SN/A if (barr_inst->isMemBarrier()) { 2992292SN/A loadBarrier = true; 3002292SN/A loadBarrierSN = barr_sn; 3012292SN/A storeBarrier = true; 3022292SN/A storeBarrierSN = barr_sn; 3038516SMrinmoy.Ghosh@arm.com DPRINTF(MemDepUnit, "Inserted a memory barrier %s SN:%lli\n", 3048516SMrinmoy.Ghosh@arm.com barr_inst->pcState(),barr_sn); 3052292SN/A } else if (barr_inst->isWriteBarrier()) { 3062292SN/A storeBarrier = true; 3072292SN/A storeBarrierSN = barr_sn; 3082292SN/A DPRINTF(MemDepUnit, "Inserted a write barrier\n"); 3092292SN/A } 3101062SN/A 3116221Snate@binkert.org ThreadID tid = barr_inst->threadNumber; 3121062SN/A 31310473Sandreas.hansson@arm.com MemDepEntryPtr inst_entry = std::make_shared<MemDepEntry>(barr_inst); 3141062SN/A 3152292SN/A // Add the MemDepEntry to the hash. 3162292SN/A memDepHash.insert( 3172292SN/A std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry)); 3182678Sktlim@umich.edu#ifdef DEBUG 3192292SN/A MemDepEntry::memdep_insert++; 3202678Sktlim@umich.edu#endif 3211062SN/A 3222292SN/A // Add the instruction to the instruction list. 3232292SN/A instList[tid].push_back(barr_inst); 3242292SN/A 3252292SN/A inst_entry->listIt = --(instList[tid].end()); 3261062SN/A} 3271062SN/A 3281062SN/Atemplate <class MemDepPred, class Impl> 3291062SN/Avoid 3301062SN/AMemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst) 3311062SN/A{ 3322292SN/A DPRINTF(MemDepUnit, "Marking registers as ready for " 3337720Sgblack@eecs.umich.edu "instruction PC %s [sn:%lli].\n", 3347720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 3351062SN/A 3362292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 3371062SN/A 3382292SN/A inst_entry->regsReady = true; 3391062SN/A 3402292SN/A if (inst_entry->memDepReady) { 3412292SN/A DPRINTF(MemDepUnit, "Instruction has its memory " 3421062SN/A "dependencies resolved, adding it to the ready list.\n"); 3431062SN/A 3442292SN/A moveToReady(inst_entry); 3451062SN/A } else { 3462292SN/A DPRINTF(MemDepUnit, "Instruction still waiting on " 3471062SN/A "memory dependency.\n"); 3481062SN/A } 3491061SN/A} 3501061SN/A 3511061SN/Atemplate <class MemDepPred, class Impl> 3521062SN/Avoid 3531062SN/AMemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst) 3541061SN/A{ 3552292SN/A DPRINTF(MemDepUnit, "Marking non speculative " 3567720Sgblack@eecs.umich.edu "instruction PC %s as ready [sn:%lli].\n", 3577720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 3581062SN/A 3592292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 3601061SN/A 3612292SN/A moveToReady(inst_entry); 3621061SN/A} 3631061SN/A 3641061SN/Atemplate <class MemDepPred, class Impl> 3651061SN/Avoid 3662292SN/AMemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst) 3671061SN/A{ 3682292SN/A instsToReplay.push_back(inst); 3692292SN/A} 3701061SN/A 3712292SN/Atemplate <class MemDepPred, class Impl> 3722292SN/Avoid 37310333Smitch.hayenga@arm.comMemDepUnit<MemDepPred, Impl>::replay() 3742292SN/A{ 3752292SN/A DynInstPtr temp_inst; 3761062SN/A 3772348SN/A // For now this replay function replays all waiting memory ops. 3782292SN/A while (!instsToReplay.empty()) { 3792292SN/A temp_inst = instsToReplay.front(); 3801062SN/A 3812292SN/A MemDepEntryPtr inst_entry = findInHash(temp_inst); 3822292SN/A 3837720Sgblack@eecs.umich.edu DPRINTF(MemDepUnit, "Replaying mem instruction PC %s [sn:%lli].\n", 3847720Sgblack@eecs.umich.edu temp_inst->pcState(), temp_inst->seqNum); 3852292SN/A 3862292SN/A moveToReady(inst_entry); 3872292SN/A 3882292SN/A instsToReplay.pop_front(); 3892292SN/A } 3902292SN/A} 3912292SN/A 3922292SN/Atemplate <class MemDepPred, class Impl> 3932292SN/Avoid 3942292SN/AMemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst) 3952292SN/A{ 3967720Sgblack@eecs.umich.edu DPRINTF(MemDepUnit, "Completed mem instruction PC %s [sn:%lli].\n", 3977720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 3982292SN/A 3996221Snate@binkert.org ThreadID tid = inst->threadNumber; 4002292SN/A 4012292SN/A // Remove the instruction from the hash and the list. 4022292SN/A MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 4032292SN/A 4042292SN/A assert(hash_it != memDepHash.end()); 4052292SN/A 4062292SN/A instList[tid].erase((*hash_it).second->listIt); 4072292SN/A 4082292SN/A (*hash_it).second = NULL; 4092292SN/A 4102292SN/A memDepHash.erase(hash_it); 4112678Sktlim@umich.edu#ifdef DEBUG 4122292SN/A MemDepEntry::memdep_erase++; 4132678Sktlim@umich.edu#endif 4142292SN/A} 4152292SN/A 4162292SN/Atemplate <class MemDepPred, class Impl> 4172292SN/Avoid 4182292SN/AMemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst) 4192292SN/A{ 4202292SN/A wakeDependents(inst); 4212292SN/A completed(inst); 4222292SN/A 4232292SN/A InstSeqNum barr_sn = inst->seqNum; 4248515SMrinmoy.Ghosh@arm.com DPRINTF(MemDepUnit, "barrier completed: %s SN:%lli\n", inst->pcState(), 4258515SMrinmoy.Ghosh@arm.com inst->seqNum); 4262292SN/A if (inst->isMemBarrier()) { 4272292SN/A if (loadBarrierSN == barr_sn) 4282292SN/A loadBarrier = false; 4292292SN/A if (storeBarrierSN == barr_sn) 4302292SN/A storeBarrier = false; 4312292SN/A } else if (inst->isWriteBarrier()) { 4322292SN/A if (storeBarrierSN == barr_sn) 4332292SN/A storeBarrier = false; 4342292SN/A } 4351061SN/A} 4361061SN/A 4371061SN/Atemplate <class MemDepPred, class Impl> 4381061SN/Avoid 4391061SN/AMemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst) 4401061SN/A{ 4412292SN/A // Only stores and barriers have dependents. 4422292SN/A if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) { 4431062SN/A return; 4441062SN/A } 4451062SN/A 4462292SN/A MemDepEntryPtr inst_entry = findInHash(inst); 4471061SN/A 4482292SN/A for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) { 4492292SN/A MemDepEntryPtr woken_inst = inst_entry->dependInsts[i]; 4501062SN/A 4512292SN/A if (!woken_inst->inst) { 4522292SN/A // Potentially removed mem dep entries could be on this list 4532292SN/A continue; 4542292SN/A } 4551061SN/A 4562292SN/A DPRINTF(MemDepUnit, "Waking up a dependent inst, " 4572292SN/A "[sn:%lli].\n", 4582292SN/A woken_inst->inst->seqNum); 4591061SN/A 4602292SN/A if (woken_inst->regsReady && !woken_inst->squashed) { 4611062SN/A moveToReady(woken_inst); 4621062SN/A } else { 4632292SN/A woken_inst->memDepReady = true; 4641062SN/A } 4651061SN/A } 4661061SN/A 4672292SN/A inst_entry->dependInsts.clear(); 4681061SN/A} 4691061SN/A 4701061SN/Atemplate <class MemDepPred, class Impl> 4711061SN/Avoid 4722292SN/AMemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num, 4736221Snate@binkert.org ThreadID tid) 4741061SN/A{ 4752292SN/A if (!instsToReplay.empty()) { 4762292SN/A ListIt replay_it = instsToReplay.begin(); 4772292SN/A while (replay_it != instsToReplay.end()) { 4782292SN/A if ((*replay_it)->threadNumber == tid && 4792292SN/A (*replay_it)->seqNum > squashed_num) { 4802292SN/A instsToReplay.erase(replay_it++); 4812292SN/A } else { 4822292SN/A ++replay_it; 4831062SN/A } 4841061SN/A } 4851061SN/A } 4861061SN/A 4872292SN/A ListIt squash_it = instList[tid].end(); 4882292SN/A --squash_it; 4891061SN/A 4902292SN/A MemDepHashIt hash_it; 4911061SN/A 4922292SN/A while (!instList[tid].empty() && 4932292SN/A (*squash_it)->seqNum > squashed_num) { 4941061SN/A 4952292SN/A DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n", 4962292SN/A (*squash_it)->seqNum); 4971061SN/A 4988515SMrinmoy.Ghosh@arm.com if ((*squash_it)->seqNum == loadBarrierSN) 4998515SMrinmoy.Ghosh@arm.com loadBarrier = false; 5008515SMrinmoy.Ghosh@arm.com 5018515SMrinmoy.Ghosh@arm.com if ((*squash_it)->seqNum == storeBarrierSN) 5028515SMrinmoy.Ghosh@arm.com storeBarrier = false; 5038515SMrinmoy.Ghosh@arm.com 5042292SN/A hash_it = memDepHash.find((*squash_it)->seqNum); 5051061SN/A 5062292SN/A assert(hash_it != memDepHash.end()); 5071062SN/A 5082292SN/A (*hash_it).second->squashed = true; 5091717SN/A 5102292SN/A (*hash_it).second = NULL; 5111717SN/A 5122292SN/A memDepHash.erase(hash_it); 5132678Sktlim@umich.edu#ifdef DEBUG 5142292SN/A MemDepEntry::memdep_erase++; 5152678Sktlim@umich.edu#endif 5161717SN/A 5172292SN/A instList[tid].erase(squash_it--); 5181061SN/A } 5191061SN/A 5201061SN/A // Tell the dependency predictor to squash as well. 5212292SN/A depPred.squash(squashed_num, tid); 5221061SN/A} 5231061SN/A 5241061SN/Atemplate <class MemDepPred, class Impl> 5251061SN/Avoid 5261061SN/AMemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst, 5271061SN/A DynInstPtr &violating_load) 5281061SN/A{ 5292292SN/A DPRINTF(MemDepUnit, "Passing violating PCs to store sets," 5307720Sgblack@eecs.umich.edu " load: %#x, store: %#x\n", violating_load->instAddr(), 5317720Sgblack@eecs.umich.edu store_inst->instAddr()); 5321061SN/A // Tell the memory dependence unit of the violation. 5338515SMrinmoy.Ghosh@arm.com depPred.violation(store_inst->instAddr(), violating_load->instAddr()); 5341061SN/A} 5351062SN/A 5361062SN/Atemplate <class MemDepPred, class Impl> 5372292SN/Avoid 5382292SN/AMemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst) 5392292SN/A{ 5402292SN/A DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n", 5417720Sgblack@eecs.umich.edu inst->instAddr(), inst->seqNum); 5422292SN/A 5437720Sgblack@eecs.umich.edu depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore()); 5442292SN/A} 5452292SN/A 5462292SN/Atemplate <class MemDepPred, class Impl> 5472292SN/Ainline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr & 5482292SN/AMemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst) 5492292SN/A{ 5502292SN/A MemDepHashIt hash_it = memDepHash.find(inst->seqNum); 5512292SN/A 5522292SN/A assert(hash_it != memDepHash.end()); 5532292SN/A 5542292SN/A return (*hash_it).second; 5552292SN/A} 5562292SN/A 5572292SN/Atemplate <class MemDepPred, class Impl> 5581062SN/Ainline void 5592292SN/AMemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry) 5601062SN/A{ 5612292SN/A DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] " 5622292SN/A "to the ready list.\n", woken_inst_entry->inst->seqNum); 5631062SN/A 5642292SN/A assert(!woken_inst_entry->squashed); 5651062SN/A 5662292SN/A iqPtr->addReadyMemInst(woken_inst_entry->inst); 5671062SN/A} 5682292SN/A 5692292SN/A 5702292SN/Atemplate <class MemDepPred, class Impl> 5712292SN/Avoid 5722292SN/AMemDepUnit<MemDepPred, Impl>::dumpLists() 5732292SN/A{ 5746221Snate@binkert.org for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 5752292SN/A cprintf("Instruction list %i size: %i\n", 5762292SN/A tid, instList[tid].size()); 5772292SN/A 5782292SN/A ListIt inst_list_it = instList[tid].begin(); 5792292SN/A int num = 0; 5802292SN/A 5812292SN/A while (inst_list_it != instList[tid].end()) { 5827720Sgblack@eecs.umich.edu cprintf("Instruction:%i\nPC: %s\n[sn:%i]\n[tid:%i]\nIssued:%i\n" 5832292SN/A "Squashed:%i\n\n", 5847720Sgblack@eecs.umich.edu num, (*inst_list_it)->pcState(), 5852292SN/A (*inst_list_it)->seqNum, 5862292SN/A (*inst_list_it)->threadNumber, 5872292SN/A (*inst_list_it)->isIssued(), 5882292SN/A (*inst_list_it)->isSquashed()); 5892292SN/A inst_list_it++; 5902292SN/A ++num; 5912292SN/A } 5922292SN/A } 5932292SN/A 5942292SN/A cprintf("Memory dependence hash size: %i\n", memDepHash.size()); 5952292SN/A 5962678Sktlim@umich.edu#ifdef DEBUG 5972292SN/A cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count); 5982678Sktlim@umich.edu#endif 5992292SN/A} 6009944Smatt.horsnell@ARM.com 6019944Smatt.horsnell@ARM.com#endif//__CPU_O3_MEM_DEP_UNIT_IMPL_HH__ 602