mem_dep_unit.hh revision 5529
16019Shines@cs.fsu.edu/* 27416SAli.Saidi@ARM.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 37416SAli.Saidi@ARM.com * All rights reserved. 47416SAli.Saidi@ARM.com * 57416SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67416SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77416SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87416SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97416SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107416SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117416SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127416SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137416SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 146019Shines@cs.fsu.edu * this software without specific prior written permission. 156019Shines@cs.fsu.edu * 166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * Authors: Kevin Lim 296019Shines@cs.fsu.edu */ 306019Shines@cs.fsu.edu 316019Shines@cs.fsu.edu#ifndef __CPU_O3_MEM_DEP_UNIT_HH__ 326019Shines@cs.fsu.edu#define __CPU_O3_MEM_DEP_UNIT_HH__ 336019Shines@cs.fsu.edu 346019Shines@cs.fsu.edu#include <list> 356019Shines@cs.fsu.edu#include <set> 366019Shines@cs.fsu.edu 376019Shines@cs.fsu.edu#include "base/hashmap.hh" 386019Shines@cs.fsu.edu#include "base/refcnt.hh" 396019Shines@cs.fsu.edu#include "base/statistics.hh" 406019Shines@cs.fsu.edu#include "cpu/inst_seq.hh" 417416SAli.Saidi@ARM.com 427416SAli.Saidi@ARM.comstruct SNHash { 436019Shines@cs.fsu.edu size_t operator() (const InstSeqNum &seq_num) const { 446019Shines@cs.fsu.edu unsigned a = (unsigned)seq_num; 456019Shines@cs.fsu.edu unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF; 466019Shines@cs.fsu.edu 476019Shines@cs.fsu.edu return hash; 486019Shines@cs.fsu.edu } 496019Shines@cs.fsu.edu}; 506019Shines@cs.fsu.edu 516019Shines@cs.fsu.educlass DerivO3CPUParams; 526019Shines@cs.fsu.edu 536019Shines@cs.fsu.edutemplate <class Impl> 546019Shines@cs.fsu.educlass InstructionQueue; 556019Shines@cs.fsu.edu 566019Shines@cs.fsu.edu/** 576019Shines@cs.fsu.edu * Memory dependency unit class. This holds the memory dependence predictor. 586019Shines@cs.fsu.edu * As memory operations are issued to the IQ, they are also issued to this 596019Shines@cs.fsu.edu * unit, which then looks up the prediction as to what they are dependent 606019Shines@cs.fsu.edu * upon. This unit must be checked prior to a memory operation being able 616019Shines@cs.fsu.edu * to issue. Although this is templated, it's somewhat hard to make a generic 627416SAli.Saidi@ARM.com * memory dependence unit. This one is mostly for store sets; it will be 637416SAli.Saidi@ARM.com * quite limited in what other memory dependence predictions it can also 647416SAli.Saidi@ARM.com * utilize. Thus this class should be most likely be rewritten for other 657416SAli.Saidi@ARM.com * dependence prediction schemes. 667416SAli.Saidi@ARM.com */ 677416SAli.Saidi@ARM.comtemplate <class MemDepPred, class Impl> 687416SAli.Saidi@ARM.comclass MemDepUnit { 697416SAli.Saidi@ARM.com public: 706019Shines@cs.fsu.edu typedef typename Impl::DynInstPtr DynInstPtr; 716341Sjack-m5ml2@cs.york.ac.uk 726341Sjack-m5ml2@cs.york.ac.uk /** Empty constructor. Must call init() prior to using in this case. */ 736341Sjack-m5ml2@cs.york.ac.uk MemDepUnit(); 746341Sjack-m5ml2@cs.york.ac.uk 756341Sjack-m5ml2@cs.york.ac.uk /** Constructs a MemDepUnit with given parameters. */ 766341Sjack-m5ml2@cs.york.ac.uk MemDepUnit(DerivO3CPUParams *params); 776341Sjack-m5ml2@cs.york.ac.uk 786341Sjack-m5ml2@cs.york.ac.uk /** Frees up any memory allocated. */ 796341Sjack-m5ml2@cs.york.ac.uk ~MemDepUnit(); 806341Sjack-m5ml2@cs.york.ac.uk 816341Sjack-m5ml2@cs.york.ac.uk /** Returns the name of the memory dependence unit. */ 827441SAli.Saidi@ARM.com std::string name() const; 837441SAli.Saidi@ARM.com 847441SAli.Saidi@ARM.com /** Initializes the unit with parameters and a thread id. */ 857441SAli.Saidi@ARM.com void init(DerivO3CPUParams *params, int tid); 866341Sjack-m5ml2@cs.york.ac.uk 877441SAli.Saidi@ARM.com /** Registers statistics. */ 887441SAli.Saidi@ARM.com void regStats(); 897441SAli.Saidi@ARM.com 906019Shines@cs.fsu.edu /** Switches out the memory dependence predictor. */ 916019Shines@cs.fsu.edu void switchOut(); 926019Shines@cs.fsu.edu 936413Ssaidi@eecs.umich.edu /** Takes over from another CPU's thread. */ 948600Ssteve.reinhardt@amd.com void takeOverFrom(); 956019Shines@cs.fsu.edu 966019Shines@cs.fsu.edu /** Sets the pointer to the IQ. */ 976019Shines@cs.fsu.edu void setIQ(InstructionQueue<Impl> *iq_ptr); 986019Shines@cs.fsu.edu 996019Shines@cs.fsu.edu /** Inserts a memory instruction. */ 1006019Shines@cs.fsu.edu void insert(DynInstPtr &inst); 1016019Shines@cs.fsu.edu 1026019Shines@cs.fsu.edu /** Inserts a non-speculative memory instruction. */ 1036019Shines@cs.fsu.edu void insertNonSpec(DynInstPtr &inst); 1046019Shines@cs.fsu.edu 1056415Ssaidi@eecs.umich.edu /** Inserts a barrier instruction. */ 1066019Shines@cs.fsu.edu void insertBarrier(DynInstPtr &barr_inst); 1076019Shines@cs.fsu.edu 1086019Shines@cs.fsu.edu /** Indicate that an instruction has its registers ready. */ 1096019Shines@cs.fsu.edu void regsReady(DynInstPtr &inst); 1106019Shines@cs.fsu.edu 1116019Shines@cs.fsu.edu /** Indicate that a non-speculative instruction is ready. */ 1126019Shines@cs.fsu.edu void nonSpecInstReady(DynInstPtr &inst); 1137441SAli.Saidi@ARM.com 1146689Stjones1@inf.ed.ac.uk /** Reschedules an instruction to be re-executed. */ 1156019Shines@cs.fsu.edu void reschedule(DynInstPtr &inst); 1166019Shines@cs.fsu.edu 1176019Shines@cs.fsu.edu /** Replays all instructions that have been rescheduled by moving them to 1186019Shines@cs.fsu.edu * the ready list. 1196019Shines@cs.fsu.edu */ 1206019Shines@cs.fsu.edu void replay(DynInstPtr &inst); 1216019Shines@cs.fsu.edu 1226019Shines@cs.fsu.edu /** Completes a memory instruction. */ 1236019Shines@cs.fsu.edu void completed(DynInstPtr &inst); 1246019Shines@cs.fsu.edu 1256019Shines@cs.fsu.edu /** Completes a barrier instruction. */ 1266019Shines@cs.fsu.edu void completeBarrier(DynInstPtr &inst); 1276413Ssaidi@eecs.umich.edu 1286413Ssaidi@eecs.umich.edu /** Wakes any dependents of a memory instruction. */ 1296413Ssaidi@eecs.umich.edu void wakeDependents(DynInstPtr &inst); 1306413Ssaidi@eecs.umich.edu 1316413Ssaidi@eecs.umich.edu /** Squashes all instructions up until a given sequence number for a 1326019Shines@cs.fsu.edu * specific thread. 1336019Shines@cs.fsu.edu */ 1346019Shines@cs.fsu.edu void squash(const InstSeqNum &squashed_num, unsigned tid); 1357416SAli.Saidi@ARM.com 1367416SAli.Saidi@ARM.com /** Indicates an ordering violation between a store and a younger load. */ 1377416SAli.Saidi@ARM.com void violation(DynInstPtr &store_inst, DynInstPtr &violating_load); 1387416SAli.Saidi@ARM.com 1397416SAli.Saidi@ARM.com /** Issues the given instruction */ 1407416SAli.Saidi@ARM.com void issue(DynInstPtr &inst); 1417416SAli.Saidi@ARM.com 1427416SAli.Saidi@ARM.com /** Debugging function to dump the lists of instructions. */ 1437416SAli.Saidi@ARM.com void dumpLists(); 1447416SAli.Saidi@ARM.com 1457416SAli.Saidi@ARM.com private: 1467416SAli.Saidi@ARM.com typedef typename std::list<DynInstPtr>::iterator ListIt; 1477416SAli.Saidi@ARM.com 1487416SAli.Saidi@ARM.com class MemDepEntry; 1497416SAli.Saidi@ARM.com 1507416SAli.Saidi@ARM.com typedef RefCountingPtr<MemDepEntry> MemDepEntryPtr; 1517416SAli.Saidi@ARM.com 1527416SAli.Saidi@ARM.com /** Memory dependence entries that track memory operations, marking 1537416SAli.Saidi@ARM.com * when the instruction is ready to execute and what instructions depend 1546395Ssaidi@eecs.umich.edu * upon it. 1556395Ssaidi@eecs.umich.edu */ 1566395Ssaidi@eecs.umich.edu class MemDepEntry : public RefCounted { 1576395Ssaidi@eecs.umich.edu public: 1586395Ssaidi@eecs.umich.edu /** Constructs a memory dependence entry. */ 1596395Ssaidi@eecs.umich.edu MemDepEntry(DynInstPtr &new_inst) 1606395Ssaidi@eecs.umich.edu : inst(new_inst), regsReady(false), memDepReady(false), 1616395Ssaidi@eecs.umich.edu completed(false), squashed(false) 1626395Ssaidi@eecs.umich.edu { 1636395Ssaidi@eecs.umich.edu#ifdef DEBUG 1646395Ssaidi@eecs.umich.edu ++memdep_count; 1656395Ssaidi@eecs.umich.edu 1666395Ssaidi@eecs.umich.edu DPRINTF(MemDepUnit, "Memory dependency entry created. " 1676395Ssaidi@eecs.umich.edu "memdep_count=%i\n", memdep_count); 1686395Ssaidi@eecs.umich.edu#endif 1696395Ssaidi@eecs.umich.edu } 1706395Ssaidi@eecs.umich.edu 1716395Ssaidi@eecs.umich.edu /** Frees any pointers. */ 1726395Ssaidi@eecs.umich.edu ~MemDepEntry() 1736395Ssaidi@eecs.umich.edu { 1746395Ssaidi@eecs.umich.edu for (int i = 0; i < dependInsts.size(); ++i) { 1756395Ssaidi@eecs.umich.edu dependInsts[i] = NULL; 1766395Ssaidi@eecs.umich.edu } 1776395Ssaidi@eecs.umich.edu#ifdef DEBUG 1786395Ssaidi@eecs.umich.edu --memdep_count; 1796395Ssaidi@eecs.umich.edu 1806395Ssaidi@eecs.umich.edu DPRINTF(MemDepUnit, "Memory dependency entry deleted. " 1816395Ssaidi@eecs.umich.edu "memdep_count=%i\n", memdep_count); 1826395Ssaidi@eecs.umich.edu#endif 1836395Ssaidi@eecs.umich.edu } 1846395Ssaidi@eecs.umich.edu 1856395Ssaidi@eecs.umich.edu /** Returns the name of the memory dependence entry. */ 1866395Ssaidi@eecs.umich.edu std::string name() const { return "memdepentry"; } 1876395Ssaidi@eecs.umich.edu 1886395Ssaidi@eecs.umich.edu /** The instruction being tracked. */ 1896395Ssaidi@eecs.umich.edu DynInstPtr inst; 1906395Ssaidi@eecs.umich.edu 1916395Ssaidi@eecs.umich.edu /** The iterator to the instruction's location inside the list. */ 1926395Ssaidi@eecs.umich.edu ListIt listIt; 1936395Ssaidi@eecs.umich.edu 1946395Ssaidi@eecs.umich.edu /** A vector of any dependent instructions. */ 1956640Svince@csl.cornell.edu std::vector<MemDepEntryPtr> dependInsts; 1966640Svince@csl.cornell.edu 1976640Svince@csl.cornell.edu /** If the registers are ready or not. */ 1986640Svince@csl.cornell.edu bool regsReady; 1996640Svince@csl.cornell.edu /** If all memory dependencies have been satisfied. */ 2006640Svince@csl.cornell.edu bool memDepReady; 2016640Svince@csl.cornell.edu /** If the instruction is completed. */ 2026640Svince@csl.cornell.edu bool completed; 2036640Svince@csl.cornell.edu /** If the instruction is squashed. */ 2046640Svince@csl.cornell.edu bool squashed; 2056640Svince@csl.cornell.edu 2066640Svince@csl.cornell.edu /** For debugging. */ 2076640Svince@csl.cornell.edu#ifdef DEBUG 2086640Svince@csl.cornell.edu static int memdep_count; 2096640Svince@csl.cornell.edu static int memdep_insert; 2107416SAli.Saidi@ARM.com static int memdep_erase; 2117416SAli.Saidi@ARM.com#endif 2127416SAli.Saidi@ARM.com }; 2137416SAli.Saidi@ARM.com 2147416SAli.Saidi@ARM.com /** Finds the memory dependence entry in the hash map. */ 2157416SAli.Saidi@ARM.com inline MemDepEntryPtr &findInHash(const DynInstPtr &inst); 2167416SAli.Saidi@ARM.com 2177416SAli.Saidi@ARM.com /** Moves an entry to the ready list. */ 2187416SAli.Saidi@ARM.com inline void moveToReady(MemDepEntryPtr &ready_inst_entry); 2197416SAli.Saidi@ARM.com 2207416SAli.Saidi@ARM.com typedef m5::hash_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash; 2217416SAli.Saidi@ARM.com 2227416SAli.Saidi@ARM.com typedef typename MemDepHash::iterator MemDepHashIt; 2237416SAli.Saidi@ARM.com 2247416SAli.Saidi@ARM.com /** A hash map of all memory dependence entries. */ 2257416SAli.Saidi@ARM.com MemDepHash memDepHash; 2267416SAli.Saidi@ARM.com 2277416SAli.Saidi@ARM.com /** A list of all instructions in the memory dependence unit. */ 2287416SAli.Saidi@ARM.com std::list<DynInstPtr> instList[Impl::MaxThreads]; 2297416SAli.Saidi@ARM.com 2307416SAli.Saidi@ARM.com /** A list of all instructions that are going to be replayed. */ 2317416SAli.Saidi@ARM.com std::list<DynInstPtr> instsToReplay; 2327416SAli.Saidi@ARM.com 2337416SAli.Saidi@ARM.com /** The memory dependence predictor. It is accessed upon new 2347416SAli.Saidi@ARM.com * instructions being added to the IQ, and responds by telling 2357416SAli.Saidi@ARM.com * this unit what instruction the newly added instruction is dependent 2367416SAli.Saidi@ARM.com * upon. 2377416SAli.Saidi@ARM.com */ 2386395Ssaidi@eecs.umich.edu MemDepPred depPred; 2396019Shines@cs.fsu.edu 2406019Shines@cs.fsu.edu /** Is there an outstanding load barrier that loads must wait on. */ 2416019Shines@cs.fsu.edu bool loadBarrier; 242 /** The sequence number of the load barrier. */ 243 InstSeqNum loadBarrierSN; 244 /** Is there an outstanding store barrier that loads must wait on. */ 245 bool storeBarrier; 246 /** The sequence number of the store barrier. */ 247 InstSeqNum storeBarrierSN; 248 249 /** Pointer to the IQ. */ 250 InstructionQueue<Impl> *iqPtr; 251 252 /** The thread id of this memory dependence unit. */ 253 int id; 254 255 /** Stat for number of inserted loads. */ 256 Stats::Scalar<> insertedLoads; 257 /** Stat for number of inserted stores. */ 258 Stats::Scalar<> insertedStores; 259 /** Stat for number of conflicting loads that had to wait for a store. */ 260 Stats::Scalar<> conflictingLoads; 261 /** Stat for number of conflicting stores that had to wait for a store. */ 262 Stats::Scalar<> conflictingStores; 263}; 264 265#endif // __CPU_O3_MEM_DEP_UNIT_HH__ 266