mem_dep_unit.hh revision 10473 
1/*
2 * Copyright (c) 2012, 2014 ARM Limited
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4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
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18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
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26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_O3_MEM_DEP_UNIT_HH__
44#define __CPU_O3_MEM_DEP_UNIT_HH__
45
46#include <list>
47#include <memory>
48#include <set>
49
50#include "base/hashmap.hh"
51#include "base/statistics.hh"
52#include "cpu/inst_seq.hh"
53#include "debug/MemDepUnit.hh"
54
55struct SNHash {
56    size_t operator() (const InstSeqNum &seq_num) const {
57        unsigned a = (unsigned)seq_num;
58        unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
59
60        return hash;
61    }
62};
63
64struct DerivO3CPUParams;
65
66template <class Impl>
67class InstructionQueue;
68
69/**
70 * Memory dependency unit class.  This holds the memory dependence predictor.
71 * As memory operations are issued to the IQ, they are also issued to this
72 * unit, which then looks up the prediction as to what they are dependent
73 * upon.  This unit must be checked prior to a memory operation being able
74 * to issue.  Although this is templated, it's somewhat hard to make a generic
75 * memory dependence unit.  This one is mostly for store sets; it will be
76 * quite limited in what other memory dependence predictions it can also
77 * utilize.  Thus this class should be most likely be rewritten for other
78 * dependence prediction schemes.
79 */
80template <class MemDepPred, class Impl>
81class MemDepUnit
82{
83  protected:
84    std::string _name;
85
86  public:
87    typedef typename Impl::DynInstPtr DynInstPtr;
88
89    /** Empty constructor. Must call init() prior to using in this case. */
90    MemDepUnit();
91
92    /** Constructs a MemDepUnit with given parameters. */
93    MemDepUnit(DerivO3CPUParams *params);
94
95    /** Frees up any memory allocated. */
96    ~MemDepUnit();
97
98    /** Returns the name of the memory dependence unit. */
99    std::string name() const { return _name; }
100
101    /** Initializes the unit with parameters and a thread id. */
102    void init(DerivO3CPUParams *params, ThreadID tid);
103
104    /** Registers statistics. */
105    void regStats();
106
107    /** Perform sanity checks after a drain. */
108    void drainSanityCheck() const;
109
110    /** Takes over from another CPU's thread. */
111    void takeOverFrom();
112
113    /** Sets the pointer to the IQ. */
114    void setIQ(InstructionQueue<Impl> *iq_ptr);
115
116    /** Inserts a memory instruction. */
117    void insert(DynInstPtr &inst);
118
119    /** Inserts a non-speculative memory instruction. */
120    void insertNonSpec(DynInstPtr &inst);
121
122    /** Inserts a barrier instruction. */
123    void insertBarrier(DynInstPtr &barr_inst);
124
125    /** Indicate that an instruction has its registers ready. */
126    void regsReady(DynInstPtr &inst);
127
128    /** Indicate that a non-speculative instruction is ready. */
129    void nonSpecInstReady(DynInstPtr &inst);
130
131    /** Reschedules an instruction to be re-executed. */
132    void reschedule(DynInstPtr &inst);
133
134    /** Replays all instructions that have been rescheduled by moving them to
135     *  the ready list.
136     */
137    void replay();
138
139    /** Completes a memory instruction. */
140    void completed(DynInstPtr &inst);
141
142    /** Completes a barrier instruction. */
143    void completeBarrier(DynInstPtr &inst);
144
145    /** Wakes any dependents of a memory instruction. */
146    void wakeDependents(DynInstPtr &inst);
147
148    /** Squashes all instructions up until a given sequence number for a
149     *  specific thread.
150     */
151    void squash(const InstSeqNum &squashed_num, ThreadID tid);
152
153    /** Indicates an ordering violation between a store and a younger load. */
154    void violation(DynInstPtr &store_inst, DynInstPtr &violating_load);
155
156    /** Issues the given instruction */
157    void issue(DynInstPtr &inst);
158
159    /** Debugging function to dump the lists of instructions. */
160    void dumpLists();
161
162  private:
163    typedef typename std::list<DynInstPtr>::iterator ListIt;
164
165    class MemDepEntry;
166
167    typedef std::shared_ptr<MemDepEntry> MemDepEntryPtr;
168
169    /** Memory dependence entries that track memory operations, marking
170     *  when the instruction is ready to execute and what instructions depend
171     *  upon it.
172     */
173    class MemDepEntry {
174      public:
175        /** Constructs a memory dependence entry. */
176        MemDepEntry(DynInstPtr &new_inst)
177            : inst(new_inst), regsReady(false), memDepReady(false),
178              completed(false), squashed(false)
179        {
180#ifdef DEBUG
181            ++memdep_count;
182
183            DPRINTF(MemDepUnit, "Memory dependency entry created.  "
184                    "memdep_count=%i %s\n", memdep_count, inst->pcState());
185#endif
186        }
187
188        /** Frees any pointers. */
189        ~MemDepEntry()
190        {
191            for (int i = 0; i < dependInsts.size(); ++i) {
192                dependInsts[i] = NULL;
193            }
194#ifdef DEBUG
195            --memdep_count;
196
197            DPRINTF(MemDepUnit, "Memory dependency entry deleted.  "
198                    "memdep_count=%i %s\n", memdep_count, inst->pcState());
199#endif
200        }
201
202        /** Returns the name of the memory dependence entry. */
203        std::string name() const { return "memdepentry"; }
204
205        /** The instruction being tracked. */
206        DynInstPtr inst;
207
208        /** The iterator to the instruction's location inside the list. */
209        ListIt listIt;
210
211        /** A vector of any dependent instructions. */
212        std::vector<MemDepEntryPtr> dependInsts;
213
214        /** If the registers are ready or not. */
215        bool regsReady;
216        /** If all memory dependencies have been satisfied. */
217        bool memDepReady;
218        /** If the instruction is completed. */
219        bool completed;
220        /** If the instruction is squashed. */
221        bool squashed;
222
223        /** For debugging. */
224#ifdef DEBUG
225        static int memdep_count;
226        static int memdep_insert;
227        static int memdep_erase;
228#endif
229    };
230
231    /** Finds the memory dependence entry in the hash map. */
232    inline MemDepEntryPtr &findInHash(const DynInstPtr &inst);
233
234    /** Moves an entry to the ready list. */
235    inline void moveToReady(MemDepEntryPtr &ready_inst_entry);
236
237    typedef m5::hash_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash;
238
239    typedef typename MemDepHash::iterator MemDepHashIt;
240
241    /** A hash map of all memory dependence entries. */
242    MemDepHash memDepHash;
243
244    /** A list of all instructions in the memory dependence unit. */
245    std::list<DynInstPtr> instList[Impl::MaxThreads];
246
247    /** A list of all instructions that are going to be replayed. */
248    std::list<DynInstPtr> instsToReplay;
249
250    /** The memory dependence predictor.  It is accessed upon new
251     *  instructions being added to the IQ, and responds by telling
252     *  this unit what instruction the newly added instruction is dependent
253     *  upon.
254     */
255    MemDepPred depPred;
256
257    /** Is there an outstanding load barrier that loads must wait on. */
258    bool loadBarrier;
259    /** The sequence number of the load barrier. */
260    InstSeqNum loadBarrierSN;
261    /** Is there an outstanding store barrier that loads must wait on. */
262    bool storeBarrier;
263    /** The sequence number of the store barrier. */
264    InstSeqNum storeBarrierSN;
265
266    /** Pointer to the IQ. */
267    InstructionQueue<Impl> *iqPtr;
268
269    /** The thread id of this memory dependence unit. */
270    int id;
271
272    /** Stat for number of inserted loads. */
273    Stats::Scalar insertedLoads;
274    /** Stat for number of inserted stores. */
275    Stats::Scalar insertedStores;
276    /** Stat for number of conflicting loads that had to wait for a store. */
277    Stats::Scalar conflictingLoads;
278    /** Stat for number of conflicting stores that had to wait for a store. */
279    Stats::Scalar conflictingStores;
280};
281
282#endif // __CPU_O3_MEM_DEP_UNIT_HH__
283