mem_dep_unit.hh revision 6005
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301061SN/A 312292SN/A#ifndef __CPU_O3_MEM_DEP_UNIT_HH__ 322292SN/A#define __CPU_O3_MEM_DEP_UNIT_HH__ 331061SN/A 342292SN/A#include <list> 351061SN/A#include <set> 361061SN/A 372292SN/A#include "base/hashmap.hh" 382292SN/A#include "base/refcnt.hh" 391684SN/A#include "base/statistics.hh" 401061SN/A#include "cpu/inst_seq.hh" 411061SN/A 422292SN/Astruct SNHash { 432292SN/A size_t operator() (const InstSeqNum &seq_num) const { 442292SN/A unsigned a = (unsigned)seq_num; 452292SN/A unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF; 462292SN/A 472292SN/A return hash; 482292SN/A } 492292SN/A}; 502292SN/A 515529Snate@binkert.orgclass DerivO3CPUParams; 525529Snate@binkert.org 532292SN/Atemplate <class Impl> 542292SN/Aclass InstructionQueue; 552292SN/A 561061SN/A/** 571061SN/A * Memory dependency unit class. This holds the memory dependence predictor. 581061SN/A * As memory operations are issued to the IQ, they are also issued to this 591061SN/A * unit, which then looks up the prediction as to what they are dependent 601061SN/A * upon. This unit must be checked prior to a memory operation being able 611061SN/A * to issue. Although this is templated, it's somewhat hard to make a generic 621061SN/A * memory dependence unit. This one is mostly for store sets; it will be 631061SN/A * quite limited in what other memory dependence predictions it can also 641061SN/A * utilize. Thus this class should be most likely be rewritten for other 651061SN/A * dependence prediction schemes. 661061SN/A */ 671061SN/Atemplate <class MemDepPred, class Impl> 686005Snate@binkert.orgclass MemDepUnit 696005Snate@binkert.org{ 706005Snate@binkert.org protected: 716005Snate@binkert.org std::string _name; 726005Snate@binkert.org 731061SN/A public: 741061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 751061SN/A 762292SN/A /** Empty constructor. Must call init() prior to using in this case. */ 773500Sktlim@umich.edu MemDepUnit(); 781061SN/A 792292SN/A /** Constructs a MemDepUnit with given parameters. */ 805529Snate@binkert.org MemDepUnit(DerivO3CPUParams *params); 812292SN/A 822292SN/A /** Frees up any memory allocated. */ 832292SN/A ~MemDepUnit(); 842292SN/A 852292SN/A /** Returns the name of the memory dependence unit. */ 866005Snate@binkert.org std::string name() const { return _name; } 872292SN/A 882292SN/A /** Initializes the unit with parameters and a thread id. */ 895529Snate@binkert.org void init(DerivO3CPUParams *params, int tid); 902292SN/A 912292SN/A /** Registers statistics. */ 921062SN/A void regStats(); 931061SN/A 942348SN/A /** Switches out the memory dependence predictor. */ 952307SN/A void switchOut(); 962307SN/A 972348SN/A /** Takes over from another CPU's thread. */ 982307SN/A void takeOverFrom(); 992307SN/A 1002292SN/A /** Sets the pointer to the IQ. */ 1012292SN/A void setIQ(InstructionQueue<Impl> *iq_ptr); 1022292SN/A 1032292SN/A /** Inserts a memory instruction. */ 1041061SN/A void insert(DynInstPtr &inst); 1051061SN/A 1062292SN/A /** Inserts a non-speculative memory instruction. */ 1071062SN/A void insertNonSpec(DynInstPtr &inst); 1081062SN/A 1092292SN/A /** Inserts a barrier instruction. */ 1102292SN/A void insertBarrier(DynInstPtr &barr_inst); 1111684SN/A 1122292SN/A /** Indicate that an instruction has its registers ready. */ 1131062SN/A void regsReady(DynInstPtr &inst); 1141062SN/A 1152292SN/A /** Indicate that a non-speculative instruction is ready. */ 1161062SN/A void nonSpecInstReady(DynInstPtr &inst); 1171061SN/A 1182292SN/A /** Reschedules an instruction to be re-executed. */ 1192292SN/A void reschedule(DynInstPtr &inst); 1202292SN/A 1212292SN/A /** Replays all instructions that have been rescheduled by moving them to 1222292SN/A * the ready list. 1232292SN/A */ 1242292SN/A void replay(DynInstPtr &inst); 1252292SN/A 1262292SN/A /** Completes a memory instruction. */ 1272292SN/A void completed(DynInstPtr &inst); 1282292SN/A 1292292SN/A /** Completes a barrier instruction. */ 1302292SN/A void completeBarrier(DynInstPtr &inst); 1312292SN/A 1322292SN/A /** Wakes any dependents of a memory instruction. */ 1332292SN/A void wakeDependents(DynInstPtr &inst); 1342292SN/A 1352292SN/A /** Squashes all instructions up until a given sequence number for a 1362292SN/A * specific thread. 1372292SN/A */ 1382292SN/A void squash(const InstSeqNum &squashed_num, unsigned tid); 1392292SN/A 1402292SN/A /** Indicates an ordering violation between a store and a younger load. */ 1412292SN/A void violation(DynInstPtr &store_inst, DynInstPtr &violating_load); 1422292SN/A 1432292SN/A /** Issues the given instruction */ 1441061SN/A void issue(DynInstPtr &inst); 1451061SN/A 1462292SN/A /** Debugging function to dump the lists of instructions. */ 1472292SN/A void dumpLists(); 1481062SN/A 1491062SN/A private: 1502292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1511062SN/A 1522292SN/A class MemDepEntry; 1531062SN/A 1542292SN/A typedef RefCountingPtr<MemDepEntry> MemDepEntryPtr; 1551062SN/A 1562292SN/A /** Memory dependence entries that track memory operations, marking 1572292SN/A * when the instruction is ready to execute and what instructions depend 1582292SN/A * upon it. 1592292SN/A */ 1602292SN/A class MemDepEntry : public RefCounted { 1612292SN/A public: 1622292SN/A /** Constructs a memory dependence entry. */ 1632292SN/A MemDepEntry(DynInstPtr &new_inst) 1642292SN/A : inst(new_inst), regsReady(false), memDepReady(false), 1652292SN/A completed(false), squashed(false) 1662292SN/A { 1672348SN/A#ifdef DEBUG 1682292SN/A ++memdep_count; 1691062SN/A 1702292SN/A DPRINTF(MemDepUnit, "Memory dependency entry created. " 1712292SN/A "memdep_count=%i\n", memdep_count); 1722348SN/A#endif 1732292SN/A } 1741062SN/A 1752292SN/A /** Frees any pointers. */ 1762292SN/A ~MemDepEntry() 1772292SN/A { 1782292SN/A for (int i = 0; i < dependInsts.size(); ++i) { 1792292SN/A dependInsts[i] = NULL; 1802292SN/A } 1812348SN/A#ifdef DEBUG 1822292SN/A --memdep_count; 1832292SN/A 1842292SN/A DPRINTF(MemDepUnit, "Memory dependency entry deleted. " 1852292SN/A "memdep_count=%i\n", memdep_count); 1862348SN/A#endif 1872292SN/A } 1882292SN/A 1892292SN/A /** Returns the name of the memory dependence entry. */ 1902292SN/A std::string name() const { return "memdepentry"; } 1912292SN/A 1922292SN/A /** The instruction being tracked. */ 1932292SN/A DynInstPtr inst; 1942292SN/A 1952292SN/A /** The iterator to the instruction's location inside the list. */ 1962292SN/A ListIt listIt; 1972292SN/A 1982292SN/A /** A vector of any dependent instructions. */ 1992292SN/A std::vector<MemDepEntryPtr> dependInsts; 2002292SN/A 2012292SN/A /** If the registers are ready or not. */ 2022292SN/A bool regsReady; 2032292SN/A /** If all memory dependencies have been satisfied. */ 2042292SN/A bool memDepReady; 2052292SN/A /** If the instruction is completed. */ 2062292SN/A bool completed; 2072292SN/A /** If the instruction is squashed. */ 2082292SN/A bool squashed; 2092292SN/A 2102292SN/A /** For debugging. */ 2112348SN/A#ifdef DEBUG 2122292SN/A static int memdep_count; 2132292SN/A static int memdep_insert; 2142292SN/A static int memdep_erase; 2152348SN/A#endif 2161062SN/A }; 2171062SN/A 2182292SN/A /** Finds the memory dependence entry in the hash map. */ 2192292SN/A inline MemDepEntryPtr &findInHash(const DynInstPtr &inst); 2201062SN/A 2212292SN/A /** Moves an entry to the ready list. */ 2222292SN/A inline void moveToReady(MemDepEntryPtr &ready_inst_entry); 2231062SN/A 2242292SN/A typedef m5::hash_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash; 2251061SN/A 2262292SN/A typedef typename MemDepHash::iterator MemDepHashIt; 2271061SN/A 2282292SN/A /** A hash map of all memory dependence entries. */ 2292292SN/A MemDepHash memDepHash; 2301062SN/A 2312292SN/A /** A list of all instructions in the memory dependence unit. */ 2322292SN/A std::list<DynInstPtr> instList[Impl::MaxThreads]; 2331062SN/A 2342292SN/A /** A list of all instructions that are going to be replayed. */ 2352292SN/A std::list<DynInstPtr> instsToReplay; 2361061SN/A 2371061SN/A /** The memory dependence predictor. It is accessed upon new 2381061SN/A * instructions being added to the IQ, and responds by telling 2391061SN/A * this unit what instruction the newly added instruction is dependent 2401061SN/A * upon. 2411061SN/A */ 2421061SN/A MemDepPred depPred; 2431061SN/A 2442348SN/A /** Is there an outstanding load barrier that loads must wait on. */ 2452292SN/A bool loadBarrier; 2462348SN/A /** The sequence number of the load barrier. */ 2472292SN/A InstSeqNum loadBarrierSN; 2482348SN/A /** Is there an outstanding store barrier that loads must wait on. */ 2492292SN/A bool storeBarrier; 2502348SN/A /** The sequence number of the store barrier. */ 2512292SN/A InstSeqNum storeBarrierSN; 2522292SN/A 2532292SN/A /** Pointer to the IQ. */ 2542292SN/A InstructionQueue<Impl> *iqPtr; 2552292SN/A 2562292SN/A /** The thread id of this memory dependence unit. */ 2572292SN/A int id; 2582292SN/A 2592292SN/A /** Stat for number of inserted loads. */ 2605999Snate@binkert.org Stats::Scalar insertedLoads; 2612292SN/A /** Stat for number of inserted stores. */ 2625999Snate@binkert.org Stats::Scalar insertedStores; 2632292SN/A /** Stat for number of conflicting loads that had to wait for a store. */ 2645999Snate@binkert.org Stats::Scalar conflictingLoads; 2652292SN/A /** Stat for number of conflicting stores that had to wait for a store. */ 2665999Snate@binkert.org Stats::Scalar conflictingStores; 2671061SN/A}; 2681061SN/A 2692292SN/A#endif // __CPU_O3_MEM_DEP_UNIT_HH__ 270