mem_dep_unit.hh revision 3500
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301061SN/A 312292SN/A#ifndef __CPU_O3_MEM_DEP_UNIT_HH__ 322292SN/A#define __CPU_O3_MEM_DEP_UNIT_HH__ 331061SN/A 342292SN/A#include <list> 351061SN/A#include <set> 361061SN/A 372292SN/A#include "base/hashmap.hh" 382292SN/A#include "base/refcnt.hh" 391684SN/A#include "base/statistics.hh" 401061SN/A#include "cpu/inst_seq.hh" 411061SN/A 422292SN/Astruct SNHash { 432292SN/A size_t operator() (const InstSeqNum &seq_num) const { 442292SN/A unsigned a = (unsigned)seq_num; 452292SN/A unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF; 462292SN/A 472292SN/A return hash; 482292SN/A } 492292SN/A}; 502292SN/A 512292SN/Atemplate <class Impl> 522292SN/Aclass InstructionQueue; 532292SN/A 541061SN/A/** 551061SN/A * Memory dependency unit class. This holds the memory dependence predictor. 561061SN/A * As memory operations are issued to the IQ, they are also issued to this 571061SN/A * unit, which then looks up the prediction as to what they are dependent 581061SN/A * upon. This unit must be checked prior to a memory operation being able 591061SN/A * to issue. Although this is templated, it's somewhat hard to make a generic 601061SN/A * memory dependence unit. This one is mostly for store sets; it will be 611061SN/A * quite limited in what other memory dependence predictions it can also 621061SN/A * utilize. Thus this class should be most likely be rewritten for other 631061SN/A * dependence prediction schemes. 641061SN/A */ 651061SN/Atemplate <class MemDepPred, class Impl> 661061SN/Aclass MemDepUnit { 671061SN/A public: 681061SN/A typedef typename Impl::Params Params; 691061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 701061SN/A 712292SN/A /** Empty constructor. Must call init() prior to using in this case. */ 723500Sktlim@umich.edu MemDepUnit(); 731061SN/A 742292SN/A /** Constructs a MemDepUnit with given parameters. */ 752292SN/A MemDepUnit(Params *params); 762292SN/A 772292SN/A /** Frees up any memory allocated. */ 782292SN/A ~MemDepUnit(); 792292SN/A 802292SN/A /** Returns the name of the memory dependence unit. */ 812292SN/A std::string name() const; 822292SN/A 832292SN/A /** Initializes the unit with parameters and a thread id. */ 842292SN/A void init(Params *params, int tid); 852292SN/A 862292SN/A /** Registers statistics. */ 871062SN/A void regStats(); 881061SN/A 892348SN/A /** Switches out the memory dependence predictor. */ 902307SN/A void switchOut(); 912307SN/A 922348SN/A /** Takes over from another CPU's thread. */ 932307SN/A void takeOverFrom(); 942307SN/A 952292SN/A /** Sets the pointer to the IQ. */ 962292SN/A void setIQ(InstructionQueue<Impl> *iq_ptr); 972292SN/A 982292SN/A /** Inserts a memory instruction. */ 991061SN/A void insert(DynInstPtr &inst); 1001061SN/A 1012292SN/A /** Inserts a non-speculative memory instruction. */ 1021062SN/A void insertNonSpec(DynInstPtr &inst); 1031062SN/A 1042292SN/A /** Inserts a barrier instruction. */ 1052292SN/A void insertBarrier(DynInstPtr &barr_inst); 1061684SN/A 1072292SN/A /** Indicate that an instruction has its registers ready. */ 1081062SN/A void regsReady(DynInstPtr &inst); 1091062SN/A 1102292SN/A /** Indicate that a non-speculative instruction is ready. */ 1111062SN/A void nonSpecInstReady(DynInstPtr &inst); 1121061SN/A 1132292SN/A /** Reschedules an instruction to be re-executed. */ 1142292SN/A void reschedule(DynInstPtr &inst); 1152292SN/A 1162292SN/A /** Replays all instructions that have been rescheduled by moving them to 1172292SN/A * the ready list. 1182292SN/A */ 1192292SN/A void replay(DynInstPtr &inst); 1202292SN/A 1212292SN/A /** Completes a memory instruction. */ 1222292SN/A void completed(DynInstPtr &inst); 1232292SN/A 1242292SN/A /** Completes a barrier instruction. */ 1252292SN/A void completeBarrier(DynInstPtr &inst); 1262292SN/A 1272292SN/A /** Wakes any dependents of a memory instruction. */ 1282292SN/A void wakeDependents(DynInstPtr &inst); 1292292SN/A 1302292SN/A /** Squashes all instructions up until a given sequence number for a 1312292SN/A * specific thread. 1322292SN/A */ 1332292SN/A void squash(const InstSeqNum &squashed_num, unsigned tid); 1342292SN/A 1352292SN/A /** Indicates an ordering violation between a store and a younger load. */ 1362292SN/A void violation(DynInstPtr &store_inst, DynInstPtr &violating_load); 1372292SN/A 1382292SN/A /** Issues the given instruction */ 1391061SN/A void issue(DynInstPtr &inst); 1401061SN/A 1412292SN/A /** Debugging function to dump the lists of instructions. */ 1422292SN/A void dumpLists(); 1431062SN/A 1441062SN/A private: 1452292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1461062SN/A 1472292SN/A class MemDepEntry; 1481062SN/A 1492292SN/A typedef RefCountingPtr<MemDepEntry> MemDepEntryPtr; 1501062SN/A 1512292SN/A /** Memory dependence entries that track memory operations, marking 1522292SN/A * when the instruction is ready to execute and what instructions depend 1532292SN/A * upon it. 1542292SN/A */ 1552292SN/A class MemDepEntry : public RefCounted { 1562292SN/A public: 1572292SN/A /** Constructs a memory dependence entry. */ 1582292SN/A MemDepEntry(DynInstPtr &new_inst) 1592292SN/A : inst(new_inst), regsReady(false), memDepReady(false), 1602292SN/A completed(false), squashed(false) 1612292SN/A { 1622348SN/A#ifdef DEBUG 1632292SN/A ++memdep_count; 1641062SN/A 1652292SN/A DPRINTF(MemDepUnit, "Memory dependency entry created. " 1662292SN/A "memdep_count=%i\n", memdep_count); 1672348SN/A#endif 1682292SN/A } 1691062SN/A 1702292SN/A /** Frees any pointers. */ 1712292SN/A ~MemDepEntry() 1722292SN/A { 1732292SN/A for (int i = 0; i < dependInsts.size(); ++i) { 1742292SN/A dependInsts[i] = NULL; 1752292SN/A } 1762348SN/A#ifdef DEBUG 1772292SN/A --memdep_count; 1782292SN/A 1792292SN/A DPRINTF(MemDepUnit, "Memory dependency entry deleted. " 1802292SN/A "memdep_count=%i\n", memdep_count); 1812348SN/A#endif 1822292SN/A } 1832292SN/A 1842292SN/A /** Returns the name of the memory dependence entry. */ 1852292SN/A std::string name() const { return "memdepentry"; } 1862292SN/A 1872292SN/A /** The instruction being tracked. */ 1882292SN/A DynInstPtr inst; 1892292SN/A 1902292SN/A /** The iterator to the instruction's location inside the list. */ 1912292SN/A ListIt listIt; 1922292SN/A 1932292SN/A /** A vector of any dependent instructions. */ 1942292SN/A std::vector<MemDepEntryPtr> dependInsts; 1952292SN/A 1962292SN/A /** If the registers are ready or not. */ 1972292SN/A bool regsReady; 1982292SN/A /** If all memory dependencies have been satisfied. */ 1992292SN/A bool memDepReady; 2002292SN/A /** If the instruction is completed. */ 2012292SN/A bool completed; 2022292SN/A /** If the instruction is squashed. */ 2032292SN/A bool squashed; 2042292SN/A 2052292SN/A /** For debugging. */ 2062348SN/A#ifdef DEBUG 2072292SN/A static int memdep_count; 2082292SN/A static int memdep_insert; 2092292SN/A static int memdep_erase; 2102348SN/A#endif 2111062SN/A }; 2121062SN/A 2132292SN/A /** Finds the memory dependence entry in the hash map. */ 2142292SN/A inline MemDepEntryPtr &findInHash(const DynInstPtr &inst); 2151062SN/A 2162292SN/A /** Moves an entry to the ready list. */ 2172292SN/A inline void moveToReady(MemDepEntryPtr &ready_inst_entry); 2181062SN/A 2192292SN/A typedef m5::hash_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash; 2201061SN/A 2212292SN/A typedef typename MemDepHash::iterator MemDepHashIt; 2221061SN/A 2232292SN/A /** A hash map of all memory dependence entries. */ 2242292SN/A MemDepHash memDepHash; 2251062SN/A 2262292SN/A /** A list of all instructions in the memory dependence unit. */ 2272292SN/A std::list<DynInstPtr> instList[Impl::MaxThreads]; 2281062SN/A 2292292SN/A /** A list of all instructions that are going to be replayed. */ 2302292SN/A std::list<DynInstPtr> instsToReplay; 2311061SN/A 2321061SN/A /** The memory dependence predictor. It is accessed upon new 2331061SN/A * instructions being added to the IQ, and responds by telling 2341061SN/A * this unit what instruction the newly added instruction is dependent 2351061SN/A * upon. 2361061SN/A */ 2371061SN/A MemDepPred depPred; 2381061SN/A 2392348SN/A /** Is there an outstanding load barrier that loads must wait on. */ 2402292SN/A bool loadBarrier; 2412348SN/A /** The sequence number of the load barrier. */ 2422292SN/A InstSeqNum loadBarrierSN; 2432348SN/A /** Is there an outstanding store barrier that loads must wait on. */ 2442292SN/A bool storeBarrier; 2452348SN/A /** The sequence number of the store barrier. */ 2462292SN/A InstSeqNum storeBarrierSN; 2472292SN/A 2482292SN/A /** Pointer to the IQ. */ 2492292SN/A InstructionQueue<Impl> *iqPtr; 2502292SN/A 2512292SN/A /** The thread id of this memory dependence unit. */ 2522292SN/A int id; 2532292SN/A 2542292SN/A /** Stat for number of inserted loads. */ 2551062SN/A Stats::Scalar<> insertedLoads; 2562292SN/A /** Stat for number of inserted stores. */ 2571062SN/A Stats::Scalar<> insertedStores; 2582292SN/A /** Stat for number of conflicting loads that had to wait for a store. */ 2591062SN/A Stats::Scalar<> conflictingLoads; 2602292SN/A /** Stat for number of conflicting stores that had to wait for a store. */ 2611062SN/A Stats::Scalar<> conflictingStores; 2621061SN/A}; 2631061SN/A 2642292SN/A#endif // __CPU_O3_MEM_DEP_UNIT_HH__ 265