mem_dep_unit.hh revision 2292 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_O3_MEM_DEP_UNIT_HH__
30#define __CPU_O3_MEM_DEP_UNIT_HH__
31
32#include <list>
33#include <set>
34
35#include "base/hashmap.hh"
36#include "base/refcnt.hh"
37#include "base/statistics.hh"
38#include "cpu/inst_seq.hh"
39
40struct SNHash {
41    size_t operator() (const InstSeqNum &seq_num) const {
42        unsigned a = (unsigned)seq_num;
43        unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
44
45        return hash;
46    }
47};
48
49template <class Impl>
50class InstructionQueue;
51
52/**
53 * Memory dependency unit class.  This holds the memory dependence predictor.
54 * As memory operations are issued to the IQ, they are also issued to this
55 * unit, which then looks up the prediction as to what they are dependent
56 * upon.  This unit must be checked prior to a memory operation being able
57 * to issue.  Although this is templated, it's somewhat hard to make a generic
58 * memory dependence unit.  This one is mostly for store sets; it will be
59 * quite limited in what other memory dependence predictions it can also
60 * utilize.  Thus this class should be most likely be rewritten for other
61 * dependence prediction schemes.
62 */
63template <class MemDepPred, class Impl>
64class MemDepUnit {
65  public:
66    typedef typename Impl::Params Params;
67    typedef typename Impl::DynInstPtr DynInstPtr;
68
69    /** Empty constructor. Must call init() prior to using in this case. */
70    MemDepUnit() {}
71
72    /** Constructs a MemDepUnit with given parameters. */
73    MemDepUnit(Params *params);
74
75    /** Frees up any memory allocated. */
76    ~MemDepUnit();
77
78    /** Returns the name of the memory dependence unit. */
79    std::string name() const;
80
81    /** Initializes the unit with parameters and a thread id. */
82    void init(Params *params, int tid);
83
84    /** Registers statistics. */
85    void regStats();
86
87    /** Sets the pointer to the IQ. */
88    void setIQ(InstructionQueue<Impl> *iq_ptr);
89
90    /** Inserts a memory instruction. */
91    void insert(DynInstPtr &inst);
92
93    /** Inserts a non-speculative memory instruction. */
94    void insertNonSpec(DynInstPtr &inst);
95
96    /** Inserts a barrier instruction. */
97    void insertBarrier(DynInstPtr &barr_inst);
98
99    /** Indicate that an instruction has its registers ready. */
100    void regsReady(DynInstPtr &inst);
101
102    /** Indicate that a non-speculative instruction is ready. */
103    void nonSpecInstReady(DynInstPtr &inst);
104
105    /** Reschedules an instruction to be re-executed. */
106    void reschedule(DynInstPtr &inst);
107
108    /** Replays all instructions that have been rescheduled by moving them to
109     *  the ready list.
110     */
111    void replay(DynInstPtr &inst);
112
113    /** Completes a memory instruction. */
114    void completed(DynInstPtr &inst);
115
116    /** Completes a barrier instruction. */
117    void completeBarrier(DynInstPtr &inst);
118
119    /** Wakes any dependents of a memory instruction. */
120    void wakeDependents(DynInstPtr &inst);
121
122    /** Squashes all instructions up until a given sequence number for a
123     *  specific thread.
124     */
125    void squash(const InstSeqNum &squashed_num, unsigned tid);
126
127    /** Indicates an ordering violation between a store and a younger load. */
128    void violation(DynInstPtr &store_inst, DynInstPtr &violating_load);
129
130    /** Issues the given instruction */
131    void issue(DynInstPtr &inst);
132
133    /** Debugging function to dump the lists of instructions. */
134    void dumpLists();
135
136  private:
137    typedef typename std::list<DynInstPtr>::iterator ListIt;
138
139    class MemDepEntry;
140
141    typedef RefCountingPtr<MemDepEntry> MemDepEntryPtr;
142
143    /** Memory dependence entries that track memory operations, marking
144     *  when the instruction is ready to execute and what instructions depend
145     *  upon it.
146     */
147    class MemDepEntry : public RefCounted {
148      public:
149        /** Constructs a memory dependence entry. */
150        MemDepEntry(DynInstPtr &new_inst)
151            : inst(new_inst), regsReady(false), memDepReady(false),
152              completed(false), squashed(false)
153        {
154            ++memdep_count;
155
156            DPRINTF(MemDepUnit, "Memory dependency entry created.  "
157                    "memdep_count=%i\n", memdep_count);
158        }
159
160        /** Frees any pointers. */
161        ~MemDepEntry()
162        {
163            for (int i = 0; i < dependInsts.size(); ++i) {
164                dependInsts[i] = NULL;
165            }
166
167            --memdep_count;
168
169            DPRINTF(MemDepUnit, "Memory dependency entry deleted.  "
170                    "memdep_count=%i\n", memdep_count);
171        }
172
173        /** Returns the name of the memory dependence entry. */
174        std::string name() const { return "memdepentry"; }
175
176        /** The instruction being tracked. */
177        DynInstPtr inst;
178
179        /** The iterator to the instruction's location inside the list. */
180        ListIt listIt;
181
182        /** A vector of any dependent instructions. */
183        std::vector<MemDepEntryPtr> dependInsts;
184
185        /** If the registers are ready or not. */
186        bool regsReady;
187        /** If all memory dependencies have been satisfied. */
188        bool memDepReady;
189        /** If the instruction is completed. */
190        bool completed;
191        /** If the instruction is squashed. */
192        bool squashed;
193
194        /** For debugging. */
195        static int memdep_count;
196        static int memdep_insert;
197        static int memdep_erase;
198    };
199
200    struct ltMemDepEntry {
201        bool operator() (const MemDepEntryPtr &lhs, const MemDepEntryPtr &rhs)
202        {
203            return lhs->inst->seqNum < rhs->inst->seqNum;
204        }
205    };
206
207    /** Finds the memory dependence entry in the hash map. */
208    inline MemDepEntryPtr &findInHash(const DynInstPtr &inst);
209
210    /** Moves an entry to the ready list. */
211    inline void moveToReady(MemDepEntryPtr &ready_inst_entry);
212
213    typedef m5::hash_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash;
214
215    typedef typename MemDepHash::iterator MemDepHashIt;
216
217    /** A hash map of all memory dependence entries. */
218    MemDepHash memDepHash;
219
220    /** A list of all instructions in the memory dependence unit. */
221    std::list<DynInstPtr> instList[Impl::MaxThreads];
222
223    /** A list of all instructions that are going to be replayed. */
224    std::list<DynInstPtr> instsToReplay;
225
226    /** The memory dependence predictor.  It is accessed upon new
227     *  instructions being added to the IQ, and responds by telling
228     *  this unit what instruction the newly added instruction is dependent
229     *  upon.
230     */
231    MemDepPred depPred;
232
233    bool loadBarrier;
234    InstSeqNum loadBarrierSN;
235    bool storeBarrier;
236    InstSeqNum storeBarrierSN;
237
238    /** Pointer to the IQ. */
239    InstructionQueue<Impl> *iqPtr;
240
241    /** The thread id of this memory dependence unit. */
242    int id;
243
244    /** Stat for number of inserted loads. */
245    Stats::Scalar<> insertedLoads;
246    /** Stat for number of inserted stores. */
247    Stats::Scalar<> insertedStores;
248    /** Stat for number of conflicting loads that had to wait for a store. */
249    Stats::Scalar<> conflictingLoads;
250    /** Stat for number of conflicting stores that had to wait for a store. */
251    Stats::Scalar<> conflictingStores;
252};
253
254#endif // __CPU_O3_MEM_DEP_UNIT_HH__
255