mem_dep_unit.hh revision 11168
11689SN/A/*
210333Smitch.hayenga@arm.com * Copyright (c) 2012, 2014 ARM Limited
39444SAndreas.Sandberg@ARM.com * All rights reserved
49444SAndreas.Sandberg@ARM.com *
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79444SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating
89444SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software
99444SAndreas.Sandberg@ARM.com * licensed hereunder.  You may use the software subject to the license
109444SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated
119444SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software,
129444SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form.
139444SAndreas.Sandberg@ARM.com *
142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan
151689SN/A * All rights reserved.
161689SN/A *
171689SN/A * Redistribution and use in source and binary forms, with or without
181689SN/A * modification, are permitted provided that the following conditions are
191689SN/A * met: redistributions of source code must retain the above copyright
201689SN/A * notice, this list of conditions and the following disclaimer;
211689SN/A * redistributions in binary form must reproduce the above copyright
221689SN/A * notice, this list of conditions and the following disclaimer in the
231689SN/A * documentation and/or other materials provided with the distribution;
241689SN/A * neither the name of the copyright holders nor the names of its
251689SN/A * contributors may be used to endorse or promote products derived from
261689SN/A * this software without specific prior written permission.
271689SN/A *
281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392665Ssaidi@eecs.umich.edu *
402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
411689SN/A */
421061SN/A
432292SN/A#ifndef __CPU_O3_MEM_DEP_UNIT_HH__
442292SN/A#define __CPU_O3_MEM_DEP_UNIT_HH__
451061SN/A
462292SN/A#include <list>
4710473Sandreas.hansson@arm.com#include <memory>
481061SN/A#include <set>
4911168Sandreas.hansson@arm.com#include <unordered_map>
501061SN/A
511684SN/A#include "base/statistics.hh"
521061SN/A#include "cpu/inst_seq.hh"
538232Snate@binkert.org#include "debug/MemDepUnit.hh"
541061SN/A
552292SN/Astruct SNHash {
562292SN/A    size_t operator() (const InstSeqNum &seq_num) const {
572292SN/A        unsigned a = (unsigned)seq_num;
582292SN/A        unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
592292SN/A
602292SN/A        return hash;
612292SN/A    }
622292SN/A};
632292SN/A
648737Skoansin.tan@gmail.comstruct DerivO3CPUParams;
655529Snate@binkert.org
662292SN/Atemplate <class Impl>
672292SN/Aclass InstructionQueue;
682292SN/A
691061SN/A/**
701061SN/A * Memory dependency unit class.  This holds the memory dependence predictor.
711061SN/A * As memory operations are issued to the IQ, they are also issued to this
721061SN/A * unit, which then looks up the prediction as to what they are dependent
731061SN/A * upon.  This unit must be checked prior to a memory operation being able
741061SN/A * to issue.  Although this is templated, it's somewhat hard to make a generic
751061SN/A * memory dependence unit.  This one is mostly for store sets; it will be
761061SN/A * quite limited in what other memory dependence predictions it can also
771061SN/A * utilize.  Thus this class should be most likely be rewritten for other
781061SN/A * dependence prediction schemes.
791061SN/A */
801061SN/Atemplate <class MemDepPred, class Impl>
816005Snate@binkert.orgclass MemDepUnit
826005Snate@binkert.org{
836005Snate@binkert.org  protected:
846005Snate@binkert.org    std::string _name;
856005Snate@binkert.org
861061SN/A  public:
871061SN/A    typedef typename Impl::DynInstPtr DynInstPtr;
881061SN/A
892292SN/A    /** Empty constructor. Must call init() prior to using in this case. */
903500Sktlim@umich.edu    MemDepUnit();
911061SN/A
922292SN/A    /** Constructs a MemDepUnit with given parameters. */
935529Snate@binkert.org    MemDepUnit(DerivO3CPUParams *params);
942292SN/A
952292SN/A    /** Frees up any memory allocated. */
962292SN/A    ~MemDepUnit();
972292SN/A
982292SN/A    /** Returns the name of the memory dependence unit. */
996005Snate@binkert.org    std::string name() const { return _name; }
1002292SN/A
1012292SN/A    /** Initializes the unit with parameters and a thread id. */
1026221Snate@binkert.org    void init(DerivO3CPUParams *params, ThreadID tid);
1032292SN/A
1042292SN/A    /** Registers statistics. */
1051062SN/A    void regStats();
1061061SN/A
10710510Smitch.hayenga@arm.com    /** Determine if we are drained. */
10810510Smitch.hayenga@arm.com    bool isDrained() const;
10910510Smitch.hayenga@arm.com
1109444SAndreas.Sandberg@ARM.com    /** Perform sanity checks after a drain. */
1119444SAndreas.Sandberg@ARM.com    void drainSanityCheck() const;
1122307SN/A
1132348SN/A    /** Takes over from another CPU's thread. */
1142307SN/A    void takeOverFrom();
1152307SN/A
1162292SN/A    /** Sets the pointer to the IQ. */
1172292SN/A    void setIQ(InstructionQueue<Impl> *iq_ptr);
1182292SN/A
1192292SN/A    /** Inserts a memory instruction. */
1201061SN/A    void insert(DynInstPtr &inst);
1211061SN/A
1222292SN/A    /** Inserts a non-speculative memory instruction. */
1231062SN/A    void insertNonSpec(DynInstPtr &inst);
1241062SN/A
1252292SN/A    /** Inserts a barrier instruction. */
1262292SN/A    void insertBarrier(DynInstPtr &barr_inst);
1271684SN/A
1282292SN/A    /** Indicate that an instruction has its registers ready. */
1291062SN/A    void regsReady(DynInstPtr &inst);
1301062SN/A
1312292SN/A    /** Indicate that a non-speculative instruction is ready. */
1321062SN/A    void nonSpecInstReady(DynInstPtr &inst);
1331061SN/A
1342292SN/A    /** Reschedules an instruction to be re-executed. */
1352292SN/A    void reschedule(DynInstPtr &inst);
1362292SN/A
1372292SN/A    /** Replays all instructions that have been rescheduled by moving them to
1382292SN/A     *  the ready list.
1392292SN/A     */
14010333Smitch.hayenga@arm.com    void replay();
1412292SN/A
1422292SN/A    /** Completes a memory instruction. */
1432292SN/A    void completed(DynInstPtr &inst);
1442292SN/A
1452292SN/A    /** Completes a barrier instruction. */
1462292SN/A    void completeBarrier(DynInstPtr &inst);
1472292SN/A
1482292SN/A    /** Wakes any dependents of a memory instruction. */
1492292SN/A    void wakeDependents(DynInstPtr &inst);
1502292SN/A
1512292SN/A    /** Squashes all instructions up until a given sequence number for a
1522292SN/A     *  specific thread.
1532292SN/A     */
1546221Snate@binkert.org    void squash(const InstSeqNum &squashed_num, ThreadID tid);
1552292SN/A
1562292SN/A    /** Indicates an ordering violation between a store and a younger load. */
1572292SN/A    void violation(DynInstPtr &store_inst, DynInstPtr &violating_load);
1582292SN/A
1592292SN/A    /** Issues the given instruction */
1601061SN/A    void issue(DynInstPtr &inst);
1611061SN/A
1622292SN/A    /** Debugging function to dump the lists of instructions. */
1632292SN/A    void dumpLists();
1641062SN/A
1651062SN/A  private:
1662292SN/A    typedef typename std::list<DynInstPtr>::iterator ListIt;
1671062SN/A
1682292SN/A    class MemDepEntry;
1691062SN/A
17010473Sandreas.hansson@arm.com    typedef std::shared_ptr<MemDepEntry> MemDepEntryPtr;
1711062SN/A
1722292SN/A    /** Memory dependence entries that track memory operations, marking
1732292SN/A     *  when the instruction is ready to execute and what instructions depend
1742292SN/A     *  upon it.
1752292SN/A     */
17610473Sandreas.hansson@arm.com    class MemDepEntry {
1772292SN/A      public:
1782292SN/A        /** Constructs a memory dependence entry. */
1792292SN/A        MemDepEntry(DynInstPtr &new_inst)
1802292SN/A            : inst(new_inst), regsReady(false), memDepReady(false),
1812292SN/A              completed(false), squashed(false)
1822292SN/A        {
1832348SN/A#ifdef DEBUG
1842292SN/A            ++memdep_count;
1851062SN/A
1862292SN/A            DPRINTF(MemDepUnit, "Memory dependency entry created.  "
1878516SMrinmoy.Ghosh@arm.com                    "memdep_count=%i %s\n", memdep_count, inst->pcState());
1882348SN/A#endif
1892292SN/A        }
1901062SN/A
1912292SN/A        /** Frees any pointers. */
1922292SN/A        ~MemDepEntry()
1932292SN/A        {
1942292SN/A            for (int i = 0; i < dependInsts.size(); ++i) {
1952292SN/A                dependInsts[i] = NULL;
1962292SN/A            }
1972348SN/A#ifdef DEBUG
1982292SN/A            --memdep_count;
1992292SN/A
2002292SN/A            DPRINTF(MemDepUnit, "Memory dependency entry deleted.  "
2018516SMrinmoy.Ghosh@arm.com                    "memdep_count=%i %s\n", memdep_count, inst->pcState());
2022348SN/A#endif
2032292SN/A        }
2042292SN/A
2052292SN/A        /** Returns the name of the memory dependence entry. */
2062292SN/A        std::string name() const { return "memdepentry"; }
2072292SN/A
2082292SN/A        /** The instruction being tracked. */
2092292SN/A        DynInstPtr inst;
2102292SN/A
2112292SN/A        /** The iterator to the instruction's location inside the list. */
2122292SN/A        ListIt listIt;
2132292SN/A
2142292SN/A        /** A vector of any dependent instructions. */
2152292SN/A        std::vector<MemDepEntryPtr> dependInsts;
2162292SN/A
2172292SN/A        /** If the registers are ready or not. */
2182292SN/A        bool regsReady;
2192292SN/A        /** If all memory dependencies have been satisfied. */
2202292SN/A        bool memDepReady;
2212292SN/A        /** If the instruction is completed. */
2222292SN/A        bool completed;
2232292SN/A        /** If the instruction is squashed. */
2242292SN/A        bool squashed;
2252292SN/A
2262292SN/A        /** For debugging. */
2272348SN/A#ifdef DEBUG
2282292SN/A        static int memdep_count;
2292292SN/A        static int memdep_insert;
2302292SN/A        static int memdep_erase;
2312348SN/A#endif
2321062SN/A    };
2331062SN/A
2342292SN/A    /** Finds the memory dependence entry in the hash map. */
2352292SN/A    inline MemDepEntryPtr &findInHash(const DynInstPtr &inst);
2361062SN/A
2372292SN/A    /** Moves an entry to the ready list. */
2382292SN/A    inline void moveToReady(MemDepEntryPtr &ready_inst_entry);
2391062SN/A
24011168Sandreas.hansson@arm.com    typedef std::unordered_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash;
2411061SN/A
2422292SN/A    typedef typename MemDepHash::iterator MemDepHashIt;
2431061SN/A
2442292SN/A    /** A hash map of all memory dependence entries. */
2452292SN/A    MemDepHash memDepHash;
2461062SN/A
2472292SN/A    /** A list of all instructions in the memory dependence unit. */
2482292SN/A    std::list<DynInstPtr> instList[Impl::MaxThreads];
2491062SN/A
2502292SN/A    /** A list of all instructions that are going to be replayed. */
2512292SN/A    std::list<DynInstPtr> instsToReplay;
2521061SN/A
2531061SN/A    /** The memory dependence predictor.  It is accessed upon new
2541061SN/A     *  instructions being added to the IQ, and responds by telling
2551061SN/A     *  this unit what instruction the newly added instruction is dependent
2561061SN/A     *  upon.
2571061SN/A     */
2581061SN/A    MemDepPred depPred;
2591061SN/A
2602348SN/A    /** Is there an outstanding load barrier that loads must wait on. */
2612292SN/A    bool loadBarrier;
2622348SN/A    /** The sequence number of the load barrier. */
2632292SN/A    InstSeqNum loadBarrierSN;
2642348SN/A    /** Is there an outstanding store barrier that loads must wait on. */
2652292SN/A    bool storeBarrier;
2662348SN/A    /** The sequence number of the store barrier. */
2672292SN/A    InstSeqNum storeBarrierSN;
2682292SN/A
2692292SN/A    /** Pointer to the IQ. */
2702292SN/A    InstructionQueue<Impl> *iqPtr;
2712292SN/A
2722292SN/A    /** The thread id of this memory dependence unit. */
2732292SN/A    int id;
2742292SN/A
2752292SN/A    /** Stat for number of inserted loads. */
2765999Snate@binkert.org    Stats::Scalar insertedLoads;
2772292SN/A    /** Stat for number of inserted stores. */
2785999Snate@binkert.org    Stats::Scalar insertedStores;
2792292SN/A    /** Stat for number of conflicting loads that had to wait for a store. */
2805999Snate@binkert.org    Stats::Scalar conflictingLoads;
2812292SN/A    /** Stat for number of conflicting stores that had to wait for a store. */
2825999Snate@binkert.org    Stats::Scalar conflictingStores;
2831061SN/A};
2841061SN/A
2852292SN/A#endif // __CPU_O3_MEM_DEP_UNIT_HH__
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