mem_dep_unit.hh revision 1061
12SN/A 24039Sbinkertn@umich.edu#ifndef __MEM_DEP_UNIT_HH__ 32SN/A#define __MEM_DEP_UNIT_HH__ 42SN/A 52SN/A#include <set> 62SN/A#include <map> 72SN/A 82SN/A#include "cpu/inst_seq.hh" 92SN/A 102SN/A/** 112SN/A * Memory dependency unit class. This holds the memory dependence predictor. 122SN/A * As memory operations are issued to the IQ, they are also issued to this 132SN/A * unit, which then looks up the prediction as to what they are dependent 142SN/A * upon. This unit must be checked prior to a memory operation being able 152SN/A * to issue. Although this is templated, it's somewhat hard to make a generic 162SN/A * memory dependence unit. This one is mostly for store sets; it will be 172SN/A * quite limited in what other memory dependence predictions it can also 182SN/A * utilize. Thus this class should be most likely be rewritten for other 192SN/A * dependence prediction schemes. 202SN/A */ 212SN/Atemplate <class MemDepPred, class Impl> 222SN/Aclass MemDepUnit { 232SN/A public: 242SN/A typedef typename Impl::Params Params; 252SN/A typedef typename Impl::DynInstPtr DynInstPtr; 262SN/A 272665Ssaidi@eecs.umich.edu public: 282665Ssaidi@eecs.umich.edu typedef typename std::set<InstSeqNum>::iterator sn_it_t; 292665Ssaidi@eecs.umich.edu typedef typename std::map<InstSeqNum, vector<InstSeqNum> >::iterator 302SN/A dep_it_t; 312SN/A 328229Snate@binkert.org public: 332SN/A MemDepUnit(Params ¶ms); 342SN/A 352SN/A void insert(DynInstPtr &inst); 362SN/A 3756SN/A bool readyToIssue(DynInstPtr &inst); 384046Sbinkertn@umich.edu 394046Sbinkertn@umich.edu void issue(DynInstPtr &inst); 4056SN/A 412SN/A void wakeDependents(DynInstPtr &inst); 422SN/A 432SN/A void squash(const InstSeqNum &squashed_num); 442SN/A 458232Snate@binkert.org void violation(DynInstPtr &store_inst, DynInstPtr &violating_load); 462SN/A 474074Sbinkertn@umich.edu private: 482SN/A /** List of instructions that have passed through rename, yet are still 492SN/A * waiting on a memory dependence to resolve before they can issue. 502SN/A */ 512SN/A std::set<InstSeqNum> renamedInsts; 522SN/A 532SN/A /** List of instructions that have all their predicted memory dependences 542SN/A * resolved. They are ready in terms of being free of memory 55488SN/A * dependences; however they may still have to wait on source registers. 564046Sbinkertn@umich.edu */ 574046Sbinkertn@umich.edu std::set<InstSeqNum> readyInsts; 584046Sbinkertn@umich.edu 594046Sbinkertn@umich.edu std::map<InstSeqNum, vector<InstSeqNum> > dependencies; 604046Sbinkertn@umich.edu 614046Sbinkertn@umich.edu /** The memory dependence predictor. It is accessed upon new 624046Sbinkertn@umich.edu * instructions being added to the IQ, and responds by telling 634046Sbinkertn@umich.edu * this unit what instruction the newly added instruction is dependent 644046Sbinkertn@umich.edu * upon. 654046Sbinkertn@umich.edu */ 668640SAli.Saidi@ARM.com MemDepPred depPred; 678640SAli.Saidi@ARM.com 684046Sbinkertn@umich.edu}; 692SN/A 701031SN/A#endif 712SN/A