mem_dep_unit.hh revision 1061 
1
2#ifndef __MEM_DEP_UNIT_HH__
3#define __MEM_DEP_UNIT_HH__
4
5#include <set>
6#include <map>
7
8#include "cpu/inst_seq.hh"
9
10/**
11 * Memory dependency unit class.  This holds the memory dependence predictor.
12 * As memory operations are issued to the IQ, they are also issued to this
13 * unit, which then looks up the prediction as to what they are dependent
14 * upon.  This unit must be checked prior to a memory operation being able
15 * to issue.  Although this is templated, it's somewhat hard to make a generic
16 * memory dependence unit.  This one is mostly for store sets; it will be
17 * quite limited in what other memory dependence predictions it can also
18 * utilize.  Thus this class should be most likely be rewritten for other
19 * dependence prediction schemes.
20 */
21template <class MemDepPred, class Impl>
22class MemDepUnit {
23  public:
24    typedef typename Impl::Params Params;
25    typedef typename Impl::DynInstPtr DynInstPtr;
26
27  public:
28    typedef typename std::set<InstSeqNum>::iterator sn_it_t;
29    typedef typename std::map<InstSeqNum, vector<InstSeqNum> >::iterator
30    dep_it_t;
31
32  public:
33    MemDepUnit(Params &params);
34
35    void insert(DynInstPtr &inst);
36
37    bool readyToIssue(DynInstPtr &inst);
38
39    void issue(DynInstPtr &inst);
40
41    void wakeDependents(DynInstPtr &inst);
42
43    void squash(const InstSeqNum &squashed_num);
44
45    void violation(DynInstPtr &store_inst, DynInstPtr &violating_load);
46
47  private:
48    /** List of instructions that have passed through rename, yet are still
49     *  waiting on a memory dependence to resolve before they can issue.
50     */
51    std::set<InstSeqNum> renamedInsts;
52
53    /** List of instructions that have all their predicted memory dependences
54     *  resolved.  They are ready in terms of being free of memory
55     *  dependences; however they may still have to wait on source registers.
56     */
57    std::set<InstSeqNum> readyInsts;
58
59    std::map<InstSeqNum, vector<InstSeqNum> > dependencies;
60
61    /** The memory dependence predictor.  It is accessed upon new
62     *  instructions being added to the IQ, and responds by telling
63     *  this unit what instruction the newly added instruction is dependent
64     *  upon.
65     */
66    MemDepPred depPred;
67
68};
69
70#endif
71