lsq_unit_impl.hh revision 7823:dac01f14f20f
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Korey Sewell 42 */ 43 44#include "arch/locked_mem.hh" 45#include "config/the_isa.hh" 46#include "config/use_checker.hh" 47#include "cpu/o3/lsq.hh" 48#include "cpu/o3/lsq_unit.hh" 49#include "base/str.hh" 50#include "mem/packet.hh" 51#include "mem/request.hh" 52 53#if USE_CHECKER 54#include "cpu/checker/cpu.hh" 55#endif 56 57template<class Impl> 58LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 59 LSQUnit *lsq_ptr) 60 : inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 61{ 62 this->setFlags(Event::AutoDelete); 63} 64 65template<class Impl> 66void 67LSQUnit<Impl>::WritebackEvent::process() 68{ 69 if (!lsqPtr->isSwitchedOut()) { 70 lsqPtr->writeback(inst, pkt); 71 } 72 73 if (pkt->senderState) 74 delete pkt->senderState; 75 76 delete pkt->req; 77 delete pkt; 78} 79 80template<class Impl> 81const char * 82LSQUnit<Impl>::WritebackEvent::description() const 83{ 84 return "Store writeback"; 85} 86 87template<class Impl> 88void 89LSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 90{ 91 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 92 DynInstPtr inst = state->inst; 93 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum); 94 DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum); 95 96 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 97 98 assert(!pkt->wasNacked()); 99 100 // If this is a split access, wait until all packets are received. 101 if (TheISA::HasUnalignedMemAcc && !state->complete()) { 102 delete pkt->req; 103 delete pkt; 104 return; 105 } 106 107 if (isSwitchedOut() || inst->isSquashed()) { 108 iewStage->decrWb(inst->seqNum); 109 } else { 110 if (!state->noWB) { 111 if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 112 !state->isLoad) { 113 writeback(inst, pkt); 114 } else { 115 writeback(inst, state->mainPkt); 116 } 117 } 118 119 if (inst->isStore()) { 120 completeStore(state->idx); 121 } 122 } 123 124 if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 125 delete state->mainPkt->req; 126 delete state->mainPkt; 127 } 128 delete state; 129 delete pkt->req; 130 delete pkt; 131} 132 133template <class Impl> 134LSQUnit<Impl>::LSQUnit() 135 : loads(0), stores(0), storesToWB(0), stalled(false), 136 isStoreBlocked(false), isLoadBlocked(false), 137 loadBlockedHandled(false), hasPendingPkt(false) 138{ 139} 140 141template<class Impl> 142void 143LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 144 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 145 unsigned id) 146{ 147 cpu = cpu_ptr; 148 iewStage = iew_ptr; 149 150 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 151 152 switchedOut = false; 153 154 lsq = lsq_ptr; 155 156 lsqID = id; 157 158 // Add 1 for the sentinel entry (they are circular queues). 159 LQEntries = maxLQEntries + 1; 160 SQEntries = maxSQEntries + 1; 161 162 loadQueue.resize(LQEntries); 163 storeQueue.resize(SQEntries); 164 165 loadHead = loadTail = 0; 166 167 storeHead = storeWBIdx = storeTail = 0; 168 169 usedPorts = 0; 170 cachePorts = params->cachePorts; 171 172 retryPkt = NULL; 173 memDepViolator = NULL; 174 175 blockedLoadSeqNum = 0; 176} 177 178template<class Impl> 179std::string 180LSQUnit<Impl>::name() const 181{ 182 if (Impl::MaxThreads == 1) { 183 return iewStage->name() + ".lsq"; 184 } else { 185 return iewStage->name() + ".lsq.thread." + to_string(lsqID); 186 } 187} 188 189template<class Impl> 190void 191LSQUnit<Impl>::regStats() 192{ 193 lsqForwLoads 194 .name(name() + ".forwLoads") 195 .desc("Number of loads that had data forwarded from stores"); 196 197 invAddrLoads 198 .name(name() + ".invAddrLoads") 199 .desc("Number of loads ignored due to an invalid address"); 200 201 lsqSquashedLoads 202 .name(name() + ".squashedLoads") 203 .desc("Number of loads squashed"); 204 205 lsqIgnoredResponses 206 .name(name() + ".ignoredResponses") 207 .desc("Number of memory responses ignored because the instruction is squashed"); 208 209 lsqMemOrderViolation 210 .name(name() + ".memOrderViolation") 211 .desc("Number of memory ordering violations"); 212 213 lsqSquashedStores 214 .name(name() + ".squashedStores") 215 .desc("Number of stores squashed"); 216 217 invAddrSwpfs 218 .name(name() + ".invAddrSwpfs") 219 .desc("Number of software prefetches ignored due to an invalid address"); 220 221 lsqBlockedLoads 222 .name(name() + ".blockedLoads") 223 .desc("Number of blocked loads due to partial load-store forwarding"); 224 225 lsqRescheduledLoads 226 .name(name() + ".rescheduledLoads") 227 .desc("Number of loads that were rescheduled"); 228 229 lsqCacheBlocked 230 .name(name() + ".cacheBlocked") 231 .desc("Number of times an access to memory failed due to the cache being blocked"); 232} 233 234template<class Impl> 235void 236LSQUnit<Impl>::setDcachePort(Port *dcache_port) 237{ 238 dcachePort = dcache_port; 239 240#if USE_CHECKER 241 if (cpu->checker) { 242 cpu->checker->setDcachePort(dcachePort); 243 } 244#endif 245} 246 247template<class Impl> 248void 249LSQUnit<Impl>::clearLQ() 250{ 251 loadQueue.clear(); 252} 253 254template<class Impl> 255void 256LSQUnit<Impl>::clearSQ() 257{ 258 storeQueue.clear(); 259} 260 261template<class Impl> 262void 263LSQUnit<Impl>::switchOut() 264{ 265 switchedOut = true; 266 for (int i = 0; i < loadQueue.size(); ++i) { 267 assert(!loadQueue[i]); 268 loadQueue[i] = NULL; 269 } 270 271 assert(storesToWB == 0); 272} 273 274template<class Impl> 275void 276LSQUnit<Impl>::takeOverFrom() 277{ 278 switchedOut = false; 279 loads = stores = storesToWB = 0; 280 281 loadHead = loadTail = 0; 282 283 storeHead = storeWBIdx = storeTail = 0; 284 285 usedPorts = 0; 286 287 memDepViolator = NULL; 288 289 blockedLoadSeqNum = 0; 290 291 stalled = false; 292 isLoadBlocked = false; 293 loadBlockedHandled = false; 294} 295 296template<class Impl> 297void 298LSQUnit<Impl>::resizeLQ(unsigned size) 299{ 300 unsigned size_plus_sentinel = size + 1; 301 assert(size_plus_sentinel >= LQEntries); 302 303 if (size_plus_sentinel > LQEntries) { 304 while (size_plus_sentinel > loadQueue.size()) { 305 DynInstPtr dummy; 306 loadQueue.push_back(dummy); 307 LQEntries++; 308 } 309 } else { 310 LQEntries = size_plus_sentinel; 311 } 312 313} 314 315template<class Impl> 316void 317LSQUnit<Impl>::resizeSQ(unsigned size) 318{ 319 unsigned size_plus_sentinel = size + 1; 320 if (size_plus_sentinel > SQEntries) { 321 while (size_plus_sentinel > storeQueue.size()) { 322 SQEntry dummy; 323 storeQueue.push_back(dummy); 324 SQEntries++; 325 } 326 } else { 327 SQEntries = size_plus_sentinel; 328 } 329} 330 331template <class Impl> 332void 333LSQUnit<Impl>::insert(DynInstPtr &inst) 334{ 335 assert(inst->isMemRef()); 336 337 assert(inst->isLoad() || inst->isStore()); 338 339 if (inst->isLoad()) { 340 insertLoad(inst); 341 } else { 342 insertStore(inst); 343 } 344 345 inst->setInLSQ(); 346} 347 348template <class Impl> 349void 350LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 351{ 352 assert((loadTail + 1) % LQEntries != loadHead); 353 assert(loads < LQEntries); 354 355 DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 356 load_inst->pcState(), loadTail, load_inst->seqNum); 357 358 load_inst->lqIdx = loadTail; 359 360 if (stores == 0) { 361 load_inst->sqIdx = -1; 362 } else { 363 load_inst->sqIdx = storeTail; 364 } 365 366 loadQueue[loadTail] = load_inst; 367 368 incrLdIdx(loadTail); 369 370 ++loads; 371} 372 373template <class Impl> 374void 375LSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 376{ 377 // Make sure it is not full before inserting an instruction. 378 assert((storeTail + 1) % SQEntries != storeHead); 379 assert(stores < SQEntries); 380 381 DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 382 store_inst->pcState(), storeTail, store_inst->seqNum); 383 384 store_inst->sqIdx = storeTail; 385 store_inst->lqIdx = loadTail; 386 387 storeQueue[storeTail] = SQEntry(store_inst); 388 389 incrStIdx(storeTail); 390 391 ++stores; 392} 393 394template <class Impl> 395typename Impl::DynInstPtr 396LSQUnit<Impl>::getMemDepViolator() 397{ 398 DynInstPtr temp = memDepViolator; 399 400 memDepViolator = NULL; 401 402 return temp; 403} 404 405template <class Impl> 406unsigned 407LSQUnit<Impl>::numFreeEntries() 408{ 409 unsigned free_lq_entries = LQEntries - loads; 410 unsigned free_sq_entries = SQEntries - stores; 411 412 // Both the LQ and SQ entries have an extra dummy entry to differentiate 413 // empty/full conditions. Subtract 1 from the free entries. 414 if (free_lq_entries < free_sq_entries) { 415 return free_lq_entries - 1; 416 } else { 417 return free_sq_entries - 1; 418 } 419} 420 421template <class Impl> 422int 423LSQUnit<Impl>::numLoadsReady() 424{ 425 int load_idx = loadHead; 426 int retval = 0; 427 428 while (load_idx != loadTail) { 429 assert(loadQueue[load_idx]); 430 431 if (loadQueue[load_idx]->readyToIssue()) { 432 ++retval; 433 } 434 } 435 436 return retval; 437} 438 439template <class Impl> 440Fault 441LSQUnit<Impl>::executeLoad(DynInstPtr &inst) 442{ 443 using namespace TheISA; 444 // Execute a specific load. 445 Fault load_fault = NoFault; 446 447 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 448 inst->pcState(),inst->seqNum); 449 450 assert(!inst->isSquashed()); 451 452 load_fault = inst->initiateAcc(); 453 454 // If the instruction faulted or predicated false, then we need to send it 455 // along to commit without the instruction completing. 456 if (load_fault != NoFault || inst->readPredicate() == false) { 457 // Send this instruction to commit, also make sure iew stage 458 // realizes there is activity. 459 // Mark it as executed unless it is an uncached load that 460 // needs to hit the head of commit. 461 DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 462 inst->seqNum, 463 (load_fault != NoFault ? "fault" : "predication")); 464 if (!(inst->hasRequest() && inst->uncacheable()) || 465 inst->isAtCommit()) { 466 inst->setExecuted(); 467 } 468 iewStage->instToCommit(inst); 469 iewStage->activityThisCycle(); 470 } else if (!loadBlocked()) { 471 assert(inst->effAddrValid); 472 int load_idx = inst->lqIdx; 473 incrLdIdx(load_idx); 474 while (load_idx != loadTail) { 475 // Really only need to check loads that have actually executed 476 477 // @todo: For now this is extra conservative, detecting a 478 // violation if the addresses match assuming all accesses 479 // are quad word accesses. 480 481 // @todo: Fix this, magic number being used here 482 483 // @todo: Uncachable load is not executed until it reaches 484 // the head of the ROB. Once this if checks only the executed 485 // loads(as noted above), this check can be removed 486 if (loadQueue[load_idx]->effAddrValid && 487 ((loadQueue[load_idx]->effAddr >> 8) 488 == (inst->effAddr >> 8)) && 489 !loadQueue[load_idx]->uncacheable()) { 490 // A load incorrectly passed this load. Squash and refetch. 491 // For now return a fault to show that it was unsuccessful. 492 DynInstPtr violator = loadQueue[load_idx]; 493 if (!memDepViolator || 494 (violator->seqNum < memDepViolator->seqNum)) { 495 memDepViolator = violator; 496 } else { 497 break; 498 } 499 500 ++lsqMemOrderViolation; 501 502 return genMachineCheckFault(); 503 } 504 505 incrLdIdx(load_idx); 506 } 507 } 508 509 return load_fault; 510} 511 512template <class Impl> 513Fault 514LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 515{ 516 using namespace TheISA; 517 // Make sure that a store exists. 518 assert(stores != 0); 519 520 int store_idx = store_inst->sqIdx; 521 522 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 523 store_inst->pcState(), store_inst->seqNum); 524 525 assert(!store_inst->isSquashed()); 526 527 // Check the recently completed loads to see if any match this store's 528 // address. If so, then we have a memory ordering violation. 529 int load_idx = store_inst->lqIdx; 530 531 Fault store_fault = store_inst->initiateAcc(); 532 533 if (storeQueue[store_idx].size == 0) { 534 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 535 store_inst->pcState(), store_inst->seqNum); 536 537 return store_fault; 538 } else if (store_inst->readPredicate() == false) { 539 DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 540 store_inst->seqNum); 541 return store_fault; 542 } 543 544 assert(store_fault == NoFault); 545 546 if (store_inst->isStoreConditional()) { 547 // Store conditionals need to set themselves as able to 548 // writeback if we haven't had a fault by here. 549 storeQueue[store_idx].canWB = true; 550 551 ++storesToWB; 552 } 553 554 assert(store_inst->effAddrValid); 555 while (load_idx != loadTail) { 556 // Really only need to check loads that have actually executed 557 // It's safe to check all loads because effAddr is set to 558 // InvalAddr when the dyn inst is created. 559 560 // @todo: For now this is extra conservative, detecting a 561 // violation if the addresses match assuming all accesses 562 // are quad word accesses. 563 564 // @todo: Fix this, magic number being used here 565 566 // @todo: Uncachable load is not executed until it reaches 567 // the head of the ROB. Once this if checks only the executed 568 // loads(as noted above), this check can be removed 569 if (loadQueue[load_idx]->effAddrValid && 570 ((loadQueue[load_idx]->effAddr >> 8) 571 == (store_inst->effAddr >> 8)) && 572 !loadQueue[load_idx]->uncacheable()) { 573 // A load incorrectly passed this store. Squash and refetch. 574 // For now return a fault to show that it was unsuccessful. 575 DynInstPtr violator = loadQueue[load_idx]; 576 if (!memDepViolator || 577 (violator->seqNum < memDepViolator->seqNum)) { 578 memDepViolator = violator; 579 } else { 580 break; 581 } 582 583 ++lsqMemOrderViolation; 584 585 return genMachineCheckFault(); 586 } 587 588 incrLdIdx(load_idx); 589 } 590 591 return store_fault; 592} 593 594template <class Impl> 595void 596LSQUnit<Impl>::commitLoad() 597{ 598 assert(loadQueue[loadHead]); 599 600 DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 601 loadQueue[loadHead]->pcState()); 602 603 loadQueue[loadHead] = NULL; 604 605 incrLdIdx(loadHead); 606 607 --loads; 608} 609 610template <class Impl> 611void 612LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 613{ 614 assert(loads == 0 || loadQueue[loadHead]); 615 616 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 617 commitLoad(); 618 } 619} 620 621template <class Impl> 622void 623LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 624{ 625 assert(stores == 0 || storeQueue[storeHead].inst); 626 627 int store_idx = storeHead; 628 629 while (store_idx != storeTail) { 630 assert(storeQueue[store_idx].inst); 631 // Mark any stores that are now committed and have not yet 632 // been marked as able to write back. 633 if (!storeQueue[store_idx].canWB) { 634 if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 635 break; 636 } 637 DPRINTF(LSQUnit, "Marking store as able to write back, PC " 638 "%s [sn:%lli]\n", 639 storeQueue[store_idx].inst->pcState(), 640 storeQueue[store_idx].inst->seqNum); 641 642 storeQueue[store_idx].canWB = true; 643 644 ++storesToWB; 645 } 646 647 incrStIdx(store_idx); 648 } 649} 650 651template <class Impl> 652void 653LSQUnit<Impl>::writebackPendingStore() 654{ 655 if (hasPendingPkt) { 656 assert(pendingPkt != NULL); 657 658 // If the cache is blocked, this will store the packet for retry. 659 if (sendStore(pendingPkt)) { 660 storePostSend(pendingPkt); 661 } 662 pendingPkt = NULL; 663 hasPendingPkt = false; 664 } 665} 666 667template <class Impl> 668void 669LSQUnit<Impl>::writebackStores() 670{ 671 // First writeback the second packet from any split store that didn't 672 // complete last cycle because there weren't enough cache ports available. 673 if (TheISA::HasUnalignedMemAcc) { 674 writebackPendingStore(); 675 } 676 677 while (storesToWB > 0 && 678 storeWBIdx != storeTail && 679 storeQueue[storeWBIdx].inst && 680 storeQueue[storeWBIdx].canWB && 681 usedPorts < cachePorts) { 682 683 if (isStoreBlocked || lsq->cacheBlocked()) { 684 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 685 " is blocked!\n"); 686 break; 687 } 688 689 // Store didn't write any data so no need to write it back to 690 // memory. 691 if (storeQueue[storeWBIdx].size == 0) { 692 completeStore(storeWBIdx); 693 694 incrStIdx(storeWBIdx); 695 696 continue; 697 } 698 699 ++usedPorts; 700 701 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 702 incrStIdx(storeWBIdx); 703 704 continue; 705 } 706 707 assert(storeQueue[storeWBIdx].req); 708 assert(!storeQueue[storeWBIdx].committed); 709 710 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 711 assert(storeQueue[storeWBIdx].sreqLow); 712 assert(storeQueue[storeWBIdx].sreqHigh); 713 } 714 715 DynInstPtr inst = storeQueue[storeWBIdx].inst; 716 717 Request *req = storeQueue[storeWBIdx].req; 718 storeQueue[storeWBIdx].committed = true; 719 720 assert(!inst->memData); 721 inst->memData = new uint8_t[64]; 722 723 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 724 725 MemCmd command = 726 req->isSwap() ? MemCmd::SwapReq : 727 (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 728 PacketPtr data_pkt; 729 PacketPtr snd_data_pkt = NULL; 730 731 LSQSenderState *state = new LSQSenderState; 732 state->isLoad = false; 733 state->idx = storeWBIdx; 734 state->inst = inst; 735 736 if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 737 738 // Build a single data packet if the store isn't split. 739 data_pkt = new Packet(req, command, Packet::Broadcast); 740 data_pkt->dataStatic(inst->memData); 741 data_pkt->senderState = state; 742 } else { 743 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 744 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 745 746 // Create two packets if the store is split in two. 747 data_pkt = new Packet(sreqLow, command, Packet::Broadcast); 748 snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast); 749 750 data_pkt->dataStatic(inst->memData); 751 snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 752 753 data_pkt->senderState = state; 754 snd_data_pkt->senderState = state; 755 756 state->isSplit = true; 757 state->outstanding = 2; 758 759 // Can delete the main request now. 760 delete req; 761 req = sreqLow; 762 } 763 764 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 765 "to Addr:%#x, data:%#x [sn:%lli]\n", 766 storeWBIdx, inst->pcState(), 767 req->getPaddr(), (int)*(inst->memData), 768 inst->seqNum); 769 770 // @todo: Remove this SC hack once the memory system handles it. 771 if (inst->isStoreConditional()) { 772 assert(!storeQueue[storeWBIdx].isSplit); 773 // Disable recording the result temporarily. Writing to 774 // misc regs normally updates the result, but this is not 775 // the desired behavior when handling store conditionals. 776 inst->recordResult = false; 777 bool success = TheISA::handleLockedWrite(inst.get(), req); 778 inst->recordResult = true; 779 780 if (!success) { 781 // Instantly complete this store. 782 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 783 "Instantly completing it.\n", 784 inst->seqNum); 785 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 786 cpu->schedule(wb, curTick() + 1); 787 completeStore(storeWBIdx); 788 incrStIdx(storeWBIdx); 789 continue; 790 } 791 } else { 792 // Non-store conditionals do not need a writeback. 793 state->noWB = true; 794 } 795 796 if (!sendStore(data_pkt)) { 797 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 798 "retry later\n", 799 inst->seqNum); 800 801 // Need to store the second packet, if split. 802 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 803 state->pktToSend = true; 804 state->pendingPacket = snd_data_pkt; 805 } 806 } else { 807 808 // If split, try to send the second packet too 809 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 810 assert(snd_data_pkt); 811 812 // Ensure there are enough ports to use. 813 if (usedPorts < cachePorts) { 814 ++usedPorts; 815 if (sendStore(snd_data_pkt)) { 816 storePostSend(snd_data_pkt); 817 } else { 818 DPRINTF(IEW, "D-Cache became blocked when writing" 819 " [sn:%lli] second packet, will retry later\n", 820 inst->seqNum); 821 } 822 } else { 823 824 // Store the packet for when there's free ports. 825 assert(pendingPkt == NULL); 826 pendingPkt = snd_data_pkt; 827 hasPendingPkt = true; 828 } 829 } else { 830 831 // Not a split store. 832 storePostSend(data_pkt); 833 } 834 } 835 } 836 837 // Not sure this should set it to 0. 838 usedPorts = 0; 839 840 assert(stores >= 0 && storesToWB >= 0); 841} 842 843/*template <class Impl> 844void 845LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 846{ 847 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 848 mshrSeqNums.end(), 849 seqNum); 850 851 if (mshr_it != mshrSeqNums.end()) { 852 mshrSeqNums.erase(mshr_it); 853 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 854 } 855}*/ 856 857template <class Impl> 858void 859LSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 860{ 861 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 862 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 863 864 int load_idx = loadTail; 865 decrLdIdx(load_idx); 866 867 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 868 DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 869 "[sn:%lli]\n", 870 loadQueue[load_idx]->pcState(), 871 loadQueue[load_idx]->seqNum); 872 873 if (isStalled() && load_idx == stallingLoadIdx) { 874 stalled = false; 875 stallingStoreIsn = 0; 876 stallingLoadIdx = 0; 877 } 878 879 // Clear the smart pointer to make sure it is decremented. 880 loadQueue[load_idx]->setSquashed(); 881 loadQueue[load_idx] = NULL; 882 --loads; 883 884 // Inefficient! 885 loadTail = load_idx; 886 887 decrLdIdx(load_idx); 888 ++lsqSquashedLoads; 889 } 890 891 if (isLoadBlocked) { 892 if (squashed_num < blockedLoadSeqNum) { 893 isLoadBlocked = false; 894 loadBlockedHandled = false; 895 blockedLoadSeqNum = 0; 896 } 897 } 898 899 if (memDepViolator && squashed_num < memDepViolator->seqNum) { 900 memDepViolator = NULL; 901 } 902 903 int store_idx = storeTail; 904 decrStIdx(store_idx); 905 906 while (stores != 0 && 907 storeQueue[store_idx].inst->seqNum > squashed_num) { 908 // Instructions marked as can WB are already committed. 909 if (storeQueue[store_idx].canWB) { 910 break; 911 } 912 913 DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 914 "idx:%i [sn:%lli]\n", 915 storeQueue[store_idx].inst->pcState(), 916 store_idx, storeQueue[store_idx].inst->seqNum); 917 918 // I don't think this can happen. It should have been cleared 919 // by the stalling load. 920 if (isStalled() && 921 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 922 panic("Is stalled should have been cleared by stalling load!\n"); 923 stalled = false; 924 stallingStoreIsn = 0; 925 } 926 927 // Clear the smart pointer to make sure it is decremented. 928 storeQueue[store_idx].inst->setSquashed(); 929 storeQueue[store_idx].inst = NULL; 930 storeQueue[store_idx].canWB = 0; 931 932 // Must delete request now that it wasn't handed off to 933 // memory. This is quite ugly. @todo: Figure out the proper 934 // place to really handle request deletes. 935 delete storeQueue[store_idx].req; 936 if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 937 delete storeQueue[store_idx].sreqLow; 938 delete storeQueue[store_idx].sreqHigh; 939 940 storeQueue[store_idx].sreqLow = NULL; 941 storeQueue[store_idx].sreqHigh = NULL; 942 } 943 944 storeQueue[store_idx].req = NULL; 945 --stores; 946 947 // Inefficient! 948 storeTail = store_idx; 949 950 decrStIdx(store_idx); 951 ++lsqSquashedStores; 952 } 953} 954 955template <class Impl> 956void 957LSQUnit<Impl>::storePostSend(PacketPtr pkt) 958{ 959 if (isStalled() && 960 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 961 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 962 "load idx:%i\n", 963 stallingStoreIsn, stallingLoadIdx); 964 stalled = false; 965 stallingStoreIsn = 0; 966 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 967 } 968 969 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 970 // The store is basically completed at this time. This 971 // only works so long as the checker doesn't try to 972 // verify the value in memory for stores. 973 storeQueue[storeWBIdx].inst->setCompleted(); 974#if USE_CHECKER 975 if (cpu->checker) { 976 cpu->checker->verify(storeQueue[storeWBIdx].inst); 977 } 978#endif 979 } 980 981 incrStIdx(storeWBIdx); 982} 983 984template <class Impl> 985void 986LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 987{ 988 iewStage->wakeCPU(); 989 990 // Squashed instructions do not need to complete their access. 991 if (inst->isSquashed()) { 992 iewStage->decrWb(inst->seqNum); 993 assert(!inst->isStore()); 994 ++lsqIgnoredResponses; 995 return; 996 } 997 998 if (!inst->isExecuted()) { 999 inst->setExecuted(); 1000 1001 // Complete access to copy data to proper place. 1002 inst->completeAcc(pkt); 1003 } 1004 1005 // Need to insert instruction into queue to commit 1006 iewStage->instToCommit(inst); 1007 1008 iewStage->activityThisCycle(); 1009 1010 // see if this load changed the PC 1011 iewStage->checkMisprediction(inst); 1012} 1013 1014template <class Impl> 1015void 1016LSQUnit<Impl>::completeStore(int store_idx) 1017{ 1018 assert(storeQueue[store_idx].inst); 1019 storeQueue[store_idx].completed = true; 1020 --storesToWB; 1021 // A bit conservative because a store completion may not free up entries, 1022 // but hopefully avoids two store completions in one cycle from making 1023 // the CPU tick twice. 1024 cpu->wakeCPU(); 1025 cpu->activityThisCycle(); 1026 1027 if (store_idx == storeHead) { 1028 do { 1029 incrStIdx(storeHead); 1030 1031 --stores; 1032 } while (storeQueue[storeHead].completed && 1033 storeHead != storeTail); 1034 1035 iewStage->updateLSQNextCycle = true; 1036 } 1037 1038 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 1039 "idx:%i\n", 1040 storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 1041 1042 if (isStalled() && 1043 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 1044 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 1045 "load idx:%i\n", 1046 stallingStoreIsn, stallingLoadIdx); 1047 stalled = false; 1048 stallingStoreIsn = 0; 1049 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 1050 } 1051 1052 storeQueue[store_idx].inst->setCompleted(); 1053 1054 // Tell the checker we've completed this instruction. Some stores 1055 // may get reported twice to the checker, but the checker can 1056 // handle that case. 1057#if USE_CHECKER 1058 if (cpu->checker) { 1059 cpu->checker->verify(storeQueue[store_idx].inst); 1060 } 1061#endif 1062} 1063 1064template <class Impl> 1065bool 1066LSQUnit<Impl>::sendStore(PacketPtr data_pkt) 1067{ 1068 if (!dcachePort->sendTiming(data_pkt)) { 1069 // Need to handle becoming blocked on a store. 1070 isStoreBlocked = true; 1071 ++lsqCacheBlocked; 1072 assert(retryPkt == NULL); 1073 retryPkt = data_pkt; 1074 lsq->setRetryTid(lsqID); 1075 return false; 1076 } 1077 return true; 1078} 1079 1080template <class Impl> 1081void 1082LSQUnit<Impl>::recvRetry() 1083{ 1084 if (isStoreBlocked) { 1085 DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 1086 assert(retryPkt != NULL); 1087 1088 if (dcachePort->sendTiming(retryPkt)) { 1089 LSQSenderState *state = 1090 dynamic_cast<LSQSenderState *>(retryPkt->senderState); 1091 1092 // Don't finish the store unless this is the last packet. 1093 if (!TheISA::HasUnalignedMemAcc || !state->pktToSend) { 1094 storePostSend(retryPkt); 1095 } 1096 retryPkt = NULL; 1097 isStoreBlocked = false; 1098 lsq->setRetryTid(InvalidThreadID); 1099 1100 // Send any outstanding packet. 1101 if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 1102 assert(state->pendingPacket); 1103 if (sendStore(state->pendingPacket)) { 1104 storePostSend(state->pendingPacket); 1105 } 1106 } 1107 } else { 1108 // Still blocked! 1109 ++lsqCacheBlocked; 1110 lsq->setRetryTid(lsqID); 1111 } 1112 } else if (isLoadBlocked) { 1113 DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 1114 "no need to resend packet.\n"); 1115 } else { 1116 DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 1117 } 1118} 1119 1120template <class Impl> 1121inline void 1122LSQUnit<Impl>::incrStIdx(int &store_idx) 1123{ 1124 if (++store_idx >= SQEntries) 1125 store_idx = 0; 1126} 1127 1128template <class Impl> 1129inline void 1130LSQUnit<Impl>::decrStIdx(int &store_idx) 1131{ 1132 if (--store_idx < 0) 1133 store_idx += SQEntries; 1134} 1135 1136template <class Impl> 1137inline void 1138LSQUnit<Impl>::incrLdIdx(int &load_idx) 1139{ 1140 if (++load_idx >= LQEntries) 1141 load_idx = 0; 1142} 1143 1144template <class Impl> 1145inline void 1146LSQUnit<Impl>::decrLdIdx(int &load_idx) 1147{ 1148 if (--load_idx < 0) 1149 load_idx += LQEntries; 1150} 1151 1152template <class Impl> 1153void 1154LSQUnit<Impl>::dumpInsts() 1155{ 1156 cprintf("Load store queue: Dumping instructions.\n"); 1157 cprintf("Load queue size: %i\n", loads); 1158 cprintf("Load queue: "); 1159 1160 int load_idx = loadHead; 1161 1162 while (load_idx != loadTail && loadQueue[load_idx]) { 1163 cprintf("%s ", loadQueue[load_idx]->pcState()); 1164 1165 incrLdIdx(load_idx); 1166 } 1167 1168 cprintf("Store queue size: %i\n", stores); 1169 cprintf("Store queue: "); 1170 1171 int store_idx = storeHead; 1172 1173 while (store_idx != storeTail && storeQueue[store_idx].inst) { 1174 cprintf("%s ", storeQueue[store_idx].inst->pcState()); 1175 1176 incrStIdx(store_idx); 1177 } 1178 1179 cprintf("\n"); 1180} 1181