lsq_unit_impl.hh revision 7720:65d338a8dba4
16691Stjones1@inf.ed.ac.uk/*
26691Stjones1@inf.ed.ac.uk * Copyright (c) 2010 ARM Limited
36691Stjones1@inf.ed.ac.uk * All rights reserved
46691Stjones1@inf.ed.ac.uk *
56691Stjones1@inf.ed.ac.uk * The license below extends only to copyright in the software and shall
66691Stjones1@inf.ed.ac.uk * not be construed as granting a license to any other intellectual
76691Stjones1@inf.ed.ac.uk * property including but not limited to intellectual property relating
86691Stjones1@inf.ed.ac.uk * to a hardware implementation of the functionality of the software
96691Stjones1@inf.ed.ac.uk * licensed hereunder.  You may use the software subject to the license
106691Stjones1@inf.ed.ac.uk * terms below provided that you ensure that this notice is replicated
116691Stjones1@inf.ed.ac.uk * unmodified and in its entirety in all distributions of the software,
126691Stjones1@inf.ed.ac.uk * modified or unmodified, in source code or in binary form.
136691Stjones1@inf.ed.ac.uk *
146691Stjones1@inf.ed.ac.uk * Copyright (c) 2004-2005 The Regents of The University of Michigan
156691Stjones1@inf.ed.ac.uk * All rights reserved.
166691Stjones1@inf.ed.ac.uk *
176691Stjones1@inf.ed.ac.uk * Redistribution and use in source and binary forms, with or without
186691Stjones1@inf.ed.ac.uk * modification, are permitted provided that the following conditions are
196691Stjones1@inf.ed.ac.uk * met: redistributions of source code must retain the above copyright
206691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer;
216691Stjones1@inf.ed.ac.uk * redistributions in binary form must reproduce the above copyright
226691Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer in the
236691Stjones1@inf.ed.ac.uk * documentation and/or other materials provided with the distribution;
246691Stjones1@inf.ed.ac.uk * neither the name of the copyright holders nor the names of its
256691Stjones1@inf.ed.ac.uk * contributors may be used to endorse or promote products derived from
266691Stjones1@inf.ed.ac.uk * this software without specific prior written permission.
276691Stjones1@inf.ed.ac.uk *
286691Stjones1@inf.ed.ac.uk * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
296691Stjones1@inf.ed.ac.uk * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
306691Stjones1@inf.ed.ac.uk * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
316691Stjones1@inf.ed.ac.uk * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
326691Stjones1@inf.ed.ac.uk * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
336691Stjones1@inf.ed.ac.uk * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
346691Stjones1@inf.ed.ac.uk * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
356691Stjones1@inf.ed.ac.uk * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
366691Stjones1@inf.ed.ac.uk * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
376691Stjones1@inf.ed.ac.uk * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
386691Stjones1@inf.ed.ac.uk * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
396691Stjones1@inf.ed.ac.uk *
406691Stjones1@inf.ed.ac.uk * Authors: Kevin Lim
416691Stjones1@inf.ed.ac.uk *          Korey Sewell
426691Stjones1@inf.ed.ac.uk */
436691Stjones1@inf.ed.ac.uk
446691Stjones1@inf.ed.ac.uk#include "arch/locked_mem.hh"
456691Stjones1@inf.ed.ac.uk#include "config/the_isa.hh"
466691Stjones1@inf.ed.ac.uk#include "config/use_checker.hh"
476691Stjones1@inf.ed.ac.uk#include "cpu/o3/lsq.hh"
486691Stjones1@inf.ed.ac.uk#include "cpu/o3/lsq_unit.hh"
496691Stjones1@inf.ed.ac.uk#include "base/str.hh"
506691Stjones1@inf.ed.ac.uk#include "mem/packet.hh"
516691Stjones1@inf.ed.ac.uk#include "mem/request.hh"
526691Stjones1@inf.ed.ac.uk
536691Stjones1@inf.ed.ac.uk#if USE_CHECKER
546691Stjones1@inf.ed.ac.uk#include "cpu/checker/cpu.hh"
556691Stjones1@inf.ed.ac.uk#endif
566691Stjones1@inf.ed.ac.uk
576691Stjones1@inf.ed.ac.uktemplate<class Impl>
586691Stjones1@inf.ed.ac.ukLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
596691Stjones1@inf.ed.ac.uk                                              LSQUnit *lsq_ptr)
606691Stjones1@inf.ed.ac.uk    : inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
616691Stjones1@inf.ed.ac.uk{
626691Stjones1@inf.ed.ac.uk    this->setFlags(Event::AutoDelete);
636691Stjones1@inf.ed.ac.uk}
646691Stjones1@inf.ed.ac.uk
656691Stjones1@inf.ed.ac.uktemplate<class Impl>
666691Stjones1@inf.ed.ac.ukvoid
676691Stjones1@inf.ed.ac.ukLSQUnit<Impl>::WritebackEvent::process()
686691Stjones1@inf.ed.ac.uk{
696691Stjones1@inf.ed.ac.uk    if (!lsqPtr->isSwitchedOut()) {
706691Stjones1@inf.ed.ac.uk        lsqPtr->writeback(inst, pkt);
716691Stjones1@inf.ed.ac.uk    }
726691Stjones1@inf.ed.ac.uk
736691Stjones1@inf.ed.ac.uk    if (pkt->senderState)
746691Stjones1@inf.ed.ac.uk        delete pkt->senderState;
756691Stjones1@inf.ed.ac.uk
766691Stjones1@inf.ed.ac.uk    delete pkt->req;
776691Stjones1@inf.ed.ac.uk    delete pkt;
786691Stjones1@inf.ed.ac.uk}
796691Stjones1@inf.ed.ac.uk
806691Stjones1@inf.ed.ac.uktemplate<class Impl>
816691Stjones1@inf.ed.ac.ukconst char *
826691Stjones1@inf.ed.ac.ukLSQUnit<Impl>::WritebackEvent::description() const
836691Stjones1@inf.ed.ac.uk{
846691Stjones1@inf.ed.ac.uk    return "Store writeback";
856691Stjones1@inf.ed.ac.uk}
866691Stjones1@inf.ed.ac.uk
876691Stjones1@inf.ed.ac.uktemplate<class Impl>
886691Stjones1@inf.ed.ac.ukvoid
896691Stjones1@inf.ed.ac.ukLSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
906691Stjones1@inf.ed.ac.uk{
916691Stjones1@inf.ed.ac.uk    LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
926691Stjones1@inf.ed.ac.uk    DynInstPtr inst = state->inst;
936691Stjones1@inf.ed.ac.uk    DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
946691Stjones1@inf.ed.ac.uk    DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
956691Stjones1@inf.ed.ac.uk
966691Stjones1@inf.ed.ac.uk    //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
976691Stjones1@inf.ed.ac.uk
986691Stjones1@inf.ed.ac.uk    assert(!pkt->wasNacked());
996691Stjones1@inf.ed.ac.uk
1006691Stjones1@inf.ed.ac.uk    // If this is a split access, wait until all packets are received.
1016691Stjones1@inf.ed.ac.uk    if (TheISA::HasUnalignedMemAcc && !state->complete()) {
1026691Stjones1@inf.ed.ac.uk        delete pkt->req;
1036691Stjones1@inf.ed.ac.uk        delete pkt;
1046691Stjones1@inf.ed.ac.uk        return;
1056691Stjones1@inf.ed.ac.uk    }
1066691Stjones1@inf.ed.ac.uk
1076691Stjones1@inf.ed.ac.uk    if (isSwitchedOut() || inst->isSquashed()) {
1086691Stjones1@inf.ed.ac.uk        iewStage->decrWb(inst->seqNum);
1096691Stjones1@inf.ed.ac.uk    } else {
1106691Stjones1@inf.ed.ac.uk        if (!state->noWB) {
1116691Stjones1@inf.ed.ac.uk            if (!TheISA::HasUnalignedMemAcc || !state->isSplit ||
1126691Stjones1@inf.ed.ac.uk                !state->isLoad) {
1136691Stjones1@inf.ed.ac.uk                writeback(inst, pkt);
1146691Stjones1@inf.ed.ac.uk            } else {
1156691Stjones1@inf.ed.ac.uk                writeback(inst, state->mainPkt);
1166691Stjones1@inf.ed.ac.uk            }
1176691Stjones1@inf.ed.ac.uk        }
1186691Stjones1@inf.ed.ac.uk
1196691Stjones1@inf.ed.ac.uk        if (inst->isStore()) {
1206691Stjones1@inf.ed.ac.uk            completeStore(state->idx);
1216691Stjones1@inf.ed.ac.uk        }
1226691Stjones1@inf.ed.ac.uk    }
1236691Stjones1@inf.ed.ac.uk
1246691Stjones1@inf.ed.ac.uk    if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) {
1256691Stjones1@inf.ed.ac.uk        delete state->mainPkt->req;
1266691Stjones1@inf.ed.ac.uk        delete state->mainPkt;
1276691Stjones1@inf.ed.ac.uk    }
1286691Stjones1@inf.ed.ac.uk    delete state;
1296691Stjones1@inf.ed.ac.uk    delete pkt->req;
1306691Stjones1@inf.ed.ac.uk    delete pkt;
1316691Stjones1@inf.ed.ac.uk}
1326691Stjones1@inf.ed.ac.uk
1336691Stjones1@inf.ed.ac.uktemplate <class Impl>
1346691Stjones1@inf.ed.ac.ukLSQUnit<Impl>::LSQUnit()
1356691Stjones1@inf.ed.ac.uk    : loads(0), stores(0), storesToWB(0), stalled(false),
1366691Stjones1@inf.ed.ac.uk      isStoreBlocked(false), isLoadBlocked(false),
1376691Stjones1@inf.ed.ac.uk      loadBlockedHandled(false), hasPendingPkt(false)
1386691Stjones1@inf.ed.ac.uk{
1396691Stjones1@inf.ed.ac.uk}
1406691Stjones1@inf.ed.ac.uk
1416691Stjones1@inf.ed.ac.uktemplate<class Impl>
1426691Stjones1@inf.ed.ac.ukvoid
1436691Stjones1@inf.ed.ac.ukLSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
1446691Stjones1@inf.ed.ac.uk        LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
1456691Stjones1@inf.ed.ac.uk        unsigned id)
1466691Stjones1@inf.ed.ac.uk{
1476691Stjones1@inf.ed.ac.uk    cpu = cpu_ptr;
1486691Stjones1@inf.ed.ac.uk    iewStage = iew_ptr;
1496691Stjones1@inf.ed.ac.uk
1506691Stjones1@inf.ed.ac.uk    DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
1516691Stjones1@inf.ed.ac.uk
1526691Stjones1@inf.ed.ac.uk    switchedOut = false;
1536691Stjones1@inf.ed.ac.uk
1546691Stjones1@inf.ed.ac.uk    lsq = lsq_ptr;
1556691Stjones1@inf.ed.ac.uk
1566691Stjones1@inf.ed.ac.uk    lsqID = id;
1576691Stjones1@inf.ed.ac.uk
1586691Stjones1@inf.ed.ac.uk    // Add 1 for the sentinel entry (they are circular queues).
1596691Stjones1@inf.ed.ac.uk    LQEntries = maxLQEntries + 1;
1606691Stjones1@inf.ed.ac.uk    SQEntries = maxSQEntries + 1;
1616691Stjones1@inf.ed.ac.uk
1626691Stjones1@inf.ed.ac.uk    loadQueue.resize(LQEntries);
1636691Stjones1@inf.ed.ac.uk    storeQueue.resize(SQEntries);
1646691Stjones1@inf.ed.ac.uk
1656691Stjones1@inf.ed.ac.uk    loadHead = loadTail = 0;
1666691Stjones1@inf.ed.ac.uk
1676691Stjones1@inf.ed.ac.uk    storeHead = storeWBIdx = storeTail = 0;
1686691Stjones1@inf.ed.ac.uk
1696691Stjones1@inf.ed.ac.uk    usedPorts = 0;
1706691Stjones1@inf.ed.ac.uk    cachePorts = params->cachePorts;
1716691Stjones1@inf.ed.ac.uk
1726691Stjones1@inf.ed.ac.uk    retryPkt = NULL;
1736691Stjones1@inf.ed.ac.uk    memDepViolator = NULL;
1746691Stjones1@inf.ed.ac.uk
1756691Stjones1@inf.ed.ac.uk    blockedLoadSeqNum = 0;
1766691Stjones1@inf.ed.ac.uk}
1776691Stjones1@inf.ed.ac.uk
1786691Stjones1@inf.ed.ac.uktemplate<class Impl>
1796691Stjones1@inf.ed.ac.ukstd::string
1806691Stjones1@inf.ed.ac.ukLSQUnit<Impl>::name() const
1816691Stjones1@inf.ed.ac.uk{
1826691Stjones1@inf.ed.ac.uk    if (Impl::MaxThreads == 1) {
1836691Stjones1@inf.ed.ac.uk        return iewStage->name() + ".lsq";
1846691Stjones1@inf.ed.ac.uk    } else {
1856691Stjones1@inf.ed.ac.uk        return iewStage->name() + ".lsq.thread." + to_string(lsqID);
1866691Stjones1@inf.ed.ac.uk    }
1876691Stjones1@inf.ed.ac.uk}
1886691Stjones1@inf.ed.ac.uk
1896691Stjones1@inf.ed.ac.uktemplate<class Impl>
1906691Stjones1@inf.ed.ac.ukvoid
1916691Stjones1@inf.ed.ac.ukLSQUnit<Impl>::regStats()
1926691Stjones1@inf.ed.ac.uk{
1936691Stjones1@inf.ed.ac.uk    lsqForwLoads
1946691Stjones1@inf.ed.ac.uk        .name(name() + ".forwLoads")
1956691Stjones1@inf.ed.ac.uk        .desc("Number of loads that had data forwarded from stores");
1966691Stjones1@inf.ed.ac.uk
1976691Stjones1@inf.ed.ac.uk    invAddrLoads
1986691Stjones1@inf.ed.ac.uk        .name(name() + ".invAddrLoads")
1996691Stjones1@inf.ed.ac.uk        .desc("Number of loads ignored due to an invalid address");
2006691Stjones1@inf.ed.ac.uk
2016691Stjones1@inf.ed.ac.uk    lsqSquashedLoads
2026691Stjones1@inf.ed.ac.uk        .name(name() + ".squashedLoads")
2036691Stjones1@inf.ed.ac.uk        .desc("Number of loads squashed");
2046691Stjones1@inf.ed.ac.uk
2056691Stjones1@inf.ed.ac.uk    lsqIgnoredResponses
2066691Stjones1@inf.ed.ac.uk        .name(name() + ".ignoredResponses")
2076691Stjones1@inf.ed.ac.uk        .desc("Number of memory responses ignored because the instruction is squashed");
2086691Stjones1@inf.ed.ac.uk
2096691Stjones1@inf.ed.ac.uk    lsqMemOrderViolation
2106691Stjones1@inf.ed.ac.uk        .name(name() + ".memOrderViolation")
2116691Stjones1@inf.ed.ac.uk        .desc("Number of memory ordering violations");
2126691Stjones1@inf.ed.ac.uk
2136691Stjones1@inf.ed.ac.uk    lsqSquashedStores
2146691Stjones1@inf.ed.ac.uk        .name(name() + ".squashedStores")
2156691Stjones1@inf.ed.ac.uk        .desc("Number of stores squashed");
2166691Stjones1@inf.ed.ac.uk
2176691Stjones1@inf.ed.ac.uk    invAddrSwpfs
2186691Stjones1@inf.ed.ac.uk        .name(name() + ".invAddrSwpfs")
2196691Stjones1@inf.ed.ac.uk        .desc("Number of software prefetches ignored due to an invalid address");
2206691Stjones1@inf.ed.ac.uk
2216691Stjones1@inf.ed.ac.uk    lsqBlockedLoads
2226691Stjones1@inf.ed.ac.uk        .name(name() + ".blockedLoads")
2236691Stjones1@inf.ed.ac.uk        .desc("Number of blocked loads due to partial load-store forwarding");
2246691Stjones1@inf.ed.ac.uk
2256691Stjones1@inf.ed.ac.uk    lsqRescheduledLoads
2266691Stjones1@inf.ed.ac.uk        .name(name() + ".rescheduledLoads")
2276691Stjones1@inf.ed.ac.uk        .desc("Number of loads that were rescheduled");
2286691Stjones1@inf.ed.ac.uk
2296691Stjones1@inf.ed.ac.uk    lsqCacheBlocked
2306691Stjones1@inf.ed.ac.uk        .name(name() + ".cacheBlocked")
2316691Stjones1@inf.ed.ac.uk        .desc("Number of times an access to memory failed due to the cache being blocked");
2326691Stjones1@inf.ed.ac.uk}
2336691Stjones1@inf.ed.ac.uk
2346691Stjones1@inf.ed.ac.uktemplate<class Impl>
2356691Stjones1@inf.ed.ac.ukvoid
2366691Stjones1@inf.ed.ac.ukLSQUnit<Impl>::setDcachePort(Port *dcache_port)
2376691Stjones1@inf.ed.ac.uk{
2386691Stjones1@inf.ed.ac.uk    dcachePort = dcache_port;
2396691Stjones1@inf.ed.ac.uk
2406691Stjones1@inf.ed.ac.uk#if USE_CHECKER
2416691Stjones1@inf.ed.ac.uk    if (cpu->checker) {
2426691Stjones1@inf.ed.ac.uk        cpu->checker->setDcachePort(dcachePort);
2436691Stjones1@inf.ed.ac.uk    }
2446691Stjones1@inf.ed.ac.uk#endif
2456691Stjones1@inf.ed.ac.uk}
2466691Stjones1@inf.ed.ac.uk
2476691Stjones1@inf.ed.ac.uktemplate<class Impl>
2486691Stjones1@inf.ed.ac.ukvoid
2496691Stjones1@inf.ed.ac.ukLSQUnit<Impl>::clearLQ()
2506691Stjones1@inf.ed.ac.uk{
2516691Stjones1@inf.ed.ac.uk    loadQueue.clear();
2526691Stjones1@inf.ed.ac.uk}
2536691Stjones1@inf.ed.ac.uk
2546691Stjones1@inf.ed.ac.uktemplate<class Impl>
2556691Stjones1@inf.ed.ac.ukvoid
2566691Stjones1@inf.ed.ac.ukLSQUnit<Impl>::clearSQ()
2576691Stjones1@inf.ed.ac.uk{
2586691Stjones1@inf.ed.ac.uk    storeQueue.clear();
2596691Stjones1@inf.ed.ac.uk}
2606691Stjones1@inf.ed.ac.uk
2616691Stjones1@inf.ed.ac.uktemplate<class Impl>
2626691Stjones1@inf.ed.ac.ukvoid
2636691Stjones1@inf.ed.ac.ukLSQUnit<Impl>::switchOut()
2646691Stjones1@inf.ed.ac.uk{
2656691Stjones1@inf.ed.ac.uk    switchedOut = true;
2666691Stjones1@inf.ed.ac.uk    for (int i = 0; i < loadQueue.size(); ++i) {
2676691Stjones1@inf.ed.ac.uk        assert(!loadQueue[i]);
2686691Stjones1@inf.ed.ac.uk        loadQueue[i] = NULL;
2696691Stjones1@inf.ed.ac.uk    }
2706691Stjones1@inf.ed.ac.uk
2716691Stjones1@inf.ed.ac.uk    assert(storesToWB == 0);
2726691Stjones1@inf.ed.ac.uk}
2736691Stjones1@inf.ed.ac.uk
2746691Stjones1@inf.ed.ac.uktemplate<class Impl>
2756691Stjones1@inf.ed.ac.ukvoid
2766691Stjones1@inf.ed.ac.ukLSQUnit<Impl>::takeOverFrom()
2776691Stjones1@inf.ed.ac.uk{
2786691Stjones1@inf.ed.ac.uk    switchedOut = false;
2796691Stjones1@inf.ed.ac.uk    loads = stores = storesToWB = 0;
2806691Stjones1@inf.ed.ac.uk
2816691Stjones1@inf.ed.ac.uk    loadHead = loadTail = 0;
2826691Stjones1@inf.ed.ac.uk
2836691Stjones1@inf.ed.ac.uk    storeHead = storeWBIdx = storeTail = 0;
2846691Stjones1@inf.ed.ac.uk
2856691Stjones1@inf.ed.ac.uk    usedPorts = 0;
2866691Stjones1@inf.ed.ac.uk
2876691Stjones1@inf.ed.ac.uk    memDepViolator = NULL;
2886691Stjones1@inf.ed.ac.uk
289    blockedLoadSeqNum = 0;
290
291    stalled = false;
292    isLoadBlocked = false;
293    loadBlockedHandled = false;
294}
295
296template<class Impl>
297void
298LSQUnit<Impl>::resizeLQ(unsigned size)
299{
300    unsigned size_plus_sentinel = size + 1;
301    assert(size_plus_sentinel >= LQEntries);
302
303    if (size_plus_sentinel > LQEntries) {
304        while (size_plus_sentinel > loadQueue.size()) {
305            DynInstPtr dummy;
306            loadQueue.push_back(dummy);
307            LQEntries++;
308        }
309    } else {
310        LQEntries = size_plus_sentinel;
311    }
312
313}
314
315template<class Impl>
316void
317LSQUnit<Impl>::resizeSQ(unsigned size)
318{
319    unsigned size_plus_sentinel = size + 1;
320    if (size_plus_sentinel > SQEntries) {
321        while (size_plus_sentinel > storeQueue.size()) {
322            SQEntry dummy;
323            storeQueue.push_back(dummy);
324            SQEntries++;
325        }
326    } else {
327        SQEntries = size_plus_sentinel;
328    }
329}
330
331template <class Impl>
332void
333LSQUnit<Impl>::insert(DynInstPtr &inst)
334{
335    assert(inst->isMemRef());
336
337    assert(inst->isLoad() || inst->isStore());
338
339    if (inst->isLoad()) {
340        insertLoad(inst);
341    } else {
342        insertStore(inst);
343    }
344
345    inst->setInLSQ();
346}
347
348template <class Impl>
349void
350LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
351{
352    assert((loadTail + 1) % LQEntries != loadHead);
353    assert(loads < LQEntries);
354
355    DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n",
356            load_inst->pcState(), loadTail, load_inst->seqNum);
357
358    load_inst->lqIdx = loadTail;
359
360    if (stores == 0) {
361        load_inst->sqIdx = -1;
362    } else {
363        load_inst->sqIdx = storeTail;
364    }
365
366    loadQueue[loadTail] = load_inst;
367
368    incrLdIdx(loadTail);
369
370    ++loads;
371}
372
373template <class Impl>
374void
375LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
376{
377    // Make sure it is not full before inserting an instruction.
378    assert((storeTail + 1) % SQEntries != storeHead);
379    assert(stores < SQEntries);
380
381    DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n",
382            store_inst->pcState(), storeTail, store_inst->seqNum);
383
384    store_inst->sqIdx = storeTail;
385    store_inst->lqIdx = loadTail;
386
387    storeQueue[storeTail] = SQEntry(store_inst);
388
389    incrStIdx(storeTail);
390
391    ++stores;
392}
393
394template <class Impl>
395typename Impl::DynInstPtr
396LSQUnit<Impl>::getMemDepViolator()
397{
398    DynInstPtr temp = memDepViolator;
399
400    memDepViolator = NULL;
401
402    return temp;
403}
404
405template <class Impl>
406unsigned
407LSQUnit<Impl>::numFreeEntries()
408{
409    unsigned free_lq_entries = LQEntries - loads;
410    unsigned free_sq_entries = SQEntries - stores;
411
412    // Both the LQ and SQ entries have an extra dummy entry to differentiate
413    // empty/full conditions.  Subtract 1 from the free entries.
414    if (free_lq_entries < free_sq_entries) {
415        return free_lq_entries - 1;
416    } else {
417        return free_sq_entries - 1;
418    }
419}
420
421template <class Impl>
422int
423LSQUnit<Impl>::numLoadsReady()
424{
425    int load_idx = loadHead;
426    int retval = 0;
427
428    while (load_idx != loadTail) {
429        assert(loadQueue[load_idx]);
430
431        if (loadQueue[load_idx]->readyToIssue()) {
432            ++retval;
433        }
434    }
435
436    return retval;
437}
438
439template <class Impl>
440Fault
441LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
442{
443    using namespace TheISA;
444    // Execute a specific load.
445    Fault load_fault = NoFault;
446
447    DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n",
448            inst->pcState(),inst->seqNum);
449
450    assert(!inst->isSquashed());
451
452    load_fault = inst->initiateAcc();
453
454    // If the instruction faulted or predicated false, then we need to send it
455    // along to commit without the instruction completing.
456    if (load_fault != NoFault || inst->readPredicate() == false) {
457        // Send this instruction to commit, also make sure iew stage
458        // realizes there is activity.
459        // Mark it as executed unless it is an uncached load that
460        // needs to hit the head of commit.
461        DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n",
462                inst->seqNum,
463                (load_fault != NoFault ? "fault" : "predication"));
464        if (!(inst->hasRequest() && inst->uncacheable()) ||
465            inst->isAtCommit()) {
466            inst->setExecuted();
467        }
468        iewStage->instToCommit(inst);
469        iewStage->activityThisCycle();
470    } else if (!loadBlocked()) {
471        assert(inst->effAddrValid);
472        int load_idx = inst->lqIdx;
473        incrLdIdx(load_idx);
474        while (load_idx != loadTail) {
475            // Really only need to check loads that have actually executed
476
477            // @todo: For now this is extra conservative, detecting a
478            // violation if the addresses match assuming all accesses
479            // are quad word accesses.
480
481            // @todo: Fix this, magic number being used here
482
483            // @todo: Uncachable load is not executed until it reaches
484            // the head of the ROB. Once this if checks only the executed
485            // loads(as noted above), this check can be removed
486            if (loadQueue[load_idx]->effAddrValid &&
487                ((loadQueue[load_idx]->effAddr >> 8)
488                 == (inst->effAddr >> 8)) &&
489                !loadQueue[load_idx]->uncacheable()) {
490                // A load incorrectly passed this load.  Squash and refetch.
491                // For now return a fault to show that it was unsuccessful.
492                DynInstPtr violator = loadQueue[load_idx];
493                if (!memDepViolator ||
494                    (violator->seqNum < memDepViolator->seqNum)) {
495                    memDepViolator = violator;
496                } else {
497                    break;
498                }
499
500                ++lsqMemOrderViolation;
501
502                return genMachineCheckFault();
503            }
504
505            incrLdIdx(load_idx);
506        }
507    }
508
509    return load_fault;
510}
511
512template <class Impl>
513Fault
514LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
515{
516    using namespace TheISA;
517    // Make sure that a store exists.
518    assert(stores != 0);
519
520    int store_idx = store_inst->sqIdx;
521
522    DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n",
523            store_inst->pcState(), store_inst->seqNum);
524
525    assert(!store_inst->isSquashed());
526
527    // Check the recently completed loads to see if any match this store's
528    // address.  If so, then we have a memory ordering violation.
529    int load_idx = store_inst->lqIdx;
530
531    Fault store_fault = store_inst->initiateAcc();
532
533    if (storeQueue[store_idx].size == 0) {
534        DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli],Size = 0\n",
535                store_inst->pcState(), store_inst->seqNum);
536
537        return store_fault;
538    }
539
540    assert(store_fault == NoFault);
541
542    if (store_inst->isStoreConditional()) {
543        // Store conditionals need to set themselves as able to
544        // writeback if we haven't had a fault by here.
545        storeQueue[store_idx].canWB = true;
546
547        ++storesToWB;
548    }
549
550    assert(store_inst->effAddrValid);
551    while (load_idx != loadTail) {
552        // Really only need to check loads that have actually executed
553        // It's safe to check all loads because effAddr is set to
554        // InvalAddr when the dyn inst is created.
555
556        // @todo: For now this is extra conservative, detecting a
557        // violation if the addresses match assuming all accesses
558        // are quad word accesses.
559
560        // @todo: Fix this, magic number being used here
561
562        // @todo: Uncachable load is not executed until it reaches
563        // the head of the ROB. Once this if checks only the executed
564        // loads(as noted above), this check can be removed
565        if (loadQueue[load_idx]->effAddrValid &&
566            ((loadQueue[load_idx]->effAddr >> 8)
567             == (store_inst->effAddr >> 8)) &&
568            !loadQueue[load_idx]->uncacheable()) {
569            // A load incorrectly passed this store.  Squash and refetch.
570            // For now return a fault to show that it was unsuccessful.
571            DynInstPtr violator = loadQueue[load_idx];
572            if (!memDepViolator ||
573                (violator->seqNum < memDepViolator->seqNum)) {
574                memDepViolator = violator;
575            } else {
576                break;
577            }
578
579            ++lsqMemOrderViolation;
580
581            return genMachineCheckFault();
582        }
583
584        incrLdIdx(load_idx);
585    }
586
587    return store_fault;
588}
589
590template <class Impl>
591void
592LSQUnit<Impl>::commitLoad()
593{
594    assert(loadQueue[loadHead]);
595
596    DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n",
597            loadQueue[loadHead]->pcState());
598
599    loadQueue[loadHead] = NULL;
600
601    incrLdIdx(loadHead);
602
603    --loads;
604}
605
606template <class Impl>
607void
608LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
609{
610    assert(loads == 0 || loadQueue[loadHead]);
611
612    while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
613        commitLoad();
614    }
615}
616
617template <class Impl>
618void
619LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
620{
621    assert(stores == 0 || storeQueue[storeHead].inst);
622
623    int store_idx = storeHead;
624
625    while (store_idx != storeTail) {
626        assert(storeQueue[store_idx].inst);
627        // Mark any stores that are now committed and have not yet
628        // been marked as able to write back.
629        if (!storeQueue[store_idx].canWB) {
630            if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
631                break;
632            }
633            DPRINTF(LSQUnit, "Marking store as able to write back, PC "
634                    "%s [sn:%lli]\n",
635                    storeQueue[store_idx].inst->pcState(),
636                    storeQueue[store_idx].inst->seqNum);
637
638            storeQueue[store_idx].canWB = true;
639
640            ++storesToWB;
641        }
642
643        incrStIdx(store_idx);
644    }
645}
646
647template <class Impl>
648void
649LSQUnit<Impl>::writebackPendingStore()
650{
651    if (hasPendingPkt) {
652        assert(pendingPkt != NULL);
653
654        // If the cache is blocked, this will store the packet for retry.
655        if (sendStore(pendingPkt)) {
656            storePostSend(pendingPkt);
657        }
658        pendingPkt = NULL;
659        hasPendingPkt = false;
660    }
661}
662
663template <class Impl>
664void
665LSQUnit<Impl>::writebackStores()
666{
667    // First writeback the second packet from any split store that didn't
668    // complete last cycle because there weren't enough cache ports available.
669    if (TheISA::HasUnalignedMemAcc) {
670        writebackPendingStore();
671    }
672
673    while (storesToWB > 0 &&
674           storeWBIdx != storeTail &&
675           storeQueue[storeWBIdx].inst &&
676           storeQueue[storeWBIdx].canWB &&
677           usedPorts < cachePorts) {
678
679        if (isStoreBlocked || lsq->cacheBlocked()) {
680            DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
681                    " is blocked!\n");
682            break;
683        }
684
685        // Store didn't write any data so no need to write it back to
686        // memory.
687        if (storeQueue[storeWBIdx].size == 0) {
688            completeStore(storeWBIdx);
689
690            incrStIdx(storeWBIdx);
691
692            continue;
693        }
694
695        ++usedPorts;
696
697        if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
698            incrStIdx(storeWBIdx);
699
700            continue;
701        }
702
703        assert(storeQueue[storeWBIdx].req);
704        assert(!storeQueue[storeWBIdx].committed);
705
706        if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
707            assert(storeQueue[storeWBIdx].sreqLow);
708            assert(storeQueue[storeWBIdx].sreqHigh);
709        }
710
711        DynInstPtr inst = storeQueue[storeWBIdx].inst;
712
713        Request *req = storeQueue[storeWBIdx].req;
714        storeQueue[storeWBIdx].committed = true;
715
716        assert(!inst->memData);
717        inst->memData = new uint8_t[64];
718
719        memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
720
721        MemCmd command =
722            req->isSwap() ? MemCmd::SwapReq :
723            (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq);
724        PacketPtr data_pkt;
725        PacketPtr snd_data_pkt = NULL;
726
727        LSQSenderState *state = new LSQSenderState;
728        state->isLoad = false;
729        state->idx = storeWBIdx;
730        state->inst = inst;
731
732        if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) {
733
734            // Build a single data packet if the store isn't split.
735            data_pkt = new Packet(req, command, Packet::Broadcast);
736            data_pkt->dataStatic(inst->memData);
737            data_pkt->senderState = state;
738        } else {
739            RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow;
740            RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh;
741
742            // Create two packets if the store is split in two.
743            data_pkt = new Packet(sreqLow, command, Packet::Broadcast);
744            snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast);
745
746            data_pkt->dataStatic(inst->memData);
747            snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize());
748
749            data_pkt->senderState = state;
750            snd_data_pkt->senderState = state;
751
752            state->isSplit = true;
753            state->outstanding = 2;
754
755            // Can delete the main request now.
756            delete req;
757            req = sreqLow;
758        }
759
760        DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s "
761                "to Addr:%#x, data:%#x [sn:%lli]\n",
762                storeWBIdx, inst->pcState(),
763                req->getPaddr(), (int)*(inst->memData),
764                inst->seqNum);
765
766        // @todo: Remove this SC hack once the memory system handles it.
767        if (inst->isStoreConditional()) {
768            assert(!storeQueue[storeWBIdx].isSplit);
769            // Disable recording the result temporarily.  Writing to
770            // misc regs normally updates the result, but this is not
771            // the desired behavior when handling store conditionals.
772            inst->recordResult = false;
773            bool success = TheISA::handleLockedWrite(inst.get(), req);
774            inst->recordResult = true;
775
776            if (!success) {
777                // Instantly complete this store.
778                DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed.  "
779                        "Instantly completing it.\n",
780                        inst->seqNum);
781                WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
782                cpu->schedule(wb, curTick + 1);
783                completeStore(storeWBIdx);
784                incrStIdx(storeWBIdx);
785                continue;
786            }
787        } else {
788            // Non-store conditionals do not need a writeback.
789            state->noWB = true;
790        }
791
792        if (!sendStore(data_pkt)) {
793            DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
794                    "retry later\n",
795                    inst->seqNum);
796
797            // Need to store the second packet, if split.
798            if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
799                state->pktToSend = true;
800                state->pendingPacket = snd_data_pkt;
801            }
802        } else {
803
804            // If split, try to send the second packet too
805            if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
806                assert(snd_data_pkt);
807
808                // Ensure there are enough ports to use.
809                if (usedPorts < cachePorts) {
810                    ++usedPorts;
811                    if (sendStore(snd_data_pkt)) {
812                        storePostSend(snd_data_pkt);
813                    } else {
814                        DPRINTF(IEW, "D-Cache became blocked when writing"
815                                " [sn:%lli] second packet, will retry later\n",
816                                inst->seqNum);
817                    }
818                } else {
819
820                    // Store the packet for when there's free ports.
821                    assert(pendingPkt == NULL);
822                    pendingPkt = snd_data_pkt;
823                    hasPendingPkt = true;
824                }
825            } else {
826
827                // Not a split store.
828                storePostSend(data_pkt);
829            }
830        }
831    }
832
833    // Not sure this should set it to 0.
834    usedPorts = 0;
835
836    assert(stores >= 0 && storesToWB >= 0);
837}
838
839/*template <class Impl>
840void
841LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
842{
843    list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
844                                              mshrSeqNums.end(),
845                                              seqNum);
846
847    if (mshr_it != mshrSeqNums.end()) {
848        mshrSeqNums.erase(mshr_it);
849        DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
850    }
851}*/
852
853template <class Impl>
854void
855LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
856{
857    DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
858            "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
859
860    int load_idx = loadTail;
861    decrLdIdx(load_idx);
862
863    while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
864        DPRINTF(LSQUnit,"Load Instruction PC %s squashed, "
865                "[sn:%lli]\n",
866                loadQueue[load_idx]->pcState(),
867                loadQueue[load_idx]->seqNum);
868
869        if (isStalled() && load_idx == stallingLoadIdx) {
870            stalled = false;
871            stallingStoreIsn = 0;
872            stallingLoadIdx = 0;
873        }
874
875        // Clear the smart pointer to make sure it is decremented.
876        loadQueue[load_idx]->setSquashed();
877        loadQueue[load_idx] = NULL;
878        --loads;
879
880        // Inefficient!
881        loadTail = load_idx;
882
883        decrLdIdx(load_idx);
884        ++lsqSquashedLoads;
885    }
886
887    if (isLoadBlocked) {
888        if (squashed_num < blockedLoadSeqNum) {
889            isLoadBlocked = false;
890            loadBlockedHandled = false;
891            blockedLoadSeqNum = 0;
892        }
893    }
894
895    if (memDepViolator && squashed_num < memDepViolator->seqNum) {
896        memDepViolator = NULL;
897    }
898
899    int store_idx = storeTail;
900    decrStIdx(store_idx);
901
902    while (stores != 0 &&
903           storeQueue[store_idx].inst->seqNum > squashed_num) {
904        // Instructions marked as can WB are already committed.
905        if (storeQueue[store_idx].canWB) {
906            break;
907        }
908
909        DPRINTF(LSQUnit,"Store Instruction PC %s squashed, "
910                "idx:%i [sn:%lli]\n",
911                storeQueue[store_idx].inst->pcState(),
912                store_idx, storeQueue[store_idx].inst->seqNum);
913
914        // I don't think this can happen.  It should have been cleared
915        // by the stalling load.
916        if (isStalled() &&
917            storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
918            panic("Is stalled should have been cleared by stalling load!\n");
919            stalled = false;
920            stallingStoreIsn = 0;
921        }
922
923        // Clear the smart pointer to make sure it is decremented.
924        storeQueue[store_idx].inst->setSquashed();
925        storeQueue[store_idx].inst = NULL;
926        storeQueue[store_idx].canWB = 0;
927
928        // Must delete request now that it wasn't handed off to
929        // memory.  This is quite ugly.  @todo: Figure out the proper
930        // place to really handle request deletes.
931        delete storeQueue[store_idx].req;
932        if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) {
933            delete storeQueue[store_idx].sreqLow;
934            delete storeQueue[store_idx].sreqHigh;
935
936            storeQueue[store_idx].sreqLow = NULL;
937            storeQueue[store_idx].sreqHigh = NULL;
938        }
939
940        storeQueue[store_idx].req = NULL;
941        --stores;
942
943        // Inefficient!
944        storeTail = store_idx;
945
946        decrStIdx(store_idx);
947        ++lsqSquashedStores;
948    }
949}
950
951template <class Impl>
952void
953LSQUnit<Impl>::storePostSend(PacketPtr pkt)
954{
955    if (isStalled() &&
956        storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
957        DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
958                "load idx:%i\n",
959                stallingStoreIsn, stallingLoadIdx);
960        stalled = false;
961        stallingStoreIsn = 0;
962        iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
963    }
964
965    if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
966        // The store is basically completed at this time. This
967        // only works so long as the checker doesn't try to
968        // verify the value in memory for stores.
969        storeQueue[storeWBIdx].inst->setCompleted();
970#if USE_CHECKER
971        if (cpu->checker) {
972            cpu->checker->verify(storeQueue[storeWBIdx].inst);
973        }
974#endif
975    }
976
977    incrStIdx(storeWBIdx);
978}
979
980template <class Impl>
981void
982LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
983{
984    iewStage->wakeCPU();
985
986    // Squashed instructions do not need to complete their access.
987    if (inst->isSquashed()) {
988        iewStage->decrWb(inst->seqNum);
989        assert(!inst->isStore());
990        ++lsqIgnoredResponses;
991        return;
992    }
993
994    if (!inst->isExecuted()) {
995        inst->setExecuted();
996
997        // Complete access to copy data to proper place.
998        inst->completeAcc(pkt);
999    }
1000
1001    // Need to insert instruction into queue to commit
1002    iewStage->instToCommit(inst);
1003
1004    iewStage->activityThisCycle();
1005
1006    // see if this load changed the PC
1007    iewStage->checkMisprediction(inst);
1008}
1009
1010template <class Impl>
1011void
1012LSQUnit<Impl>::completeStore(int store_idx)
1013{
1014    assert(storeQueue[store_idx].inst);
1015    storeQueue[store_idx].completed = true;
1016    --storesToWB;
1017    // A bit conservative because a store completion may not free up entries,
1018    // but hopefully avoids two store completions in one cycle from making
1019    // the CPU tick twice.
1020    cpu->wakeCPU();
1021    cpu->activityThisCycle();
1022
1023    if (store_idx == storeHead) {
1024        do {
1025            incrStIdx(storeHead);
1026
1027            --stores;
1028        } while (storeQueue[storeHead].completed &&
1029                 storeHead != storeTail);
1030
1031        iewStage->updateLSQNextCycle = true;
1032    }
1033
1034    DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
1035            "idx:%i\n",
1036            storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
1037
1038    if (isStalled() &&
1039        storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
1040        DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
1041                "load idx:%i\n",
1042                stallingStoreIsn, stallingLoadIdx);
1043        stalled = false;
1044        stallingStoreIsn = 0;
1045        iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
1046    }
1047
1048    storeQueue[store_idx].inst->setCompleted();
1049
1050    // Tell the checker we've completed this instruction.  Some stores
1051    // may get reported twice to the checker, but the checker can
1052    // handle that case.
1053#if USE_CHECKER
1054    if (cpu->checker) {
1055        cpu->checker->verify(storeQueue[store_idx].inst);
1056    }
1057#endif
1058}
1059
1060template <class Impl>
1061bool
1062LSQUnit<Impl>::sendStore(PacketPtr data_pkt)
1063{
1064    if (!dcachePort->sendTiming(data_pkt)) {
1065        // Need to handle becoming blocked on a store.
1066        isStoreBlocked = true;
1067        ++lsqCacheBlocked;
1068        assert(retryPkt == NULL);
1069        retryPkt = data_pkt;
1070        lsq->setRetryTid(lsqID);
1071        return false;
1072    }
1073    return true;
1074}
1075
1076template <class Impl>
1077void
1078LSQUnit<Impl>::recvRetry()
1079{
1080    if (isStoreBlocked) {
1081        DPRINTF(LSQUnit, "Receiving retry: store blocked\n");
1082        assert(retryPkt != NULL);
1083
1084        if (dcachePort->sendTiming(retryPkt)) {
1085            LSQSenderState *state =
1086                dynamic_cast<LSQSenderState *>(retryPkt->senderState);
1087
1088            // Don't finish the store unless this is the last packet.
1089            if (!TheISA::HasUnalignedMemAcc || !state->pktToSend) {
1090                storePostSend(retryPkt);
1091            }
1092            retryPkt = NULL;
1093            isStoreBlocked = false;
1094            lsq->setRetryTid(InvalidThreadID);
1095
1096            // Send any outstanding packet.
1097            if (TheISA::HasUnalignedMemAcc && state->pktToSend) {
1098                assert(state->pendingPacket);
1099                if (sendStore(state->pendingPacket)) {
1100                    storePostSend(state->pendingPacket);
1101                }
1102            }
1103        } else {
1104            // Still blocked!
1105            ++lsqCacheBlocked;
1106            lsq->setRetryTid(lsqID);
1107        }
1108    } else if (isLoadBlocked) {
1109        DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
1110                "no need to resend packet.\n");
1111    } else {
1112        DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
1113    }
1114}
1115
1116template <class Impl>
1117inline void
1118LSQUnit<Impl>::incrStIdx(int &store_idx)
1119{
1120    if (++store_idx >= SQEntries)
1121        store_idx = 0;
1122}
1123
1124template <class Impl>
1125inline void
1126LSQUnit<Impl>::decrStIdx(int &store_idx)
1127{
1128    if (--store_idx < 0)
1129        store_idx += SQEntries;
1130}
1131
1132template <class Impl>
1133inline void
1134LSQUnit<Impl>::incrLdIdx(int &load_idx)
1135{
1136    if (++load_idx >= LQEntries)
1137        load_idx = 0;
1138}
1139
1140template <class Impl>
1141inline void
1142LSQUnit<Impl>::decrLdIdx(int &load_idx)
1143{
1144    if (--load_idx < 0)
1145        load_idx += LQEntries;
1146}
1147
1148template <class Impl>
1149void
1150LSQUnit<Impl>::dumpInsts()
1151{
1152    cprintf("Load store queue: Dumping instructions.\n");
1153    cprintf("Load queue size: %i\n", loads);
1154    cprintf("Load queue: ");
1155
1156    int load_idx = loadHead;
1157
1158    while (load_idx != loadTail && loadQueue[load_idx]) {
1159        cprintf("%s ", loadQueue[load_idx]->pcState());
1160
1161        incrLdIdx(load_idx);
1162    }
1163
1164    cprintf("Store queue size: %i\n", stores);
1165    cprintf("Store queue: ");
1166
1167    int store_idx = storeHead;
1168
1169    while (store_idx != storeTail && storeQueue[store_idx].inst) {
1170        cprintf("%s ", storeQueue[store_idx].inst->pcState());
1171
1172        incrStIdx(store_idx);
1173    }
1174
1175    cprintf("\n");
1176}
1177