lsq_unit_impl.hh revision 3349:fec4a86fa212 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include "config/use_checker.hh"
33
34#include "cpu/o3/lsq.hh"
35#include "cpu/o3/lsq_unit.hh"
36#include "base/str.hh"
37#include "mem/packet.hh"
38#include "mem/request.hh"
39
40#if USE_CHECKER
41#include "cpu/checker/cpu.hh"
42#endif
43
44template<class Impl>
45LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
46                                              LSQUnit *lsq_ptr)
47    : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
48{
49    this->setFlags(Event::AutoDelete);
50}
51
52template<class Impl>
53void
54LSQUnit<Impl>::WritebackEvent::process()
55{
56    if (!lsqPtr->isSwitchedOut()) {
57        lsqPtr->writeback(inst, pkt);
58    }
59    delete pkt;
60}
61
62template<class Impl>
63const char *
64LSQUnit<Impl>::WritebackEvent::description()
65{
66    return "Store writeback event";
67}
68
69template<class Impl>
70void
71LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
72{
73    LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
74    DynInstPtr inst = state->inst;
75    DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
76    DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
77
78    //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
79
80    if (isSwitchedOut() || inst->isSquashed()) {
81        iewStage->decrWb(inst->seqNum);
82        delete state;
83        delete pkt;
84        return;
85    } else {
86        if (!state->noWB) {
87            writeback(inst, pkt);
88        }
89
90        if (inst->isStore()) {
91            completeStore(state->idx);
92        }
93    }
94
95    delete state;
96    delete pkt;
97}
98
99template <class Impl>
100LSQUnit<Impl>::LSQUnit()
101    : loads(0), stores(0), storesToWB(0), stalled(false),
102      isStoreBlocked(false), isLoadBlocked(false),
103      loadBlockedHandled(false)
104{
105}
106
107template<class Impl>
108void
109LSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
110                    unsigned maxSQEntries, unsigned id)
111{
112    DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
113
114    switchedOut = false;
115
116    lsq = lsq_ptr;
117
118    lsqID = id;
119
120    // Add 1 for the sentinel entry (they are circular queues).
121    LQEntries = maxLQEntries + 1;
122    SQEntries = maxSQEntries + 1;
123
124    loadQueue.resize(LQEntries);
125    storeQueue.resize(SQEntries);
126
127    loadHead = loadTail = 0;
128
129    storeHead = storeWBIdx = storeTail = 0;
130
131    usedPorts = 0;
132    cachePorts = params->cachePorts;
133
134    memDepViolator = NULL;
135
136    blockedLoadSeqNum = 0;
137}
138
139template<class Impl>
140void
141LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr)
142{
143    cpu = cpu_ptr;
144
145#if USE_CHECKER
146    if (cpu->checker) {
147        cpu->checker->setDcachePort(dcachePort);
148    }
149#endif
150}
151
152template<class Impl>
153std::string
154LSQUnit<Impl>::name() const
155{
156    if (Impl::MaxThreads == 1) {
157        return iewStage->name() + ".lsq";
158    } else {
159        return iewStage->name() + ".lsq.thread." + to_string(lsqID);
160    }
161}
162
163template<class Impl>
164void
165LSQUnit<Impl>::regStats()
166{
167    lsqForwLoads
168        .name(name() + ".forwLoads")
169        .desc("Number of loads that had data forwarded from stores");
170
171    invAddrLoads
172        .name(name() + ".invAddrLoads")
173        .desc("Number of loads ignored due to an invalid address");
174
175    lsqSquashedLoads
176        .name(name() + ".squashedLoads")
177        .desc("Number of loads squashed");
178
179    lsqIgnoredResponses
180        .name(name() + ".ignoredResponses")
181        .desc("Number of memory responses ignored because the instruction is squashed");
182
183    lsqMemOrderViolation
184        .name(name() + ".memOrderViolation")
185        .desc("Number of memory ordering violations");
186
187    lsqSquashedStores
188        .name(name() + ".squashedStores")
189        .desc("Number of stores squashed");
190
191    invAddrSwpfs
192        .name(name() + ".invAddrSwpfs")
193        .desc("Number of software prefetches ignored due to an invalid address");
194
195    lsqBlockedLoads
196        .name(name() + ".blockedLoads")
197        .desc("Number of blocked loads due to partial load-store forwarding");
198
199    lsqRescheduledLoads
200        .name(name() + ".rescheduledLoads")
201        .desc("Number of loads that were rescheduled");
202
203    lsqCacheBlocked
204        .name(name() + ".cacheBlocked")
205        .desc("Number of times an access to memory failed due to the cache being blocked");
206}
207
208template<class Impl>
209void
210LSQUnit<Impl>::clearLQ()
211{
212    loadQueue.clear();
213}
214
215template<class Impl>
216void
217LSQUnit<Impl>::clearSQ()
218{
219    storeQueue.clear();
220}
221
222template<class Impl>
223void
224LSQUnit<Impl>::switchOut()
225{
226    switchedOut = true;
227    for (int i = 0; i < loadQueue.size(); ++i) {
228        assert(!loadQueue[i]);
229        loadQueue[i] = NULL;
230    }
231
232    assert(storesToWB == 0);
233}
234
235template<class Impl>
236void
237LSQUnit<Impl>::takeOverFrom()
238{
239    switchedOut = false;
240    loads = stores = storesToWB = 0;
241
242    loadHead = loadTail = 0;
243
244    storeHead = storeWBIdx = storeTail = 0;
245
246    usedPorts = 0;
247
248    memDepViolator = NULL;
249
250    blockedLoadSeqNum = 0;
251
252    stalled = false;
253    isLoadBlocked = false;
254    loadBlockedHandled = false;
255}
256
257template<class Impl>
258void
259LSQUnit<Impl>::resizeLQ(unsigned size)
260{
261    unsigned size_plus_sentinel = size + 1;
262    assert(size_plus_sentinel >= LQEntries);
263
264    if (size_plus_sentinel > LQEntries) {
265        while (size_plus_sentinel > loadQueue.size()) {
266            DynInstPtr dummy;
267            loadQueue.push_back(dummy);
268            LQEntries++;
269        }
270    } else {
271        LQEntries = size_plus_sentinel;
272    }
273
274}
275
276template<class Impl>
277void
278LSQUnit<Impl>::resizeSQ(unsigned size)
279{
280    unsigned size_plus_sentinel = size + 1;
281    if (size_plus_sentinel > SQEntries) {
282        while (size_plus_sentinel > storeQueue.size()) {
283            SQEntry dummy;
284            storeQueue.push_back(dummy);
285            SQEntries++;
286        }
287    } else {
288        SQEntries = size_plus_sentinel;
289    }
290}
291
292template <class Impl>
293void
294LSQUnit<Impl>::insert(DynInstPtr &inst)
295{
296    assert(inst->isMemRef());
297
298    assert(inst->isLoad() || inst->isStore());
299
300    if (inst->isLoad()) {
301        insertLoad(inst);
302    } else {
303        insertStore(inst);
304    }
305
306    inst->setInLSQ();
307}
308
309template <class Impl>
310void
311LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
312{
313    assert((loadTail + 1) % LQEntries != loadHead);
314    assert(loads < LQEntries);
315
316    DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
317            load_inst->readPC(), loadTail, load_inst->seqNum);
318
319    load_inst->lqIdx = loadTail;
320
321    if (stores == 0) {
322        load_inst->sqIdx = -1;
323    } else {
324        load_inst->sqIdx = storeTail;
325    }
326
327    loadQueue[loadTail] = load_inst;
328
329    incrLdIdx(loadTail);
330
331    ++loads;
332}
333
334template <class Impl>
335void
336LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
337{
338    // Make sure it is not full before inserting an instruction.
339    assert((storeTail + 1) % SQEntries != storeHead);
340    assert(stores < SQEntries);
341
342    DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
343            store_inst->readPC(), storeTail, store_inst->seqNum);
344
345    store_inst->sqIdx = storeTail;
346    store_inst->lqIdx = loadTail;
347
348    storeQueue[storeTail] = SQEntry(store_inst);
349
350    incrStIdx(storeTail);
351
352    ++stores;
353}
354
355template <class Impl>
356typename Impl::DynInstPtr
357LSQUnit<Impl>::getMemDepViolator()
358{
359    DynInstPtr temp = memDepViolator;
360
361    memDepViolator = NULL;
362
363    return temp;
364}
365
366template <class Impl>
367unsigned
368LSQUnit<Impl>::numFreeEntries()
369{
370    unsigned free_lq_entries = LQEntries - loads;
371    unsigned free_sq_entries = SQEntries - stores;
372
373    // Both the LQ and SQ entries have an extra dummy entry to differentiate
374    // empty/full conditions.  Subtract 1 from the free entries.
375    if (free_lq_entries < free_sq_entries) {
376        return free_lq_entries - 1;
377    } else {
378        return free_sq_entries - 1;
379    }
380}
381
382template <class Impl>
383int
384LSQUnit<Impl>::numLoadsReady()
385{
386    int load_idx = loadHead;
387    int retval = 0;
388
389    while (load_idx != loadTail) {
390        assert(loadQueue[load_idx]);
391
392        if (loadQueue[load_idx]->readyToIssue()) {
393            ++retval;
394        }
395    }
396
397    return retval;
398}
399
400template <class Impl>
401Fault
402LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
403{
404    // Execute a specific load.
405    Fault load_fault = NoFault;
406
407    DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
408            inst->readPC(),inst->seqNum);
409
410    load_fault = inst->initiateAcc();
411
412    // If the instruction faulted, then we need to send it along to commit
413    // without the instruction completing.
414    if (load_fault != NoFault) {
415        // Send this instruction to commit, also make sure iew stage
416        // realizes there is activity.
417        // Mark it as executed unless it is an uncached load that
418        // needs to hit the head of commit.
419        if (!(inst->req->isUncacheable()) || inst->isAtCommit()) {
420            inst->setExecuted();
421        }
422        iewStage->instToCommit(inst);
423        iewStage->activityThisCycle();
424    }
425
426    return load_fault;
427}
428
429template <class Impl>
430Fault
431LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
432{
433    using namespace TheISA;
434    // Make sure that a store exists.
435    assert(stores != 0);
436
437    int store_idx = store_inst->sqIdx;
438
439    DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
440            store_inst->readPC(), store_inst->seqNum);
441
442    // Check the recently completed loads to see if any match this store's
443    // address.  If so, then we have a memory ordering violation.
444    int load_idx = store_inst->lqIdx;
445
446    Fault store_fault = store_inst->initiateAcc();
447
448    if (storeQueue[store_idx].size == 0) {
449        DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
450                store_inst->readPC(),store_inst->seqNum);
451
452        return store_fault;
453    }
454
455    assert(store_fault == NoFault);
456
457    if (store_inst->isStoreConditional()) {
458        // Store conditionals need to set themselves as able to
459        // writeback if we haven't had a fault by here.
460        storeQueue[store_idx].canWB = true;
461
462        ++storesToWB;
463    }
464
465    if (!memDepViolator) {
466        while (load_idx != loadTail) {
467            // Really only need to check loads that have actually executed
468            // It's safe to check all loads because effAddr is set to
469            // InvalAddr when the dyn inst is created.
470
471            // @todo: For now this is extra conservative, detecting a
472            // violation if the addresses match assuming all accesses
473            // are quad word accesses.
474
475            // @todo: Fix this, magic number being used here
476            if ((loadQueue[load_idx]->effAddr >> 8) ==
477                (store_inst->effAddr >> 8)) {
478                // A load incorrectly passed this store.  Squash and refetch.
479                // For now return a fault to show that it was unsuccessful.
480                memDepViolator = loadQueue[load_idx];
481                ++lsqMemOrderViolation;
482
483                return genMachineCheckFault();
484            }
485
486            incrLdIdx(load_idx);
487        }
488
489        // If we've reached this point, there was no violation.
490        memDepViolator = NULL;
491    }
492
493    return store_fault;
494}
495
496template <class Impl>
497void
498LSQUnit<Impl>::commitLoad()
499{
500    assert(loadQueue[loadHead]);
501
502    DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
503            loadQueue[loadHead]->readPC());
504
505    loadQueue[loadHead] = NULL;
506
507    incrLdIdx(loadHead);
508
509    --loads;
510}
511
512template <class Impl>
513void
514LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
515{
516    assert(loads == 0 || loadQueue[loadHead]);
517
518    while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
519        commitLoad();
520    }
521}
522
523template <class Impl>
524void
525LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
526{
527    assert(stores == 0 || storeQueue[storeHead].inst);
528
529    int store_idx = storeHead;
530
531    while (store_idx != storeTail) {
532        assert(storeQueue[store_idx].inst);
533        // Mark any stores that are now committed and have not yet
534        // been marked as able to write back.
535        if (!storeQueue[store_idx].canWB) {
536            if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
537                break;
538            }
539            DPRINTF(LSQUnit, "Marking store as able to write back, PC "
540                    "%#x [sn:%lli]\n",
541                    storeQueue[store_idx].inst->readPC(),
542                    storeQueue[store_idx].inst->seqNum);
543
544            storeQueue[store_idx].canWB = true;
545
546            ++storesToWB;
547        }
548
549        incrStIdx(store_idx);
550    }
551}
552
553template <class Impl>
554void
555LSQUnit<Impl>::writebackStores()
556{
557    while (storesToWB > 0 &&
558           storeWBIdx != storeTail &&
559           storeQueue[storeWBIdx].inst &&
560           storeQueue[storeWBIdx].canWB &&
561           usedPorts < cachePorts) {
562
563        if (isStoreBlocked || lsq->cacheBlocked()) {
564            DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
565                    " is blocked!\n");
566            break;
567        }
568
569        // Store didn't write any data so no need to write it back to
570        // memory.
571        if (storeQueue[storeWBIdx].size == 0) {
572            completeStore(storeWBIdx);
573
574            incrStIdx(storeWBIdx);
575
576            continue;
577        }
578
579        ++usedPorts;
580
581        if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
582            incrStIdx(storeWBIdx);
583
584            continue;
585        }
586
587        assert(storeQueue[storeWBIdx].req);
588        assert(!storeQueue[storeWBIdx].committed);
589
590        DynInstPtr inst = storeQueue[storeWBIdx].inst;
591
592        Request *req = storeQueue[storeWBIdx].req;
593        storeQueue[storeWBIdx].committed = true;
594
595        assert(!inst->memData);
596        inst->memData = new uint8_t[64];
597        memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data,
598               req->getSize());
599
600        PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
601        data_pkt->dataStatic(inst->memData);
602
603        LSQSenderState *state = new LSQSenderState;
604        state->isLoad = false;
605        state->idx = storeWBIdx;
606        state->inst = inst;
607        data_pkt->senderState = state;
608
609        DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
610                "to Addr:%#x, data:%#x [sn:%lli]\n",
611                storeWBIdx, inst->readPC(),
612                req->getPaddr(), *(inst->memData),
613                inst->seqNum);
614
615        // @todo: Remove this SC hack once the memory system handles it.
616        if (req->isLocked()) {
617            if (req->isUncacheable()) {
618                req->setScResult(2);
619            } else {
620                if (cpu->lockFlag) {
621                    req->setScResult(1);
622                    DPRINTF(LSQUnit, "Store conditional [sn:%lli] succeeded.",
623                            inst->seqNum);
624                } else {
625                    req->setScResult(0);
626                    // Hack: Instantly complete this store.
627//                    completeDataAccess(data_pkt);
628                    DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed.  "
629                            "Instantly completing it.\n",
630                            inst->seqNum);
631                    WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
632                    wb->schedule(curTick + 1);
633                    delete state;
634                    completeStore(storeWBIdx);
635                    incrStIdx(storeWBIdx);
636                    continue;
637                }
638            }
639        } else {
640            // Non-store conditionals do not need a writeback.
641            state->noWB = true;
642        }
643
644        if (!dcachePort->sendTiming(data_pkt)) {
645            if (data_pkt->result == Packet::BadAddress) {
646                panic("LSQ sent out a bad address for a completed store!");
647            }
648            // Need to handle becoming blocked on a store.
649            DPRINTF(IEW, "D-Cache became blcoked when writing [sn:%lli], will"
650                    "retry later\n",
651                    inst->seqNum);
652            isStoreBlocked = true;
653            ++lsqCacheBlocked;
654            assert(retryPkt == NULL);
655            retryPkt = data_pkt;
656            lsq->setRetryTid(lsqID);
657        } else {
658            storePostSend(data_pkt);
659        }
660    }
661
662    // Not sure this should set it to 0.
663    usedPorts = 0;
664
665    assert(stores >= 0 && storesToWB >= 0);
666}
667
668/*template <class Impl>
669void
670LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
671{
672    list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
673                                              mshrSeqNums.end(),
674                                              seqNum);
675
676    if (mshr_it != mshrSeqNums.end()) {
677        mshrSeqNums.erase(mshr_it);
678        DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
679    }
680}*/
681
682template <class Impl>
683void
684LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
685{
686    DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
687            "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
688
689    int load_idx = loadTail;
690    decrLdIdx(load_idx);
691
692    while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
693        DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
694                "[sn:%lli]\n",
695                loadQueue[load_idx]->readPC(),
696                loadQueue[load_idx]->seqNum);
697
698        if (isStalled() && load_idx == stallingLoadIdx) {
699            stalled = false;
700            stallingStoreIsn = 0;
701            stallingLoadIdx = 0;
702        }
703
704        // Clear the smart pointer to make sure it is decremented.
705        loadQueue[load_idx]->setSquashed();
706        loadQueue[load_idx] = NULL;
707        --loads;
708
709        // Inefficient!
710        loadTail = load_idx;
711
712        decrLdIdx(load_idx);
713        ++lsqSquashedLoads;
714    }
715
716    if (isLoadBlocked) {
717        if (squashed_num < blockedLoadSeqNum) {
718            isLoadBlocked = false;
719            loadBlockedHandled = false;
720            blockedLoadSeqNum = 0;
721        }
722    }
723
724    int store_idx = storeTail;
725    decrStIdx(store_idx);
726
727    while (stores != 0 &&
728           storeQueue[store_idx].inst->seqNum > squashed_num) {
729        // Instructions marked as can WB are already committed.
730        if (storeQueue[store_idx].canWB) {
731            break;
732        }
733
734        DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
735                "idx:%i [sn:%lli]\n",
736                storeQueue[store_idx].inst->readPC(),
737                store_idx, storeQueue[store_idx].inst->seqNum);
738
739        // I don't think this can happen.  It should have been cleared
740        // by the stalling load.
741        if (isStalled() &&
742            storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
743            panic("Is stalled should have been cleared by stalling load!\n");
744            stalled = false;
745            stallingStoreIsn = 0;
746        }
747
748        // Clear the smart pointer to make sure it is decremented.
749        storeQueue[store_idx].inst->setSquashed();
750        storeQueue[store_idx].inst = NULL;
751        storeQueue[store_idx].canWB = 0;
752
753        storeQueue[store_idx].req = NULL;
754        --stores;
755
756        // Inefficient!
757        storeTail = store_idx;
758
759        decrStIdx(store_idx);
760        ++lsqSquashedStores;
761    }
762}
763
764template <class Impl>
765void
766LSQUnit<Impl>::storePostSend(PacketPtr pkt)
767{
768    if (isStalled() &&
769        storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
770        DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
771                "load idx:%i\n",
772                stallingStoreIsn, stallingLoadIdx);
773        stalled = false;
774        stallingStoreIsn = 0;
775        iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
776    }
777
778    if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
779        // The store is basically completed at this time. This
780        // only works so long as the checker doesn't try to
781        // verify the value in memory for stores.
782        storeQueue[storeWBIdx].inst->setCompleted();
783#if USE_CHECKER
784        if (cpu->checker) {
785            cpu->checker->verify(storeQueue[storeWBIdx].inst);
786        }
787#endif
788    }
789
790    if (pkt->result != Packet::Success) {
791        DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
792                storeWBIdx);
793
794        DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
795                storeQueue[storeWBIdx].inst->seqNum);
796
797        //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
798
799        //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
800
801        // @todo: Increment stat here.
802    } else {
803        DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
804                storeWBIdx);
805
806        DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
807                storeQueue[storeWBIdx].inst->seqNum);
808    }
809
810    incrStIdx(storeWBIdx);
811}
812
813template <class Impl>
814void
815LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
816{
817    iewStage->wakeCPU();
818
819    // Squashed instructions do not need to complete their access.
820    if (inst->isSquashed()) {
821        iewStage->decrWb(inst->seqNum);
822        assert(!inst->isStore());
823        ++lsqIgnoredResponses;
824        return;
825    }
826
827    if (!inst->isExecuted()) {
828        inst->setExecuted();
829
830        // Complete access to copy data to proper place.
831        inst->completeAcc(pkt);
832    }
833
834    // Need to insert instruction into queue to commit
835    iewStage->instToCommit(inst);
836
837    iewStage->activityThisCycle();
838}
839
840template <class Impl>
841void
842LSQUnit<Impl>::completeStore(int store_idx)
843{
844    assert(storeQueue[store_idx].inst);
845    storeQueue[store_idx].completed = true;
846    --storesToWB;
847    // A bit conservative because a store completion may not free up entries,
848    // but hopefully avoids two store completions in one cycle from making
849    // the CPU tick twice.
850    cpu->wakeCPU();
851    cpu->activityThisCycle();
852
853    if (store_idx == storeHead) {
854        do {
855            incrStIdx(storeHead);
856
857            --stores;
858        } while (storeQueue[storeHead].completed &&
859                 storeHead != storeTail);
860
861        iewStage->updateLSQNextCycle = true;
862    }
863
864    DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
865            "idx:%i\n",
866            storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
867
868    if (isStalled() &&
869        storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
870        DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
871                "load idx:%i\n",
872                stallingStoreIsn, stallingLoadIdx);
873        stalled = false;
874        stallingStoreIsn = 0;
875        iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
876    }
877
878    storeQueue[store_idx].inst->setCompleted();
879
880    // Tell the checker we've completed this instruction.  Some stores
881    // may get reported twice to the checker, but the checker can
882    // handle that case.
883#if USE_CHECKER
884    if (cpu->checker) {
885        cpu->checker->verify(storeQueue[store_idx].inst);
886    }
887#endif
888}
889
890template <class Impl>
891void
892LSQUnit<Impl>::recvRetry()
893{
894    if (isStoreBlocked) {
895        assert(retryPkt != NULL);
896
897        if (dcachePort->sendTiming(retryPkt)) {
898            if (retryPkt->result == Packet::BadAddress) {
899                panic("LSQ sent out a bad address for a completed store!");
900            }
901            storePostSend(retryPkt);
902            retryPkt = NULL;
903            isStoreBlocked = false;
904            lsq->setRetryTid(-1);
905        } else {
906            // Still blocked!
907            ++lsqCacheBlocked;
908            lsq->setRetryTid(lsqID);
909        }
910    } else if (isLoadBlocked) {
911        DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
912                "no need to resend packet.\n");
913    } else {
914        DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
915    }
916}
917
918template <class Impl>
919inline void
920LSQUnit<Impl>::incrStIdx(int &store_idx)
921{
922    if (++store_idx >= SQEntries)
923        store_idx = 0;
924}
925
926template <class Impl>
927inline void
928LSQUnit<Impl>::decrStIdx(int &store_idx)
929{
930    if (--store_idx < 0)
931        store_idx += SQEntries;
932}
933
934template <class Impl>
935inline void
936LSQUnit<Impl>::incrLdIdx(int &load_idx)
937{
938    if (++load_idx >= LQEntries)
939        load_idx = 0;
940}
941
942template <class Impl>
943inline void
944LSQUnit<Impl>::decrLdIdx(int &load_idx)
945{
946    if (--load_idx < 0)
947        load_idx += LQEntries;
948}
949
950template <class Impl>
951void
952LSQUnit<Impl>::dumpInsts()
953{
954    cprintf("Load store queue: Dumping instructions.\n");
955    cprintf("Load queue size: %i\n", loads);
956    cprintf("Load queue: ");
957
958    int load_idx = loadHead;
959
960    while (load_idx != loadTail && loadQueue[load_idx]) {
961        cprintf("%#x ", loadQueue[load_idx]->readPC());
962
963        incrLdIdx(load_idx);
964    }
965
966    cprintf("Store queue size: %i\n", stores);
967    cprintf("Store queue: ");
968
969    int store_idx = storeHead;
970
971    while (store_idx != storeTail && storeQueue[store_idx].inst) {
972        cprintf("%#x ", storeQueue[store_idx].inst->readPC());
973
974        incrStIdx(store_idx);
975    }
976
977    cprintf("\n");
978}
979