lsq_unit_impl.hh revision 2698 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include "cpu/checker/cpu.hh"
33#include "cpu/o3/lsq_unit.hh"
34#include "base/str.hh"
35#include "mem/request.hh"
36
37template<class Impl>
38LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
39                                              LSQUnit *lsq_ptr)
40    : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
41{
42    this->setFlags(Event::AutoDelete);
43}
44
45template<class Impl>
46void
47LSQUnit<Impl>::WritebackEvent::process()
48{
49    if (!lsqPtr->isSwitchedOut()) {
50        lsqPtr->writeback(inst, pkt);
51    }
52    delete pkt;
53}
54
55template<class Impl>
56const char *
57LSQUnit<Impl>::WritebackEvent::description()
58{
59    return "Store writeback event";
60}
61
62template<class Impl>
63void
64LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
65{
66    LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
67    DynInstPtr inst = state->inst;
68    DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
69    DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
70
71    //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
72
73    if (isSwitchedOut() || inst->isSquashed()) {
74        delete state;
75        delete pkt;
76        return;
77    } else {
78        if (!state->noWB) {
79            writeback(inst, pkt);
80        }
81
82        if (inst->isStore()) {
83            completeStore(state->idx);
84        }
85    }
86
87    delete state;
88    delete pkt;
89}
90
91template <class Impl>
92Tick
93LSQUnit<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
94{
95    panic("O3CPU model does not work with atomic mode!");
96    return curTick;
97}
98
99template <class Impl>
100void
101LSQUnit<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
102{
103    panic("O3CPU doesn't expect recvFunctional callback!");
104}
105
106template <class Impl>
107void
108LSQUnit<Impl>::DcachePort::recvStatusChange(Status status)
109{
110    if (status == RangeChange)
111        return;
112
113    panic("O3CPU doesn't expect recvStatusChange callback!");
114}
115
116template <class Impl>
117bool
118LSQUnit<Impl>::DcachePort::recvTiming(PacketPtr pkt)
119{
120    lsq->completeDataAccess(pkt);
121    return true;
122}
123
124template <class Impl>
125void
126LSQUnit<Impl>::DcachePort::recvRetry()
127{
128    lsq->recvRetry();
129}
130
131template <class Impl>
132LSQUnit<Impl>::LSQUnit()
133    : loads(0), stores(0), storesToWB(0), stalled(false),
134      isStoreBlocked(false), isLoadBlocked(false),
135      loadBlockedHandled(false)
136{
137}
138
139template<class Impl>
140void
141LSQUnit<Impl>::init(Params *params, unsigned maxLQEntries,
142                    unsigned maxSQEntries, unsigned id)
143{
144    DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
145
146    switchedOut = false;
147
148    lsqID = id;
149
150    // Add 1 for the sentinel entry (they are circular queues).
151    LQEntries = maxLQEntries + 1;
152    SQEntries = maxSQEntries + 1;
153
154    loadQueue.resize(LQEntries);
155    storeQueue.resize(SQEntries);
156
157    loadHead = loadTail = 0;
158
159    storeHead = storeWBIdx = storeTail = 0;
160
161    usedPorts = 0;
162    cachePorts = params->cachePorts;
163
164    mem = params->mem;
165
166    memDepViolator = NULL;
167
168    blockedLoadSeqNum = 0;
169}
170
171template<class Impl>
172void
173LSQUnit<Impl>::setCPU(FullCPU *cpu_ptr)
174{
175    cpu = cpu_ptr;
176    dcachePort = new DcachePort(cpu, this);
177
178    Port *mem_dport = mem->getPort("");
179    dcachePort->setPeer(mem_dport);
180    mem_dport->setPeer(dcachePort);
181
182    if (cpu->checker) {
183        cpu->checker->setDcachePort(dcachePort);
184    }
185}
186
187template<class Impl>
188std::string
189LSQUnit<Impl>::name() const
190{
191    if (Impl::MaxThreads == 1) {
192        return iewStage->name() + ".lsq";
193    } else {
194        return iewStage->name() + ".lsq.thread." + to_string(lsqID);
195    }
196}
197
198template<class Impl>
199void
200LSQUnit<Impl>::clearLQ()
201{
202    loadQueue.clear();
203}
204
205template<class Impl>
206void
207LSQUnit<Impl>::clearSQ()
208{
209    storeQueue.clear();
210}
211
212template<class Impl>
213void
214LSQUnit<Impl>::switchOut()
215{
216    switchedOut = true;
217    for (int i = 0; i < loadQueue.size(); ++i)
218        loadQueue[i] = NULL;
219
220    assert(storesToWB == 0);
221}
222
223template<class Impl>
224void
225LSQUnit<Impl>::takeOverFrom()
226{
227    switchedOut = false;
228    loads = stores = storesToWB = 0;
229
230    loadHead = loadTail = 0;
231
232    storeHead = storeWBIdx = storeTail = 0;
233
234    usedPorts = 0;
235
236    memDepViolator = NULL;
237
238    blockedLoadSeqNum = 0;
239
240    stalled = false;
241    isLoadBlocked = false;
242    loadBlockedHandled = false;
243}
244
245template<class Impl>
246void
247LSQUnit<Impl>::resizeLQ(unsigned size)
248{
249    unsigned size_plus_sentinel = size + 1;
250    assert(size_plus_sentinel >= LQEntries);
251
252    if (size_plus_sentinel > LQEntries) {
253        while (size_plus_sentinel > loadQueue.size()) {
254            DynInstPtr dummy;
255            loadQueue.push_back(dummy);
256            LQEntries++;
257        }
258    } else {
259        LQEntries = size_plus_sentinel;
260    }
261
262}
263
264template<class Impl>
265void
266LSQUnit<Impl>::resizeSQ(unsigned size)
267{
268    unsigned size_plus_sentinel = size + 1;
269    if (size_plus_sentinel > SQEntries) {
270        while (size_plus_sentinel > storeQueue.size()) {
271            SQEntry dummy;
272            storeQueue.push_back(dummy);
273            SQEntries++;
274        }
275    } else {
276        SQEntries = size_plus_sentinel;
277    }
278}
279
280template <class Impl>
281void
282LSQUnit<Impl>::insert(DynInstPtr &inst)
283{
284    assert(inst->isMemRef());
285
286    assert(inst->isLoad() || inst->isStore());
287
288    if (inst->isLoad()) {
289        insertLoad(inst);
290    } else {
291        insertStore(inst);
292    }
293
294    inst->setInLSQ();
295}
296
297template <class Impl>
298void
299LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
300{
301    assert((loadTail + 1) % LQEntries != loadHead);
302    assert(loads < LQEntries);
303
304    DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
305            load_inst->readPC(), loadTail, load_inst->seqNum);
306
307    load_inst->lqIdx = loadTail;
308
309    if (stores == 0) {
310        load_inst->sqIdx = -1;
311    } else {
312        load_inst->sqIdx = storeTail;
313    }
314
315    loadQueue[loadTail] = load_inst;
316
317    incrLdIdx(loadTail);
318
319    ++loads;
320}
321
322template <class Impl>
323void
324LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
325{
326    // Make sure it is not full before inserting an instruction.
327    assert((storeTail + 1) % SQEntries != storeHead);
328    assert(stores < SQEntries);
329
330    DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
331            store_inst->readPC(), storeTail, store_inst->seqNum);
332
333    store_inst->sqIdx = storeTail;
334    store_inst->lqIdx = loadTail;
335
336    storeQueue[storeTail] = SQEntry(store_inst);
337
338    incrStIdx(storeTail);
339
340    ++stores;
341}
342
343template <class Impl>
344typename Impl::DynInstPtr
345LSQUnit<Impl>::getMemDepViolator()
346{
347    DynInstPtr temp = memDepViolator;
348
349    memDepViolator = NULL;
350
351    return temp;
352}
353
354template <class Impl>
355unsigned
356LSQUnit<Impl>::numFreeEntries()
357{
358    unsigned free_lq_entries = LQEntries - loads;
359    unsigned free_sq_entries = SQEntries - stores;
360
361    // Both the LQ and SQ entries have an extra dummy entry to differentiate
362    // empty/full conditions.  Subtract 1 from the free entries.
363    if (free_lq_entries < free_sq_entries) {
364        return free_lq_entries - 1;
365    } else {
366        return free_sq_entries - 1;
367    }
368}
369
370template <class Impl>
371int
372LSQUnit<Impl>::numLoadsReady()
373{
374    int load_idx = loadHead;
375    int retval = 0;
376
377    while (load_idx != loadTail) {
378        assert(loadQueue[load_idx]);
379
380        if (loadQueue[load_idx]->readyToIssue()) {
381            ++retval;
382        }
383    }
384
385    return retval;
386}
387
388template <class Impl>
389Fault
390LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
391{
392    // Execute a specific load.
393    Fault load_fault = NoFault;
394
395    DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
396            inst->readPC(),inst->seqNum);
397
398    load_fault = inst->initiateAcc();
399
400    // If the instruction faulted, then we need to send it along to commit
401    // without the instruction completing.
402    if (load_fault != NoFault) {
403        // Send this instruction to commit, also make sure iew stage
404        // realizes there is activity.
405        iewStage->instToCommit(inst);
406        iewStage->activityThisCycle();
407    }
408
409    return load_fault;
410}
411
412template <class Impl>
413Fault
414LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
415{
416    using namespace TheISA;
417    // Make sure that a store exists.
418    assert(stores != 0);
419
420    int store_idx = store_inst->sqIdx;
421
422    DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
423            store_inst->readPC(), store_inst->seqNum);
424
425    // Check the recently completed loads to see if any match this store's
426    // address.  If so, then we have a memory ordering violation.
427    int load_idx = store_inst->lqIdx;
428
429    Fault store_fault = store_inst->initiateAcc();
430
431    if (storeQueue[store_idx].size == 0) {
432        DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
433                store_inst->readPC(),store_inst->seqNum);
434
435        return store_fault;
436    }
437
438    assert(store_fault == NoFault);
439
440    if (store_inst->isStoreConditional()) {
441        // Store conditionals need to set themselves as able to
442        // writeback if we haven't had a fault by here.
443        storeQueue[store_idx].canWB = true;
444
445        ++storesToWB;
446    }
447
448    if (!memDepViolator) {
449        while (load_idx != loadTail) {
450            // Really only need to check loads that have actually executed
451            // It's safe to check all loads because effAddr is set to
452            // InvalAddr when the dyn inst is created.
453
454            // @todo: For now this is extra conservative, detecting a
455            // violation if the addresses match assuming all accesses
456            // are quad word accesses.
457
458            // @todo: Fix this, magic number being used here
459            if ((loadQueue[load_idx]->effAddr >> 8) ==
460                (store_inst->effAddr >> 8)) {
461                // A load incorrectly passed this store.  Squash and refetch.
462                // For now return a fault to show that it was unsuccessful.
463                memDepViolator = loadQueue[load_idx];
464
465                return genMachineCheckFault();
466            }
467
468            incrLdIdx(load_idx);
469        }
470
471        // If we've reached this point, there was no violation.
472        memDepViolator = NULL;
473    }
474
475    return store_fault;
476}
477
478template <class Impl>
479void
480LSQUnit<Impl>::commitLoad()
481{
482    assert(loadQueue[loadHead]);
483
484    DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
485            loadQueue[loadHead]->readPC());
486
487    loadQueue[loadHead] = NULL;
488
489    incrLdIdx(loadHead);
490
491    --loads;
492}
493
494template <class Impl>
495void
496LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
497{
498    assert(loads == 0 || loadQueue[loadHead]);
499
500    while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
501        commitLoad();
502    }
503}
504
505template <class Impl>
506void
507LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
508{
509    assert(stores == 0 || storeQueue[storeHead].inst);
510
511    int store_idx = storeHead;
512
513    while (store_idx != storeTail) {
514        assert(storeQueue[store_idx].inst);
515        // Mark any stores that are now committed and have not yet
516        // been marked as able to write back.
517        if (!storeQueue[store_idx].canWB) {
518            if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
519                break;
520            }
521            DPRINTF(LSQUnit, "Marking store as able to write back, PC "
522                    "%#x [sn:%lli]\n",
523                    storeQueue[store_idx].inst->readPC(),
524                    storeQueue[store_idx].inst->seqNum);
525
526            storeQueue[store_idx].canWB = true;
527
528            ++storesToWB;
529        }
530
531        incrStIdx(store_idx);
532    }
533}
534
535template <class Impl>
536void
537LSQUnit<Impl>::writebackStores()
538{
539    while (storesToWB > 0 &&
540           storeWBIdx != storeTail &&
541           storeQueue[storeWBIdx].inst &&
542           storeQueue[storeWBIdx].canWB &&
543           usedPorts < cachePorts) {
544
545        if (isStoreBlocked) {
546            DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
547                    " is blocked!\n");
548            break;
549        }
550
551        // Store didn't write any data so no need to write it back to
552        // memory.
553        if (storeQueue[storeWBIdx].size == 0) {
554            completeStore(storeWBIdx);
555
556            incrStIdx(storeWBIdx);
557
558            continue;
559        }
560
561        ++usedPorts;
562
563        if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
564            incrStIdx(storeWBIdx);
565
566            continue;
567        }
568
569        assert(storeQueue[storeWBIdx].req);
570        assert(!storeQueue[storeWBIdx].committed);
571
572        DynInstPtr inst = storeQueue[storeWBIdx].inst;
573
574        Request *req = storeQueue[storeWBIdx].req;
575        storeQueue[storeWBIdx].committed = true;
576
577        assert(!inst->memData);
578        inst->memData = new uint8_t[64];
579        memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data,
580               req->getSize());
581
582        PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
583        data_pkt->dataStatic(inst->memData);
584
585        LSQSenderState *state = new LSQSenderState;
586        state->isLoad = false;
587        state->idx = storeWBIdx;
588        state->inst = inst;
589        data_pkt->senderState = state;
590
591        DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
592                "to Addr:%#x, data:%#x [sn:%lli]\n",
593                storeWBIdx, storeQueue[storeWBIdx].inst->readPC(),
594                req->getPaddr(), *(inst->memData),
595                storeQueue[storeWBIdx].inst->seqNum);
596
597        // @todo: Remove this SC hack once the memory system handles it.
598        if (req->getFlags() & LOCKED) {
599            if (req->getFlags() & UNCACHEABLE) {
600                req->setScResult(2);
601            } else {
602                if (cpu->lockFlag) {
603                    req->setScResult(1);
604                } else {
605                    req->setScResult(0);
606                    // Hack: Instantly complete this store.
607                    completeDataAccess(data_pkt);
608                    incrStIdx(storeWBIdx);
609                    continue;
610                }
611            }
612        } else {
613            // Non-store conditionals do not need a writeback.
614            state->noWB = true;
615        }
616
617        if (!dcachePort->sendTiming(data_pkt)) {
618            // Need to handle becoming blocked on a store.
619            isStoreBlocked = true;
620
621            assert(retryPkt == NULL);
622            retryPkt = data_pkt;
623        } else {
624            storePostSend(data_pkt);
625        }
626    }
627
628    // Not sure this should set it to 0.
629    usedPorts = 0;
630
631    assert(stores >= 0 && storesToWB >= 0);
632}
633
634/*template <class Impl>
635void
636LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
637{
638    list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
639                                              mshrSeqNums.end(),
640                                              seqNum);
641
642    if (mshr_it != mshrSeqNums.end()) {
643        mshrSeqNums.erase(mshr_it);
644        DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
645    }
646}*/
647
648template <class Impl>
649void
650LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
651{
652    DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
653            "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
654
655    int load_idx = loadTail;
656    decrLdIdx(load_idx);
657
658    while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
659        DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
660                "[sn:%lli]\n",
661                loadQueue[load_idx]->readPC(),
662                loadQueue[load_idx]->seqNum);
663
664        if (isStalled() && load_idx == stallingLoadIdx) {
665            stalled = false;
666            stallingStoreIsn = 0;
667            stallingLoadIdx = 0;
668        }
669
670        // Clear the smart pointer to make sure it is decremented.
671        loadQueue[load_idx]->squashed = true;
672        loadQueue[load_idx] = NULL;
673        --loads;
674
675        // Inefficient!
676        loadTail = load_idx;
677
678        decrLdIdx(load_idx);
679    }
680
681    if (isLoadBlocked) {
682        if (squashed_num < blockedLoadSeqNum) {
683            isLoadBlocked = false;
684            loadBlockedHandled = false;
685            blockedLoadSeqNum = 0;
686        }
687    }
688
689    int store_idx = storeTail;
690    decrStIdx(store_idx);
691
692    while (stores != 0 &&
693           storeQueue[store_idx].inst->seqNum > squashed_num) {
694        // Instructions marked as can WB are already committed.
695        if (storeQueue[store_idx].canWB) {
696            break;
697        }
698
699        DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
700                "idx:%i [sn:%lli]\n",
701                storeQueue[store_idx].inst->readPC(),
702                store_idx, storeQueue[store_idx].inst->seqNum);
703
704        // I don't think this can happen.  It should have been cleared
705        // by the stalling load.
706        if (isStalled() &&
707            storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
708            panic("Is stalled should have been cleared by stalling load!\n");
709            stalled = false;
710            stallingStoreIsn = 0;
711        }
712
713        // Clear the smart pointer to make sure it is decremented.
714        storeQueue[store_idx].inst->squashed = true;
715        storeQueue[store_idx].inst = NULL;
716        storeQueue[store_idx].canWB = 0;
717
718        storeQueue[store_idx].req = NULL;
719        --stores;
720
721        // Inefficient!
722        storeTail = store_idx;
723
724        decrStIdx(store_idx);
725    }
726}
727
728template <class Impl>
729void
730LSQUnit<Impl>::storePostSend(Packet *pkt)
731{
732    if (isStalled() &&
733        storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
734        DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
735                "load idx:%i\n",
736                stallingStoreIsn, stallingLoadIdx);
737        stalled = false;
738        stallingStoreIsn = 0;
739        iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
740    }
741
742    if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
743        // The store is basically completed at this time. This
744        // only works so long as the checker doesn't try to
745        // verify the value in memory for stores.
746        storeQueue[storeWBIdx].inst->setCompleted();
747        if (cpu->checker) {
748            cpu->checker->tick(storeQueue[storeWBIdx].inst);
749        }
750    }
751
752    if (pkt->result != Packet::Success) {
753        DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
754                storeWBIdx);
755
756        DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
757                storeQueue[storeWBIdx].inst->seqNum);
758
759        //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
760
761        //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
762
763        // @todo: Increment stat here.
764    } else {
765        DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
766                storeWBIdx);
767
768        DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
769                storeQueue[storeWBIdx].inst->seqNum);
770    }
771
772    incrStIdx(storeWBIdx);
773}
774
775template <class Impl>
776void
777LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
778{
779    iewStage->wakeCPU();
780
781    // Squashed instructions do not need to complete their access.
782    if (inst->isSquashed()) {
783        assert(!inst->isStore());
784        return;
785    }
786
787    if (!inst->isExecuted()) {
788        inst->setExecuted();
789
790        // Complete access to copy data to proper place.
791        inst->completeAcc(pkt);
792    }
793
794    // Need to insert instruction into queue to commit
795    iewStage->instToCommit(inst);
796
797    iewStage->activityThisCycle();
798}
799
800template <class Impl>
801void
802LSQUnit<Impl>::completeStore(int store_idx)
803{
804    assert(storeQueue[store_idx].inst);
805    storeQueue[store_idx].completed = true;
806    --storesToWB;
807    // A bit conservative because a store completion may not free up entries,
808    // but hopefully avoids two store completions in one cycle from making
809    // the CPU tick twice.
810    cpu->activityThisCycle();
811
812    if (store_idx == storeHead) {
813        do {
814            incrStIdx(storeHead);
815
816            --stores;
817        } while (storeQueue[storeHead].completed &&
818                 storeHead != storeTail);
819
820        iewStage->updateLSQNextCycle = true;
821    }
822
823    DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
824            "idx:%i\n",
825            storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
826
827    if (isStalled() &&
828        storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
829        DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
830                "load idx:%i\n",
831                stallingStoreIsn, stallingLoadIdx);
832        stalled = false;
833        stallingStoreIsn = 0;
834        iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
835    }
836
837    storeQueue[store_idx].inst->setCompleted();
838
839    // Tell the checker we've completed this instruction.  Some stores
840    // may get reported twice to the checker, but the checker can
841    // handle that case.
842    if (cpu->checker) {
843        cpu->checker->tick(storeQueue[store_idx].inst);
844    }
845}
846
847template <class Impl>
848void
849LSQUnit<Impl>::recvRetry()
850{
851    if (isStoreBlocked) {
852        assert(retryPkt != NULL);
853
854        if (dcachePort->sendTiming(retryPkt)) {
855            storePostSend(retryPkt);
856            sendingPkt = NULL;
857            isStoreBlocked = false;
858        } else {
859            // Still blocked!
860        }
861    } else if (isLoadBlocked) {
862        DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
863                "no need to resend packet.\n");
864    } else {
865        DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
866    }
867}
868
869template <class Impl>
870inline void
871LSQUnit<Impl>::incrStIdx(int &store_idx)
872{
873    if (++store_idx >= SQEntries)
874        store_idx = 0;
875}
876
877template <class Impl>
878inline void
879LSQUnit<Impl>::decrStIdx(int &store_idx)
880{
881    if (--store_idx < 0)
882        store_idx += SQEntries;
883}
884
885template <class Impl>
886inline void
887LSQUnit<Impl>::incrLdIdx(int &load_idx)
888{
889    if (++load_idx >= LQEntries)
890        load_idx = 0;
891}
892
893template <class Impl>
894inline void
895LSQUnit<Impl>::decrLdIdx(int &load_idx)
896{
897    if (--load_idx < 0)
898        load_idx += LQEntries;
899}
900
901template <class Impl>
902void
903LSQUnit<Impl>::dumpInsts()
904{
905    cprintf("Load store queue: Dumping instructions.\n");
906    cprintf("Load queue size: %i\n", loads);
907    cprintf("Load queue: ");
908
909    int load_idx = loadHead;
910
911    while (load_idx != loadTail && loadQueue[load_idx]) {
912        cprintf("%#x ", loadQueue[load_idx]->readPC());
913
914        incrLdIdx(load_idx);
915    }
916
917    cprintf("Store queue size: %i\n", stores);
918    cprintf("Store queue: ");
919
920    int store_idx = storeHead;
921
922    while (store_idx != storeTail && storeQueue[store_idx].inst) {
923        cprintf("%#x ", storeQueue[store_idx].inst->readPC());
924
925        incrStIdx(store_idx);
926    }
927
928    cprintf("\n");
929}
930