lsq_unit_impl.hh revision 2679:737e9f158843
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include "cpu/checker/cpu.hh" 30#include "cpu/o3/lsq_unit.hh" 31#include "base/str.hh" 32#include "mem/request.hh" 33 34template<class Impl> 35LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 36 LSQUnit *lsq_ptr) 37 : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 38{ 39 this->setFlags(Event::AutoDelete); 40} 41 42template<class Impl> 43void 44LSQUnit<Impl>::WritebackEvent::process() 45{ 46 if (!lsqPtr->isSwitchedOut()) { 47 lsqPtr->writeback(inst, pkt); 48 } 49 delete pkt; 50} 51 52template<class Impl> 53const char * 54LSQUnit<Impl>::WritebackEvent::description() 55{ 56 return "Store writeback event"; 57} 58 59template<class Impl> 60void 61LSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 62{ 63 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 64 DynInstPtr inst = state->inst; 65 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum); 66// DPRINTF(Activity, "Activity: Ld Writeback event [sn:%lli]\n", inst->seqNum); 67 68 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 69 70 if (isSwitchedOut() || inst->isSquashed()) { 71 delete state; 72 delete pkt; 73 return; 74 } else { 75 if (!state->noWB) { 76 writeback(inst, pkt); 77 } 78 79 if (inst->isStore()) { 80 completeStore(state->idx); 81 } 82 } 83 84 delete state; 85 delete pkt; 86} 87 88template <class Impl> 89Tick 90LSQUnit<Impl>::DcachePort::recvAtomic(PacketPtr pkt) 91{ 92 panic("O3CPU model does not work with atomic mode!"); 93 return curTick; 94} 95 96template <class Impl> 97void 98LSQUnit<Impl>::DcachePort::recvFunctional(PacketPtr pkt) 99{ 100 panic("O3CPU doesn't expect recvFunctional callback!"); 101} 102 103template <class Impl> 104void 105LSQUnit<Impl>::DcachePort::recvStatusChange(Status status) 106{ 107 if (status == RangeChange) 108 return; 109 110 panic("O3CPU doesn't expect recvStatusChange callback!"); 111} 112 113template <class Impl> 114bool 115LSQUnit<Impl>::DcachePort::recvTiming(PacketPtr pkt) 116{ 117 lsq->completeDataAccess(pkt); 118 return true; 119} 120 121template <class Impl> 122void 123LSQUnit<Impl>::DcachePort::recvRetry() 124{ 125 panic("Retry unsupported for now!"); 126 // we shouldn't get a retry unless we have a packet that we're 127 // waiting to transmit 128/* 129 assert(cpu->dcache_pkt != NULL); 130 assert(cpu->_status == DcacheRetry); 131 PacketPtr tmp = cpu->dcache_pkt; 132 if (sendTiming(tmp)) { 133 cpu->_status = DcacheWaitResponse; 134 cpu->dcache_pkt = NULL; 135 } 136*/ 137} 138 139template <class Impl> 140LSQUnit<Impl>::LSQUnit() 141 : loads(0), stores(0), storesToWB(0), stalled(false), 142 isStoreBlocked(false), isLoadBlocked(false), 143 loadBlockedHandled(false) 144{ 145} 146 147template<class Impl> 148void 149LSQUnit<Impl>::init(Params *params, unsigned maxLQEntries, 150 unsigned maxSQEntries, unsigned id) 151{ 152 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 153 154 switchedOut = false; 155 156 lsqID = id; 157 158 // Add 1 for the sentinel entry (they are circular queues). 159 LQEntries = maxLQEntries + 1; 160 SQEntries = maxSQEntries + 1; 161 162 loadQueue.resize(LQEntries); 163 storeQueue.resize(SQEntries); 164 165 loadHead = loadTail = 0; 166 167 storeHead = storeWBIdx = storeTail = 0; 168 169 usedPorts = 0; 170 cachePorts = params->cachePorts; 171 172 mem = params->mem; 173 174 memDepViolator = NULL; 175 176 blockedLoadSeqNum = 0; 177} 178 179template<class Impl> 180void 181LSQUnit<Impl>::setCPU(FullCPU *cpu_ptr) 182{ 183 cpu = cpu_ptr; 184 dcachePort = new DcachePort(cpu, this); 185 186 Port *mem_dport = mem->getPort(""); 187 dcachePort->setPeer(mem_dport); 188 mem_dport->setPeer(dcachePort); 189 190 if (cpu->checker) { 191 cpu->checker->setDcachePort(dcachePort); 192 } 193} 194 195template<class Impl> 196std::string 197LSQUnit<Impl>::name() const 198{ 199 if (Impl::MaxThreads == 1) { 200 return iewStage->name() + ".lsq"; 201 } else { 202 return iewStage->name() + ".lsq.thread." + to_string(lsqID); 203 } 204} 205 206template<class Impl> 207void 208LSQUnit<Impl>::clearLQ() 209{ 210 loadQueue.clear(); 211} 212 213template<class Impl> 214void 215LSQUnit<Impl>::clearSQ() 216{ 217 storeQueue.clear(); 218} 219 220#if 0 221template<class Impl> 222void 223LSQUnit<Impl>::setPageTable(PageTable *pt_ptr) 224{ 225 DPRINTF(LSQUnit, "Setting the page table pointer.\n"); 226 pTable = pt_ptr; 227} 228#endif 229 230template<class Impl> 231void 232LSQUnit<Impl>::switchOut() 233{ 234 switchedOut = true; 235 for (int i = 0; i < loadQueue.size(); ++i) 236 loadQueue[i] = NULL; 237 238 assert(storesToWB == 0); 239} 240 241template<class Impl> 242void 243LSQUnit<Impl>::takeOverFrom() 244{ 245 switchedOut = false; 246 loads = stores = storesToWB = 0; 247 248 loadHead = loadTail = 0; 249 250 storeHead = storeWBIdx = storeTail = 0; 251 252 usedPorts = 0; 253 254 memDepViolator = NULL; 255 256 blockedLoadSeqNum = 0; 257 258 stalled = false; 259 isLoadBlocked = false; 260 loadBlockedHandled = false; 261} 262 263template<class Impl> 264void 265LSQUnit<Impl>::resizeLQ(unsigned size) 266{ 267 unsigned size_plus_sentinel = size + 1; 268 assert(size_plus_sentinel >= LQEntries); 269 270 if (size_plus_sentinel > LQEntries) { 271 while (size_plus_sentinel > loadQueue.size()) { 272 DynInstPtr dummy; 273 loadQueue.push_back(dummy); 274 LQEntries++; 275 } 276 } else { 277 LQEntries = size_plus_sentinel; 278 } 279 280} 281 282template<class Impl> 283void 284LSQUnit<Impl>::resizeSQ(unsigned size) 285{ 286 unsigned size_plus_sentinel = size + 1; 287 if (size_plus_sentinel > SQEntries) { 288 while (size_plus_sentinel > storeQueue.size()) { 289 SQEntry dummy; 290 storeQueue.push_back(dummy); 291 SQEntries++; 292 } 293 } else { 294 SQEntries = size_plus_sentinel; 295 } 296} 297 298template <class Impl> 299void 300LSQUnit<Impl>::insert(DynInstPtr &inst) 301{ 302 assert(inst->isMemRef()); 303 304 assert(inst->isLoad() || inst->isStore()); 305 306 if (inst->isLoad()) { 307 insertLoad(inst); 308 } else { 309 insertStore(inst); 310 } 311 312 inst->setInLSQ(); 313} 314 315template <class Impl> 316void 317LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 318{ 319 assert((loadTail + 1) % LQEntries != loadHead); 320 assert(loads < LQEntries); 321 322 DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n", 323 load_inst->readPC(), loadTail, load_inst->seqNum); 324 325 load_inst->lqIdx = loadTail; 326 327 if (stores == 0) { 328 load_inst->sqIdx = -1; 329 } else { 330 load_inst->sqIdx = storeTail; 331 } 332 333 loadQueue[loadTail] = load_inst; 334 335 incrLdIdx(loadTail); 336 337 ++loads; 338} 339 340template <class Impl> 341void 342LSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 343{ 344 // Make sure it is not full before inserting an instruction. 345 assert((storeTail + 1) % SQEntries != storeHead); 346 assert(stores < SQEntries); 347 348 DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n", 349 store_inst->readPC(), storeTail, store_inst->seqNum); 350 351 store_inst->sqIdx = storeTail; 352 store_inst->lqIdx = loadTail; 353 354 storeQueue[storeTail] = SQEntry(store_inst); 355 356 incrStIdx(storeTail); 357 358 ++stores; 359} 360 361template <class Impl> 362typename Impl::DynInstPtr 363LSQUnit<Impl>::getMemDepViolator() 364{ 365 DynInstPtr temp = memDepViolator; 366 367 memDepViolator = NULL; 368 369 return temp; 370} 371 372template <class Impl> 373unsigned 374LSQUnit<Impl>::numFreeEntries() 375{ 376 unsigned free_lq_entries = LQEntries - loads; 377 unsigned free_sq_entries = SQEntries - stores; 378 379 // Both the LQ and SQ entries have an extra dummy entry to differentiate 380 // empty/full conditions. Subtract 1 from the free entries. 381 if (free_lq_entries < free_sq_entries) { 382 return free_lq_entries - 1; 383 } else { 384 return free_sq_entries - 1; 385 } 386} 387 388template <class Impl> 389int 390LSQUnit<Impl>::numLoadsReady() 391{ 392 int load_idx = loadHead; 393 int retval = 0; 394 395 while (load_idx != loadTail) { 396 assert(loadQueue[load_idx]); 397 398 if (loadQueue[load_idx]->readyToIssue()) { 399 ++retval; 400 } 401 } 402 403 return retval; 404} 405 406template <class Impl> 407Fault 408LSQUnit<Impl>::executeLoad(DynInstPtr &inst) 409{ 410 // Execute a specific load. 411 Fault load_fault = NoFault; 412 413 DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n", 414 inst->readPC(),inst->seqNum); 415 416 load_fault = inst->initiateAcc(); 417 418 // If the instruction faulted, then we need to send it along to commit 419 // without the instruction completing. 420 if (load_fault != NoFault) { 421 // Send this instruction to commit, also make sure iew stage 422 // realizes there is activity. 423 iewStage->instToCommit(inst); 424 iewStage->activityThisCycle(); 425 } 426 427 return load_fault; 428} 429 430template <class Impl> 431Fault 432LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 433{ 434 using namespace TheISA; 435 // Make sure that a store exists. 436 assert(stores != 0); 437 438 int store_idx = store_inst->sqIdx; 439 440 DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n", 441 store_inst->readPC(), store_inst->seqNum); 442 443 // Check the recently completed loads to see if any match this store's 444 // address. If so, then we have a memory ordering violation. 445 int load_idx = store_inst->lqIdx; 446 447 Fault store_fault = store_inst->initiateAcc(); 448 449 if (storeQueue[store_idx].size == 0) { 450 DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n", 451 store_inst->readPC(),store_inst->seqNum); 452 453 return store_fault; 454 } 455 456 assert(store_fault == NoFault); 457 458 if (store_inst->isStoreConditional()) { 459 // Store conditionals need to set themselves as able to 460 // writeback if we haven't had a fault by here. 461 storeQueue[store_idx].canWB = true; 462 463 ++storesToWB; 464 } 465 466 if (!memDepViolator) { 467 while (load_idx != loadTail) { 468 // Really only need to check loads that have actually executed 469 // It's safe to check all loads because effAddr is set to 470 // InvalAddr when the dyn inst is created. 471 472 // @todo: For now this is extra conservative, detecting a 473 // violation if the addresses match assuming all accesses 474 // are quad word accesses. 475 476 // @todo: Fix this, magic number being used here 477 if ((loadQueue[load_idx]->effAddr >> 8) == 478 (store_inst->effAddr >> 8)) { 479 // A load incorrectly passed this store. Squash and refetch. 480 // For now return a fault to show that it was unsuccessful. 481 memDepViolator = loadQueue[load_idx]; 482 483 return genMachineCheckFault(); 484 } 485 486 incrLdIdx(load_idx); 487 } 488 489 // If we've reached this point, there was no violation. 490 memDepViolator = NULL; 491 } 492 493 return store_fault; 494} 495 496template <class Impl> 497void 498LSQUnit<Impl>::commitLoad() 499{ 500 assert(loadQueue[loadHead]); 501 502 DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n", 503 loadQueue[loadHead]->readPC()); 504 505 loadQueue[loadHead] = NULL; 506 507 incrLdIdx(loadHead); 508 509 --loads; 510} 511 512template <class Impl> 513void 514LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 515{ 516 assert(loads == 0 || loadQueue[loadHead]); 517 518 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 519 commitLoad(); 520 } 521} 522 523template <class Impl> 524void 525LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 526{ 527 assert(stores == 0 || storeQueue[storeHead].inst); 528 529 int store_idx = storeHead; 530 531 while (store_idx != storeTail) { 532 assert(storeQueue[store_idx].inst); 533 // Mark any stores that are now committed and have not yet 534 // been marked as able to write back. 535 if (!storeQueue[store_idx].canWB) { 536 if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 537 break; 538 } 539 DPRINTF(LSQUnit, "Marking store as able to write back, PC " 540 "%#x [sn:%lli]\n", 541 storeQueue[store_idx].inst->readPC(), 542 storeQueue[store_idx].inst->seqNum); 543 544 storeQueue[store_idx].canWB = true; 545 546 ++storesToWB; 547 } 548 549 incrStIdx(store_idx); 550 } 551} 552 553template <class Impl> 554void 555LSQUnit<Impl>::writebackStores() 556{ 557 while (storesToWB > 0 && 558 storeWBIdx != storeTail && 559 storeQueue[storeWBIdx].inst && 560 storeQueue[storeWBIdx].canWB && 561 usedPorts < cachePorts) { 562 563 if (isStoreBlocked) { 564 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 565 " is blocked!\n"); 566 break; 567 } 568 569 // Store didn't write any data so no need to write it back to 570 // memory. 571 if (storeQueue[storeWBIdx].size == 0) { 572 completeStore(storeWBIdx); 573 574 incrStIdx(storeWBIdx); 575 576 continue; 577 } 578 579 ++usedPorts; 580 581 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 582 incrStIdx(storeWBIdx); 583 584 continue; 585 } 586 587 assert(storeQueue[storeWBIdx].req); 588 assert(!storeQueue[storeWBIdx].committed); 589 590 DynInstPtr inst = storeQueue[storeWBIdx].inst; 591 592 Request *req = storeQueue[storeWBIdx].req; 593 storeQueue[storeWBIdx].committed = true; 594 595 assert(!inst->memData); 596 inst->memData = new uint8_t[64]; 597 memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data, 598 req->getSize()); 599 600 PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 601 data_pkt->dataStatic(inst->memData); 602 603 LSQSenderState *state = new LSQSenderState; 604 state->isLoad = false; 605 state->idx = storeWBIdx; 606 state->inst = inst; 607 data_pkt->senderState = state; 608 609 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " 610 "to Addr:%#x, data:%#x [sn:%lli]\n", 611 storeWBIdx, storeQueue[storeWBIdx].inst->readPC(), 612 req->getPaddr(), *(inst->memData), 613 storeQueue[storeWBIdx].inst->seqNum); 614 615 if (!dcachePort->sendTiming(data_pkt)) { 616 // Need to handle becoming blocked on a store. 617 isStoreBlocked = true; 618 } else { 619 if (isStalled() && 620 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 621 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 622 "load idx:%i\n", 623 stallingStoreIsn, stallingLoadIdx); 624 stalled = false; 625 stallingStoreIsn = 0; 626 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 627 } 628 629 if (!(req->getFlags() & LOCKED)) { 630 assert(!storeQueue[storeWBIdx].inst->isStoreConditional()); 631 // Non-store conditionals do not need a writeback. 632 state->noWB = true; 633 } 634 635 if (data_pkt->result != Packet::Success) { 636 DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n", 637 storeWBIdx); 638 639 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n", 640 storeQueue[storeWBIdx].inst->seqNum); 641 642 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum); 643 644 //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size()); 645 646 // @todo: Increment stat here. 647 } else { 648 DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n", 649 storeWBIdx); 650 651 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", 652 storeQueue[storeWBIdx].inst->seqNum); 653 } 654 655 incrStIdx(storeWBIdx); 656 } 657 } 658 659 // Not sure this should set it to 0. 660 usedPorts = 0; 661 662 assert(stores >= 0 && storesToWB >= 0); 663} 664 665/*template <class Impl> 666void 667LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 668{ 669 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 670 mshrSeqNums.end(), 671 seqNum); 672 673 if (mshr_it != mshrSeqNums.end()) { 674 mshrSeqNums.erase(mshr_it); 675 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 676 } 677}*/ 678 679template <class Impl> 680void 681LSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 682{ 683 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 684 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 685 686 int load_idx = loadTail; 687 decrLdIdx(load_idx); 688 689 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 690 DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, " 691 "[sn:%lli]\n", 692 loadQueue[load_idx]->readPC(), 693 loadQueue[load_idx]->seqNum); 694 695 if (isStalled() && load_idx == stallingLoadIdx) { 696 stalled = false; 697 stallingStoreIsn = 0; 698 stallingLoadIdx = 0; 699 } 700 701 // Clear the smart pointer to make sure it is decremented. 702 loadQueue[load_idx]->squashed = true; 703 loadQueue[load_idx] = NULL; 704 --loads; 705 706 // Inefficient! 707 loadTail = load_idx; 708 709 decrLdIdx(load_idx); 710 } 711 712 if (isLoadBlocked) { 713 if (squashed_num < blockedLoadSeqNum) { 714 isLoadBlocked = false; 715 loadBlockedHandled = false; 716 blockedLoadSeqNum = 0; 717 } 718 } 719 720 int store_idx = storeTail; 721 decrStIdx(store_idx); 722 723 while (stores != 0 && 724 storeQueue[store_idx].inst->seqNum > squashed_num) { 725 // Instructions marked as can WB are already committed. 726 if (storeQueue[store_idx].canWB) { 727 break; 728 } 729 730 DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, " 731 "idx:%i [sn:%lli]\n", 732 storeQueue[store_idx].inst->readPC(), 733 store_idx, storeQueue[store_idx].inst->seqNum); 734 735 // I don't think this can happen. It should have been cleared 736 // by the stalling load. 737 if (isStalled() && 738 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 739 panic("Is stalled should have been cleared by stalling load!\n"); 740 stalled = false; 741 stallingStoreIsn = 0; 742 } 743 744 // Clear the smart pointer to make sure it is decremented. 745 storeQueue[store_idx].inst->squashed = true; 746 storeQueue[store_idx].inst = NULL; 747 storeQueue[store_idx].canWB = 0; 748 749 storeQueue[store_idx].req = NULL; 750 --stores; 751 752 // Inefficient! 753 storeTail = store_idx; 754 755 decrStIdx(store_idx); 756 } 757} 758 759template <class Impl> 760void 761LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 762{ 763 iewStage->wakeCPU(); 764 765 // Squashed instructions do not need to complete their access. 766 if (inst->isSquashed()) { 767 assert(!inst->isStore()); 768 return; 769 } 770 771 if (!inst->isExecuted()) { 772 inst->setExecuted(); 773 774 // Complete access to copy data to proper place. 775 inst->completeAcc(pkt); 776 } 777 778 // Need to insert instruction into queue to commit 779 iewStage->instToCommit(inst); 780 781 iewStage->activityThisCycle(); 782} 783 784template <class Impl> 785void 786LSQUnit<Impl>::completeStore(int store_idx) 787{ 788 assert(storeQueue[store_idx].inst); 789 storeQueue[store_idx].completed = true; 790 --storesToWB; 791 // A bit conservative because a store completion may not free up entries, 792 // but hopefully avoids two store completions in one cycle from making 793 // the CPU tick twice. 794 cpu->activityThisCycle(); 795 796 if (store_idx == storeHead) { 797 do { 798 incrStIdx(storeHead); 799 800 --stores; 801 } while (storeQueue[storeHead].completed && 802 storeHead != storeTail); 803 804 iewStage->updateLSQNextCycle = true; 805 } 806 807 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 808 "idx:%i\n", 809 storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 810 811 if (isStalled() && 812 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 813 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 814 "load idx:%i\n", 815 stallingStoreIsn, stallingLoadIdx); 816 stalled = false; 817 stallingStoreIsn = 0; 818 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 819 } 820 821 storeQueue[store_idx].inst->setCompleted(); 822 823 // Tell the checker we've completed this instruction. Some stores 824 // may get reported twice to the checker, but the checker can 825 // handle that case. 826 if (cpu->checker) { 827 cpu->checker->tick(storeQueue[store_idx].inst); 828 } 829} 830 831template <class Impl> 832inline void 833LSQUnit<Impl>::incrStIdx(int &store_idx) 834{ 835 if (++store_idx >= SQEntries) 836 store_idx = 0; 837} 838 839template <class Impl> 840inline void 841LSQUnit<Impl>::decrStIdx(int &store_idx) 842{ 843 if (--store_idx < 0) 844 store_idx += SQEntries; 845} 846 847template <class Impl> 848inline void 849LSQUnit<Impl>::incrLdIdx(int &load_idx) 850{ 851 if (++load_idx >= LQEntries) 852 load_idx = 0; 853} 854 855template <class Impl> 856inline void 857LSQUnit<Impl>::decrLdIdx(int &load_idx) 858{ 859 if (--load_idx < 0) 860 load_idx += LQEntries; 861} 862 863template <class Impl> 864void 865LSQUnit<Impl>::dumpInsts() 866{ 867 cprintf("Load store queue: Dumping instructions.\n"); 868 cprintf("Load queue size: %i\n", loads); 869 cprintf("Load queue: "); 870 871 int load_idx = loadHead; 872 873 while (load_idx != loadTail && loadQueue[load_idx]) { 874 cprintf("%#x ", loadQueue[load_idx]->readPC()); 875 876 incrLdIdx(load_idx); 877 } 878 879 cprintf("Store queue size: %i\n", stores); 880 cprintf("Store queue: "); 881 882 int store_idx = storeHead; 883 884 while (store_idx != storeTail && storeQueue[store_idx].inst) { 885 cprintf("%#x ", storeQueue[store_idx].inst->readPC()); 886 887 incrStIdx(store_idx); 888 } 889 890 cprintf("\n"); 891} 892