lsq_unit_impl.hh revision 10386:c81407818741
1 2/* 3 * Copyright (c) 2010-2014 ARM Limited 4 * Copyright (c) 2013 Advanced Micro Devices, Inc. 5 * All rights reserved 6 * 7 * The license below extends only to copyright in the software and shall 8 * not be construed as granting a license to any other intellectual 9 * property including but not limited to intellectual property relating 10 * to a hardware implementation of the functionality of the software 11 * licensed hereunder. You may use the software subject to the license 12 * terms below provided that you ensure that this notice is replicated 13 * unmodified and in its entirety in all distributions of the software, 14 * modified or unmodified, in source code or in binary form. 15 * 16 * Copyright (c) 2004-2005 The Regents of The University of Michigan 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions are 21 * met: redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer; 23 * redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution; 26 * neither the name of the copyright holders nor the names of its 27 * contributors may be used to endorse or promote products derived from 28 * this software without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Kevin Lim 43 * Korey Sewell 44 */ 45 46#ifndef __CPU_O3_LSQ_UNIT_IMPL_HH__ 47#define __CPU_O3_LSQ_UNIT_IMPL_HH__ 48 49#include "arch/generic/debugfaults.hh" 50#include "arch/locked_mem.hh" 51#include "base/str.hh" 52#include "config/the_isa.hh" 53#include "cpu/checker/cpu.hh" 54#include "cpu/o3/lsq.hh" 55#include "cpu/o3/lsq_unit.hh" 56#include "debug/Activity.hh" 57#include "debug/IEW.hh" 58#include "debug/LSQUnit.hh" 59#include "debug/O3PipeView.hh" 60#include "mem/packet.hh" 61#include "mem/request.hh" 62 63template<class Impl> 64LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 65 LSQUnit *lsq_ptr) 66 : Event(Default_Pri, AutoDelete), 67 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 68{ 69} 70 71template<class Impl> 72void 73LSQUnit<Impl>::WritebackEvent::process() 74{ 75 assert(!lsqPtr->cpu->switchedOut()); 76 77 lsqPtr->writeback(inst, pkt); 78 79 if (pkt->senderState) 80 delete pkt->senderState; 81 82 delete pkt->req; 83 delete pkt; 84} 85 86template<class Impl> 87const char * 88LSQUnit<Impl>::WritebackEvent::description() const 89{ 90 return "Store writeback"; 91} 92 93template<class Impl> 94void 95LSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 96{ 97 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 98 DynInstPtr inst = state->inst; 99 DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum); 100 DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum); 101 102 if (state->cacheBlocked) { 103 // This is the first half of a previous split load, 104 // where the 2nd half blocked, ignore this response 105 DPRINTF(IEW, "[sn:%lli]: Response from first half of earlier " 106 "blocked split load recieved. Ignoring.\n", inst->seqNum); 107 delete state; 108 delete pkt->req; 109 delete pkt; 110 return; 111 } 112 113 // If this is a split access, wait until all packets are received. 114 if (TheISA::HasUnalignedMemAcc && !state->complete()) { 115 delete pkt->req; 116 delete pkt; 117 return; 118 } 119 120 assert(!cpu->switchedOut()); 121 if (!inst->isSquashed()) { 122 if (!state->noWB) { 123 if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 124 !state->isLoad) { 125 writeback(inst, pkt); 126 } else { 127 writeback(inst, state->mainPkt); 128 } 129 } 130 131 if (inst->isStore()) { 132 completeStore(state->idx); 133 } 134 } 135 136 if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 137 delete state->mainPkt->req; 138 delete state->mainPkt; 139 } 140 141 pkt->req->setAccessLatency(); 142 cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt)); 143 144 delete state; 145 delete pkt->req; 146 delete pkt; 147} 148 149template <class Impl> 150LSQUnit<Impl>::LSQUnit() 151 : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 152 isStoreBlocked(false), storeInFlight(false), hasPendingPkt(false) 153{ 154} 155 156template<class Impl> 157void 158LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 159 LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 160 unsigned id) 161{ 162 cpu = cpu_ptr; 163 iewStage = iew_ptr; 164 165 lsq = lsq_ptr; 166 167 lsqID = id; 168 169 DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 170 171 // Add 1 for the sentinel entry (they are circular queues). 172 LQEntries = maxLQEntries + 1; 173 SQEntries = maxSQEntries + 1; 174 175 //Due to uint8_t index in LSQSenderState 176 assert(LQEntries <= 256); 177 assert(SQEntries <= 256); 178 179 loadQueue.resize(LQEntries); 180 storeQueue.resize(SQEntries); 181 182 depCheckShift = params->LSQDepCheckShift; 183 checkLoads = params->LSQCheckLoads; 184 cachePorts = params->cachePorts; 185 needsTSO = params->needsTSO; 186 187 resetState(); 188} 189 190 191template<class Impl> 192void 193LSQUnit<Impl>::resetState() 194{ 195 loads = stores = storesToWB = 0; 196 197 loadHead = loadTail = 0; 198 199 storeHead = storeWBIdx = storeTail = 0; 200 201 usedPorts = 0; 202 203 retryPkt = NULL; 204 memDepViolator = NULL; 205 206 stalled = false; 207 208 cacheBlockMask = ~(cpu->cacheLineSize() - 1); 209} 210 211template<class Impl> 212std::string 213LSQUnit<Impl>::name() const 214{ 215 if (Impl::MaxThreads == 1) { 216 return iewStage->name() + ".lsq"; 217 } else { 218 return iewStage->name() + ".lsq.thread" + std::to_string(lsqID); 219 } 220} 221 222template<class Impl> 223void 224LSQUnit<Impl>::regStats() 225{ 226 lsqForwLoads 227 .name(name() + ".forwLoads") 228 .desc("Number of loads that had data forwarded from stores"); 229 230 invAddrLoads 231 .name(name() + ".invAddrLoads") 232 .desc("Number of loads ignored due to an invalid address"); 233 234 lsqSquashedLoads 235 .name(name() + ".squashedLoads") 236 .desc("Number of loads squashed"); 237 238 lsqIgnoredResponses 239 .name(name() + ".ignoredResponses") 240 .desc("Number of memory responses ignored because the instruction is squashed"); 241 242 lsqMemOrderViolation 243 .name(name() + ".memOrderViolation") 244 .desc("Number of memory ordering violations"); 245 246 lsqSquashedStores 247 .name(name() + ".squashedStores") 248 .desc("Number of stores squashed"); 249 250 invAddrSwpfs 251 .name(name() + ".invAddrSwpfs") 252 .desc("Number of software prefetches ignored due to an invalid address"); 253 254 lsqBlockedLoads 255 .name(name() + ".blockedLoads") 256 .desc("Number of blocked loads due to partial load-store forwarding"); 257 258 lsqRescheduledLoads 259 .name(name() + ".rescheduledLoads") 260 .desc("Number of loads that were rescheduled"); 261 262 lsqCacheBlocked 263 .name(name() + ".cacheBlocked") 264 .desc("Number of times an access to memory failed due to the cache being blocked"); 265} 266 267template<class Impl> 268void 269LSQUnit<Impl>::setDcachePort(MasterPort *dcache_port) 270{ 271 dcachePort = dcache_port; 272} 273 274template<class Impl> 275void 276LSQUnit<Impl>::clearLQ() 277{ 278 loadQueue.clear(); 279} 280 281template<class Impl> 282void 283LSQUnit<Impl>::clearSQ() 284{ 285 storeQueue.clear(); 286} 287 288template<class Impl> 289void 290LSQUnit<Impl>::drainSanityCheck() const 291{ 292 for (int i = 0; i < loadQueue.size(); ++i) 293 assert(!loadQueue[i]); 294 295 assert(storesToWB == 0); 296 assert(!retryPkt); 297} 298 299template<class Impl> 300void 301LSQUnit<Impl>::takeOverFrom() 302{ 303 resetState(); 304} 305 306template<class Impl> 307void 308LSQUnit<Impl>::resizeLQ(unsigned size) 309{ 310 unsigned size_plus_sentinel = size + 1; 311 assert(size_plus_sentinel >= LQEntries); 312 313 if (size_plus_sentinel > LQEntries) { 314 while (size_plus_sentinel > loadQueue.size()) { 315 DynInstPtr dummy; 316 loadQueue.push_back(dummy); 317 LQEntries++; 318 } 319 } else { 320 LQEntries = size_plus_sentinel; 321 } 322 323 assert(LQEntries <= 256); 324} 325 326template<class Impl> 327void 328LSQUnit<Impl>::resizeSQ(unsigned size) 329{ 330 unsigned size_plus_sentinel = size + 1; 331 if (size_plus_sentinel > SQEntries) { 332 while (size_plus_sentinel > storeQueue.size()) { 333 SQEntry dummy; 334 storeQueue.push_back(dummy); 335 SQEntries++; 336 } 337 } else { 338 SQEntries = size_plus_sentinel; 339 } 340 341 assert(SQEntries <= 256); 342} 343 344template <class Impl> 345void 346LSQUnit<Impl>::insert(DynInstPtr &inst) 347{ 348 assert(inst->isMemRef()); 349 350 assert(inst->isLoad() || inst->isStore()); 351 352 if (inst->isLoad()) { 353 insertLoad(inst); 354 } else { 355 insertStore(inst); 356 } 357 358 inst->setInLSQ(); 359} 360 361template <class Impl> 362void 363LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 364{ 365 assert((loadTail + 1) % LQEntries != loadHead); 366 assert(loads < LQEntries); 367 368 DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 369 load_inst->pcState(), loadTail, load_inst->seqNum); 370 371 load_inst->lqIdx = loadTail; 372 373 if (stores == 0) { 374 load_inst->sqIdx = -1; 375 } else { 376 load_inst->sqIdx = storeTail; 377 } 378 379 loadQueue[loadTail] = load_inst; 380 381 incrLdIdx(loadTail); 382 383 ++loads; 384} 385 386template <class Impl> 387void 388LSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 389{ 390 // Make sure it is not full before inserting an instruction. 391 assert((storeTail + 1) % SQEntries != storeHead); 392 assert(stores < SQEntries); 393 394 DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 395 store_inst->pcState(), storeTail, store_inst->seqNum); 396 397 store_inst->sqIdx = storeTail; 398 store_inst->lqIdx = loadTail; 399 400 storeQueue[storeTail] = SQEntry(store_inst); 401 402 incrStIdx(storeTail); 403 404 ++stores; 405} 406 407template <class Impl> 408typename Impl::DynInstPtr 409LSQUnit<Impl>::getMemDepViolator() 410{ 411 DynInstPtr temp = memDepViolator; 412 413 memDepViolator = NULL; 414 415 return temp; 416} 417 418template <class Impl> 419unsigned 420LSQUnit<Impl>::numFreeLoadEntries() 421{ 422 //LQ has an extra dummy entry to differentiate 423 //empty/full conditions. Subtract 1 from the free entries. 424 DPRINTF(LSQUnit, "LQ size: %d, #loads occupied: %d\n", LQEntries, loads); 425 return LQEntries - loads - 1; 426} 427 428template <class Impl> 429unsigned 430LSQUnit<Impl>::numFreeStoreEntries() 431{ 432 //SQ has an extra dummy entry to differentiate 433 //empty/full conditions. Subtract 1 from the free entries. 434 DPRINTF(LSQUnit, "SQ size: %d, #stores occupied: %d\n", SQEntries, stores); 435 return SQEntries - stores - 1; 436 437 } 438 439template <class Impl> 440void 441LSQUnit<Impl>::checkSnoop(PacketPtr pkt) 442{ 443 int load_idx = loadHead; 444 DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr()); 445 446 // Unlock the cpu-local monitor when the CPU sees a snoop to a locked 447 // address. The CPU can speculatively execute a LL operation after a pending 448 // SC operation in the pipeline and that can make the cache monitor the CPU 449 // is connected to valid while it really shouldn't be. 450 for (int x = 0; x < cpu->numContexts(); x++) { 451 ThreadContext *tc = cpu->getContext(x); 452 bool no_squash = cpu->thread[x]->noSquashFromTC; 453 cpu->thread[x]->noSquashFromTC = true; 454 TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask); 455 cpu->thread[x]->noSquashFromTC = no_squash; 456 } 457 458 Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 459 460 DynInstPtr ld_inst = loadQueue[load_idx]; 461 if (ld_inst) { 462 Addr load_addr = ld_inst->physEffAddr & cacheBlockMask; 463 // Check that this snoop didn't just invalidate our lock flag 464 if (ld_inst->effAddrValid() && load_addr == invalidate_addr && 465 ld_inst->memReqFlags & Request::LLSC) 466 TheISA::handleLockedSnoopHit(ld_inst.get()); 467 } 468 469 // If this is the only load in the LSQ we don't care 470 if (load_idx == loadTail) 471 return; 472 473 incrLdIdx(load_idx); 474 475 bool force_squash = false; 476 477 while (load_idx != loadTail) { 478 DynInstPtr ld_inst = loadQueue[load_idx]; 479 480 if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) { 481 incrLdIdx(load_idx); 482 continue; 483 } 484 485 Addr load_addr = ld_inst->physEffAddr & cacheBlockMask; 486 DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n", 487 ld_inst->seqNum, load_addr, invalidate_addr); 488 489 if (load_addr == invalidate_addr || force_squash) { 490 if (needsTSO) { 491 // If we have a TSO system, as all loads must be ordered with 492 // all other loads, this load as well as *all* subsequent loads 493 // need to be squashed to prevent possible load reordering. 494 force_squash = true; 495 } 496 if (ld_inst->possibleLoadViolation() || force_squash) { 497 DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n", 498 pkt->getAddr(), ld_inst->seqNum); 499 500 // Mark the load for re-execution 501 ld_inst->fault = new ReExec; 502 } else { 503 DPRINTF(LSQUnit, "HitExternal Snoop for addr %#x [sn:%lli]\n", 504 pkt->getAddr(), ld_inst->seqNum); 505 506 // Make sure that we don't lose a snoop hitting a LOCKED 507 // address since the LOCK* flags don't get updated until 508 // commit. 509 if (ld_inst->memReqFlags & Request::LLSC) 510 TheISA::handleLockedSnoopHit(ld_inst.get()); 511 512 // If a older load checks this and it's true 513 // then we might have missed the snoop 514 // in which case we need to invalidate to be sure 515 ld_inst->hitExternalSnoop(true); 516 } 517 } 518 incrLdIdx(load_idx); 519 } 520 return; 521} 522 523template <class Impl> 524Fault 525LSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) 526{ 527 Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 528 Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 529 530 /** @todo in theory you only need to check an instruction that has executed 531 * however, there isn't a good way in the pipeline at the moment to check 532 * all instructions that will execute before the store writes back. Thus, 533 * like the implementation that came before it, we're overly conservative. 534 */ 535 while (load_idx != loadTail) { 536 DynInstPtr ld_inst = loadQueue[load_idx]; 537 if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) { 538 incrLdIdx(load_idx); 539 continue; 540 } 541 542 Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 543 Addr ld_eff_addr2 = 544 (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 545 546 if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 547 if (inst->isLoad()) { 548 // If this load is to the same block as an external snoop 549 // invalidate that we've observed then the load needs to be 550 // squashed as it could have newer data 551 if (ld_inst->hitExternalSnoop()) { 552 if (!memDepViolator || 553 ld_inst->seqNum < memDepViolator->seqNum) { 554 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] " 555 "and [sn:%lli] at address %#x\n", 556 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 557 memDepViolator = ld_inst; 558 559 ++lsqMemOrderViolation; 560 561 return new GenericISA::M5PanicFault( 562 "Detected fault with inst [sn:%lli] and " 563 "[sn:%lli] at address %#x\n", 564 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 565 } 566 } 567 568 // Otherwise, mark the load has a possible load violation 569 // and if we see a snoop before it's commited, we need to squash 570 ld_inst->possibleLoadViolation(true); 571 DPRINTF(LSQUnit, "Found possible load violaiton at addr: %#x" 572 " between instructions [sn:%lli] and [sn:%lli]\n", 573 inst_eff_addr1, inst->seqNum, ld_inst->seqNum); 574 } else { 575 // A load/store incorrectly passed this store. 576 // Check if we already have a violator, or if it's newer 577 // squash and refetch. 578 if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 579 break; 580 581 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and " 582 "[sn:%lli] at address %#x\n", 583 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 584 memDepViolator = ld_inst; 585 586 ++lsqMemOrderViolation; 587 588 return new GenericISA::M5PanicFault("Detected fault with " 589 "inst [sn:%lli] and [sn:%lli] at address %#x\n", 590 inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 591 } 592 } 593 594 incrLdIdx(load_idx); 595 } 596 return NoFault; 597} 598 599 600 601 602template <class Impl> 603Fault 604LSQUnit<Impl>::executeLoad(DynInstPtr &inst) 605{ 606 using namespace TheISA; 607 // Execute a specific load. 608 Fault load_fault = NoFault; 609 610 DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 611 inst->pcState(), inst->seqNum); 612 613 assert(!inst->isSquashed()); 614 615 load_fault = inst->initiateAcc(); 616 617 if (inst->isTranslationDelayed() && 618 load_fault == NoFault) 619 return load_fault; 620 621 // If the instruction faulted or predicated false, then we need to send it 622 // along to commit without the instruction completing. 623 if (load_fault != NoFault || !inst->readPredicate()) { 624 // Send this instruction to commit, also make sure iew stage 625 // realizes there is activity. 626 // Mark it as executed unless it is an uncached load that 627 // needs to hit the head of commit. 628 if (!inst->readPredicate()) 629 inst->forwardOldRegs(); 630 DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 631 inst->seqNum, 632 (load_fault != NoFault ? "fault" : "predication")); 633 if (!(inst->hasRequest() && inst->uncacheable()) || 634 inst->isAtCommit()) { 635 inst->setExecuted(); 636 } 637 iewStage->instToCommit(inst); 638 iewStage->activityThisCycle(); 639 } else { 640 assert(inst->effAddrValid()); 641 int load_idx = inst->lqIdx; 642 incrLdIdx(load_idx); 643 644 if (checkLoads) 645 return checkViolations(load_idx, inst); 646 } 647 648 return load_fault; 649} 650 651template <class Impl> 652Fault 653LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 654{ 655 using namespace TheISA; 656 // Make sure that a store exists. 657 assert(stores != 0); 658 659 int store_idx = store_inst->sqIdx; 660 661 DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 662 store_inst->pcState(), store_inst->seqNum); 663 664 assert(!store_inst->isSquashed()); 665 666 // Check the recently completed loads to see if any match this store's 667 // address. If so, then we have a memory ordering violation. 668 int load_idx = store_inst->lqIdx; 669 670 Fault store_fault = store_inst->initiateAcc(); 671 672 if (store_inst->isTranslationDelayed() && 673 store_fault == NoFault) 674 return store_fault; 675 676 if (!store_inst->readPredicate()) 677 store_inst->forwardOldRegs(); 678 679 if (storeQueue[store_idx].size == 0) { 680 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 681 store_inst->pcState(), store_inst->seqNum); 682 683 return store_fault; 684 } else if (!store_inst->readPredicate()) { 685 DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 686 store_inst->seqNum); 687 return store_fault; 688 } 689 690 assert(store_fault == NoFault); 691 692 if (store_inst->isStoreConditional()) { 693 // Store conditionals need to set themselves as able to 694 // writeback if we haven't had a fault by here. 695 storeQueue[store_idx].canWB = true; 696 697 ++storesToWB; 698 } 699 700 return checkViolations(load_idx, store_inst); 701 702} 703 704template <class Impl> 705void 706LSQUnit<Impl>::commitLoad() 707{ 708 assert(loadQueue[loadHead]); 709 710 DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 711 loadQueue[loadHead]->pcState()); 712 713 loadQueue[loadHead] = NULL; 714 715 incrLdIdx(loadHead); 716 717 --loads; 718} 719 720template <class Impl> 721void 722LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 723{ 724 assert(loads == 0 || loadQueue[loadHead]); 725 726 while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 727 commitLoad(); 728 } 729} 730 731template <class Impl> 732void 733LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 734{ 735 assert(stores == 0 || storeQueue[storeHead].inst); 736 737 int store_idx = storeHead; 738 739 while (store_idx != storeTail) { 740 assert(storeQueue[store_idx].inst); 741 // Mark any stores that are now committed and have not yet 742 // been marked as able to write back. 743 if (!storeQueue[store_idx].canWB) { 744 if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 745 break; 746 } 747 DPRINTF(LSQUnit, "Marking store as able to write back, PC " 748 "%s [sn:%lli]\n", 749 storeQueue[store_idx].inst->pcState(), 750 storeQueue[store_idx].inst->seqNum); 751 752 storeQueue[store_idx].canWB = true; 753 754 ++storesToWB; 755 } 756 757 incrStIdx(store_idx); 758 } 759} 760 761template <class Impl> 762void 763LSQUnit<Impl>::writebackPendingStore() 764{ 765 if (hasPendingPkt) { 766 assert(pendingPkt != NULL); 767 768 // If the cache is blocked, this will store the packet for retry. 769 if (sendStore(pendingPkt)) { 770 storePostSend(pendingPkt); 771 } 772 pendingPkt = NULL; 773 hasPendingPkt = false; 774 } 775} 776 777template <class Impl> 778void 779LSQUnit<Impl>::writebackStores() 780{ 781 // First writeback the second packet from any split store that didn't 782 // complete last cycle because there weren't enough cache ports available. 783 if (TheISA::HasUnalignedMemAcc) { 784 writebackPendingStore(); 785 } 786 787 while (storesToWB > 0 && 788 storeWBIdx != storeTail && 789 storeQueue[storeWBIdx].inst && 790 storeQueue[storeWBIdx].canWB && 791 ((!needsTSO) || (!storeInFlight)) && 792 usedPorts < cachePorts) { 793 794 if (isStoreBlocked) { 795 DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 796 " is blocked!\n"); 797 break; 798 } 799 800 // Store didn't write any data so no need to write it back to 801 // memory. 802 if (storeQueue[storeWBIdx].size == 0) { 803 completeStore(storeWBIdx); 804 805 incrStIdx(storeWBIdx); 806 807 continue; 808 } 809 810 ++usedPorts; 811 812 if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 813 incrStIdx(storeWBIdx); 814 815 continue; 816 } 817 818 assert(storeQueue[storeWBIdx].req); 819 assert(!storeQueue[storeWBIdx].committed); 820 821 if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 822 assert(storeQueue[storeWBIdx].sreqLow); 823 assert(storeQueue[storeWBIdx].sreqHigh); 824 } 825 826 DynInstPtr inst = storeQueue[storeWBIdx].inst; 827 828 Request *req = storeQueue[storeWBIdx].req; 829 RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 830 RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 831 832 storeQueue[storeWBIdx].committed = true; 833 834 assert(!inst->memData); 835 inst->memData = new uint8_t[req->getSize()]; 836 837 if (storeQueue[storeWBIdx].isAllZeros) 838 memset(inst->memData, 0, req->getSize()); 839 else 840 memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 841 842 PacketPtr data_pkt; 843 PacketPtr snd_data_pkt = NULL; 844 845 LSQSenderState *state = new LSQSenderState; 846 state->isLoad = false; 847 state->idx = storeWBIdx; 848 state->inst = inst; 849 850 if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 851 852 // Build a single data packet if the store isn't split. 853 data_pkt = Packet::createWrite(req); 854 data_pkt->dataStatic(inst->memData); 855 data_pkt->senderState = state; 856 } else { 857 // Create two packets if the store is split in two. 858 data_pkt = Packet::createWrite(sreqLow); 859 snd_data_pkt = Packet::createWrite(sreqHigh); 860 861 data_pkt->dataStatic(inst->memData); 862 snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 863 864 data_pkt->senderState = state; 865 snd_data_pkt->senderState = state; 866 867 state->isSplit = true; 868 state->outstanding = 2; 869 870 // Can delete the main request now. 871 delete req; 872 req = sreqLow; 873 } 874 875 DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 876 "to Addr:%#x, data:%#x [sn:%lli]\n", 877 storeWBIdx, inst->pcState(), 878 req->getPaddr(), (int)*(inst->memData), 879 inst->seqNum); 880 881 // @todo: Remove this SC hack once the memory system handles it. 882 if (inst->isStoreConditional()) { 883 assert(!storeQueue[storeWBIdx].isSplit); 884 // Disable recording the result temporarily. Writing to 885 // misc regs normally updates the result, but this is not 886 // the desired behavior when handling store conditionals. 887 inst->recordResult(false); 888 bool success = TheISA::handleLockedWrite(inst.get(), req, cacheBlockMask); 889 inst->recordResult(true); 890 891 if (!success) { 892 // Instantly complete this store. 893 DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 894 "Instantly completing it.\n", 895 inst->seqNum); 896 WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 897 cpu->schedule(wb, curTick() + 1); 898 if (cpu->checker) { 899 // Make sure to set the LLSC data for verification 900 // if checker is loaded 901 inst->reqToVerify->setExtraData(0); 902 inst->completeAcc(data_pkt); 903 } 904 completeStore(storeWBIdx); 905 incrStIdx(storeWBIdx); 906 continue; 907 } 908 } else { 909 // Non-store conditionals do not need a writeback. 910 state->noWB = true; 911 } 912 913 bool split = 914 TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit; 915 916 ThreadContext *thread = cpu->tcBase(lsqID); 917 918 if (req->isMmappedIpr()) { 919 assert(!inst->isStoreConditional()); 920 TheISA::handleIprWrite(thread, data_pkt); 921 delete data_pkt; 922 if (split) { 923 assert(snd_data_pkt->req->isMmappedIpr()); 924 TheISA::handleIprWrite(thread, snd_data_pkt); 925 delete snd_data_pkt; 926 delete sreqLow; 927 delete sreqHigh; 928 } 929 delete state; 930 delete req; 931 completeStore(storeWBIdx); 932 incrStIdx(storeWBIdx); 933 } else if (!sendStore(data_pkt)) { 934 DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 935 "retry later\n", 936 inst->seqNum); 937 938 // Need to store the second packet, if split. 939 if (split) { 940 state->pktToSend = true; 941 state->pendingPacket = snd_data_pkt; 942 } 943 } else { 944 945 // If split, try to send the second packet too 946 if (split) { 947 assert(snd_data_pkt); 948 949 // Ensure there are enough ports to use. 950 if (usedPorts < cachePorts) { 951 ++usedPorts; 952 if (sendStore(snd_data_pkt)) { 953 storePostSend(snd_data_pkt); 954 } else { 955 DPRINTF(IEW, "D-Cache became blocked when writing" 956 " [sn:%lli] second packet, will retry later\n", 957 inst->seqNum); 958 } 959 } else { 960 961 // Store the packet for when there's free ports. 962 assert(pendingPkt == NULL); 963 pendingPkt = snd_data_pkt; 964 hasPendingPkt = true; 965 } 966 } else { 967 968 // Not a split store. 969 storePostSend(data_pkt); 970 } 971 } 972 } 973 974 // Not sure this should set it to 0. 975 usedPorts = 0; 976 977 assert(stores >= 0 && storesToWB >= 0); 978} 979 980/*template <class Impl> 981void 982LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 983{ 984 list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 985 mshrSeqNums.end(), 986 seqNum); 987 988 if (mshr_it != mshrSeqNums.end()) { 989 mshrSeqNums.erase(mshr_it); 990 DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 991 } 992}*/ 993 994template <class Impl> 995void 996LSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 997{ 998 DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 999 "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 1000 1001 int load_idx = loadTail; 1002 decrLdIdx(load_idx); 1003 1004 while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 1005 DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 1006 "[sn:%lli]\n", 1007 loadQueue[load_idx]->pcState(), 1008 loadQueue[load_idx]->seqNum); 1009 1010 if (isStalled() && load_idx == stallingLoadIdx) { 1011 stalled = false; 1012 stallingStoreIsn = 0; 1013 stallingLoadIdx = 0; 1014 } 1015 1016 // Clear the smart pointer to make sure it is decremented. 1017 loadQueue[load_idx]->setSquashed(); 1018 loadQueue[load_idx] = NULL; 1019 --loads; 1020 1021 // Inefficient! 1022 loadTail = load_idx; 1023 1024 decrLdIdx(load_idx); 1025 ++lsqSquashedLoads; 1026 } 1027 1028 if (memDepViolator && squashed_num < memDepViolator->seqNum) { 1029 memDepViolator = NULL; 1030 } 1031 1032 int store_idx = storeTail; 1033 decrStIdx(store_idx); 1034 1035 while (stores != 0 && 1036 storeQueue[store_idx].inst->seqNum > squashed_num) { 1037 // Instructions marked as can WB are already committed. 1038 if (storeQueue[store_idx].canWB) { 1039 break; 1040 } 1041 1042 DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 1043 "idx:%i [sn:%lli]\n", 1044 storeQueue[store_idx].inst->pcState(), 1045 store_idx, storeQueue[store_idx].inst->seqNum); 1046 1047 // I don't think this can happen. It should have been cleared 1048 // by the stalling load. 1049 if (isStalled() && 1050 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 1051 panic("Is stalled should have been cleared by stalling load!\n"); 1052 stalled = false; 1053 stallingStoreIsn = 0; 1054 } 1055 1056 // Clear the smart pointer to make sure it is decremented. 1057 storeQueue[store_idx].inst->setSquashed(); 1058 storeQueue[store_idx].inst = NULL; 1059 storeQueue[store_idx].canWB = 0; 1060 1061 // Must delete request now that it wasn't handed off to 1062 // memory. This is quite ugly. @todo: Figure out the proper 1063 // place to really handle request deletes. 1064 delete storeQueue[store_idx].req; 1065 if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 1066 delete storeQueue[store_idx].sreqLow; 1067 delete storeQueue[store_idx].sreqHigh; 1068 1069 storeQueue[store_idx].sreqLow = NULL; 1070 storeQueue[store_idx].sreqHigh = NULL; 1071 } 1072 1073 storeQueue[store_idx].req = NULL; 1074 --stores; 1075 1076 // Inefficient! 1077 storeTail = store_idx; 1078 1079 decrStIdx(store_idx); 1080 ++lsqSquashedStores; 1081 } 1082} 1083 1084template <class Impl> 1085void 1086LSQUnit<Impl>::storePostSend(PacketPtr pkt) 1087{ 1088 if (isStalled() && 1089 storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 1090 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 1091 "load idx:%i\n", 1092 stallingStoreIsn, stallingLoadIdx); 1093 stalled = false; 1094 stallingStoreIsn = 0; 1095 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 1096 } 1097 1098 if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 1099 // The store is basically completed at this time. This 1100 // only works so long as the checker doesn't try to 1101 // verify the value in memory for stores. 1102 storeQueue[storeWBIdx].inst->setCompleted(); 1103 1104 if (cpu->checker) { 1105 cpu->checker->verify(storeQueue[storeWBIdx].inst); 1106 } 1107 } 1108 1109 if (needsTSO) { 1110 storeInFlight = true; 1111 } 1112 1113 incrStIdx(storeWBIdx); 1114} 1115 1116template <class Impl> 1117void 1118LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 1119{ 1120 iewStage->wakeCPU(); 1121 1122 // Squashed instructions do not need to complete their access. 1123 if (inst->isSquashed()) { 1124 assert(!inst->isStore()); 1125 ++lsqIgnoredResponses; 1126 return; 1127 } 1128 1129 if (!inst->isExecuted()) { 1130 inst->setExecuted(); 1131 1132 // Complete access to copy data to proper place. 1133 inst->completeAcc(pkt); 1134 } 1135 1136 // Need to insert instruction into queue to commit 1137 iewStage->instToCommit(inst); 1138 1139 iewStage->activityThisCycle(); 1140 1141 // see if this load changed the PC 1142 iewStage->checkMisprediction(inst); 1143} 1144 1145template <class Impl> 1146void 1147LSQUnit<Impl>::completeStore(int store_idx) 1148{ 1149 assert(storeQueue[store_idx].inst); 1150 storeQueue[store_idx].completed = true; 1151 --storesToWB; 1152 // A bit conservative because a store completion may not free up entries, 1153 // but hopefully avoids two store completions in one cycle from making 1154 // the CPU tick twice. 1155 cpu->wakeCPU(); 1156 cpu->activityThisCycle(); 1157 1158 if (store_idx == storeHead) { 1159 do { 1160 incrStIdx(storeHead); 1161 1162 --stores; 1163 } while (storeQueue[storeHead].completed && 1164 storeHead != storeTail); 1165 1166 iewStage->updateLSQNextCycle = true; 1167 } 1168 1169 DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 1170 "idx:%i\n", 1171 storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 1172 1173#if TRACING_ON 1174 if (DTRACE(O3PipeView)) { 1175 storeQueue[store_idx].inst->storeTick = 1176 curTick() - storeQueue[store_idx].inst->fetchTick; 1177 } 1178#endif 1179 1180 if (isStalled() && 1181 storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 1182 DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 1183 "load idx:%i\n", 1184 stallingStoreIsn, stallingLoadIdx); 1185 stalled = false; 1186 stallingStoreIsn = 0; 1187 iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 1188 } 1189 1190 storeQueue[store_idx].inst->setCompleted(); 1191 1192 if (needsTSO) { 1193 storeInFlight = false; 1194 } 1195 1196 // Tell the checker we've completed this instruction. Some stores 1197 // may get reported twice to the checker, but the checker can 1198 // handle that case. 1199 if (cpu->checker) { 1200 cpu->checker->verify(storeQueue[store_idx].inst); 1201 } 1202} 1203 1204template <class Impl> 1205bool 1206LSQUnit<Impl>::sendStore(PacketPtr data_pkt) 1207{ 1208 if (!dcachePort->sendTimingReq(data_pkt)) { 1209 // Need to handle becoming blocked on a store. 1210 isStoreBlocked = true; 1211 ++lsqCacheBlocked; 1212 assert(retryPkt == NULL); 1213 retryPkt = data_pkt; 1214 return false; 1215 } 1216 return true; 1217} 1218 1219template <class Impl> 1220void 1221LSQUnit<Impl>::recvRetry() 1222{ 1223 if (isStoreBlocked) { 1224 DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 1225 assert(retryPkt != NULL); 1226 1227 LSQSenderState *state = 1228 dynamic_cast<LSQSenderState *>(retryPkt->senderState); 1229 1230 if (dcachePort->sendTimingReq(retryPkt)) { 1231 // Don't finish the store unless this is the last packet. 1232 if (!TheISA::HasUnalignedMemAcc || !state->pktToSend || 1233 state->pendingPacket == retryPkt) { 1234 state->pktToSend = false; 1235 storePostSend(retryPkt); 1236 } 1237 retryPkt = NULL; 1238 isStoreBlocked = false; 1239 1240 // Send any outstanding packet. 1241 if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 1242 assert(state->pendingPacket); 1243 if (sendStore(state->pendingPacket)) { 1244 storePostSend(state->pendingPacket); 1245 } 1246 } 1247 } else { 1248 // Still blocked! 1249 ++lsqCacheBlocked; 1250 } 1251 } 1252} 1253 1254template <class Impl> 1255inline void 1256LSQUnit<Impl>::incrStIdx(int &store_idx) const 1257{ 1258 if (++store_idx >= SQEntries) 1259 store_idx = 0; 1260} 1261 1262template <class Impl> 1263inline void 1264LSQUnit<Impl>::decrStIdx(int &store_idx) const 1265{ 1266 if (--store_idx < 0) 1267 store_idx += SQEntries; 1268} 1269 1270template <class Impl> 1271inline void 1272LSQUnit<Impl>::incrLdIdx(int &load_idx) const 1273{ 1274 if (++load_idx >= LQEntries) 1275 load_idx = 0; 1276} 1277 1278template <class Impl> 1279inline void 1280LSQUnit<Impl>::decrLdIdx(int &load_idx) const 1281{ 1282 if (--load_idx < 0) 1283 load_idx += LQEntries; 1284} 1285 1286template <class Impl> 1287void 1288LSQUnit<Impl>::dumpInsts() const 1289{ 1290 cprintf("Load store queue: Dumping instructions.\n"); 1291 cprintf("Load queue size: %i\n", loads); 1292 cprintf("Load queue: "); 1293 1294 int load_idx = loadHead; 1295 1296 while (load_idx != loadTail && loadQueue[load_idx]) { 1297 const DynInstPtr &inst(loadQueue[load_idx]); 1298 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 1299 1300 incrLdIdx(load_idx); 1301 } 1302 cprintf("\n"); 1303 1304 cprintf("Store queue size: %i\n", stores); 1305 cprintf("Store queue: "); 1306 1307 int store_idx = storeHead; 1308 1309 while (store_idx != storeTail && storeQueue[store_idx].inst) { 1310 const DynInstPtr &inst(storeQueue[store_idx].inst); 1311 cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 1312 1313 incrStIdx(store_idx); 1314 } 1315 1316 cprintf("\n"); 1317} 1318 1319#endif//__CPU_O3_LSQ_UNIT_IMPL_HH__ 1320