lsq_unit_impl.hh revision 9936
19814Sandreas.hansson@arm.com 22292SN/A/* 39383SAli.Saidi@ARM.com * Copyright (c) 2010-2012 ARM Limited 47597Sminkyu.jeong@arm.com * All rights reserved 57597Sminkyu.jeong@arm.com * 67597Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 77597Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 87597Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 97597Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 107597Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 117597Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 127597Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 137597Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 147597Sminkyu.jeong@arm.com * 152292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 162292SN/A * All rights reserved. 172292SN/A * 182292SN/A * Redistribution and use in source and binary forms, with or without 192292SN/A * modification, are permitted provided that the following conditions are 202292SN/A * met: redistributions of source code must retain the above copyright 212292SN/A * notice, this list of conditions and the following disclaimer; 222292SN/A * redistributions in binary form must reproduce the above copyright 232292SN/A * notice, this list of conditions and the following disclaimer in the 242292SN/A * documentation and/or other materials provided with the distribution; 252292SN/A * neither the name of the copyright holders nor the names of its 262292SN/A * contributors may be used to endorse or promote products derived from 272292SN/A * this software without specific prior written permission. 282292SN/A * 292292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Kevin Lim 422689Sktlim@umich.edu * Korey Sewell 432292SN/A */ 442292SN/A 458591Sgblack@eecs.umich.edu#include "arch/generic/debugfaults.hh" 463326Sktlim@umich.edu#include "arch/locked_mem.hh" 478229Snate@binkert.org#include "base/str.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 498887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 502907Sktlim@umich.edu#include "cpu/o3/lsq.hh" 512292SN/A#include "cpu/o3/lsq_unit.hh" 528232Snate@binkert.org#include "debug/Activity.hh" 538232Snate@binkert.org#include "debug/IEW.hh" 548232Snate@binkert.org#include "debug/LSQUnit.hh" 559527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 562722Sktlim@umich.edu#include "mem/packet.hh" 572669Sktlim@umich.edu#include "mem/request.hh" 582292SN/A 592669Sktlim@umich.edutemplate<class Impl> 602678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 612678Sktlim@umich.edu LSQUnit *lsq_ptr) 628581Ssteve.reinhardt@amd.com : Event(Default_Pri, AutoDelete), 638581Ssteve.reinhardt@amd.com inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 642292SN/A{ 652292SN/A} 662292SN/A 672669Sktlim@umich.edutemplate<class Impl> 682292SN/Avoid 692678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 702292SN/A{ 719444SAndreas.Sandberg@ARM.com assert(!lsqPtr->cpu->switchedOut()); 729444SAndreas.Sandberg@ARM.com 739444SAndreas.Sandberg@ARM.com lsqPtr->writeback(inst, pkt); 744319Sktlim@umich.edu 754319Sktlim@umich.edu if (pkt->senderState) 764319Sktlim@umich.edu delete pkt->senderState; 774319Sktlim@umich.edu 784319Sktlim@umich.edu delete pkt->req; 792678Sktlim@umich.edu delete pkt; 802678Sktlim@umich.edu} 812292SN/A 822678Sktlim@umich.edutemplate<class Impl> 832678Sktlim@umich.educonst char * 845336Shines@cs.fsu.eduLSQUnit<Impl>::WritebackEvent::description() const 852678Sktlim@umich.edu{ 864873Sstever@eecs.umich.edu return "Store writeback"; 872678Sktlim@umich.edu} 882292SN/A 892678Sktlim@umich.edutemplate<class Impl> 902678Sktlim@umich.eduvoid 912678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 922678Sktlim@umich.edu{ 932678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 942678Sktlim@umich.edu DynInstPtr inst = state->inst; 957852SMatt.Horsnell@arm.com DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum); 967852SMatt.Horsnell@arm.com DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum); 972344SN/A 982678Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 992678Sktlim@umich.edu 1006974Stjones1@inf.ed.ac.uk // If this is a split access, wait until all packets are received. 1016974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && !state->complete()) { 1026974Stjones1@inf.ed.ac.uk delete pkt->req; 1036974Stjones1@inf.ed.ac.uk delete pkt; 1046974Stjones1@inf.ed.ac.uk return; 1056974Stjones1@inf.ed.ac.uk } 1066974Stjones1@inf.ed.ac.uk 1079444SAndreas.Sandberg@ARM.com assert(!cpu->switchedOut()); 1089444SAndreas.Sandberg@ARM.com if (inst->isSquashed()) { 1092820Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 1102678Sktlim@umich.edu } else { 1112678Sktlim@umich.edu if (!state->noWB) { 1126974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 1136974Stjones1@inf.ed.ac.uk !state->isLoad) { 1146974Stjones1@inf.ed.ac.uk writeback(inst, pkt); 1156974Stjones1@inf.ed.ac.uk } else { 1166974Stjones1@inf.ed.ac.uk writeback(inst, state->mainPkt); 1176974Stjones1@inf.ed.ac.uk } 1182678Sktlim@umich.edu } 1192678Sktlim@umich.edu 1202678Sktlim@umich.edu if (inst->isStore()) { 1212678Sktlim@umich.edu completeStore(state->idx); 1222678Sktlim@umich.edu } 1232344SN/A } 1242307SN/A 1256974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 1266974Stjones1@inf.ed.ac.uk delete state->mainPkt->req; 1276974Stjones1@inf.ed.ac.uk delete state->mainPkt; 1286974Stjones1@inf.ed.ac.uk } 1292678Sktlim@umich.edu delete state; 1304032Sktlim@umich.edu delete pkt->req; 1312678Sktlim@umich.edu delete pkt; 1322292SN/A} 1332292SN/A 1342292SN/Atemplate <class Impl> 1352292SN/ALSQUnit<Impl>::LSQUnit() 1368545Ssaidi@eecs.umich.edu : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 1372678Sktlim@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1388727Snilay@cs.wisc.edu loadBlockedHandled(false), storeInFlight(false), hasPendingPkt(false) 1392292SN/A{ 1402292SN/A} 1412292SN/A 1422292SN/Atemplate<class Impl> 1432292SN/Avoid 1445529Snate@binkert.orgLSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 1455529Snate@binkert.org LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 1465529Snate@binkert.org unsigned id) 1472292SN/A{ 1484329Sktlim@umich.edu cpu = cpu_ptr; 1494329Sktlim@umich.edu iewStage = iew_ptr; 1504329Sktlim@umich.edu 1514329Sktlim@umich.edu DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1522292SN/A 1532907Sktlim@umich.edu lsq = lsq_ptr; 1542907Sktlim@umich.edu 1552292SN/A lsqID = id; 1562292SN/A 1572329SN/A // Add 1 for the sentinel entry (they are circular queues). 1582329SN/A LQEntries = maxLQEntries + 1; 1592329SN/A SQEntries = maxSQEntries + 1; 1602292SN/A 1619936SFaissal.Sleiman@arm.com //Due to uint8_t index in LSQSenderState 1629936SFaissal.Sleiman@arm.com assert(LQEntries <= 256); 1639936SFaissal.Sleiman@arm.com assert(SQEntries <= 256); 1649936SFaissal.Sleiman@arm.com 1652292SN/A loadQueue.resize(LQEntries); 1662292SN/A storeQueue.resize(SQEntries); 1672292SN/A 1688199SAli.Saidi@ARM.com depCheckShift = params->LSQDepCheckShift; 1698199SAli.Saidi@ARM.com checkLoads = params->LSQCheckLoads; 1709444SAndreas.Sandberg@ARM.com cachePorts = params->cachePorts; 1719444SAndreas.Sandberg@ARM.com needsTSO = params->needsTSO; 1729444SAndreas.Sandberg@ARM.com 1739444SAndreas.Sandberg@ARM.com resetState(); 1749444SAndreas.Sandberg@ARM.com} 1759444SAndreas.Sandberg@ARM.com 1769444SAndreas.Sandberg@ARM.com 1779444SAndreas.Sandberg@ARM.comtemplate<class Impl> 1789444SAndreas.Sandberg@ARM.comvoid 1799444SAndreas.Sandberg@ARM.comLSQUnit<Impl>::resetState() 1809444SAndreas.Sandberg@ARM.com{ 1819444SAndreas.Sandberg@ARM.com loads = stores = storesToWB = 0; 1828199SAli.Saidi@ARM.com 1832292SN/A loadHead = loadTail = 0; 1842292SN/A 1852292SN/A storeHead = storeWBIdx = storeTail = 0; 1862292SN/A 1872292SN/A usedPorts = 0; 1882292SN/A 1893492Sktlim@umich.edu retryPkt = NULL; 1902329SN/A memDepViolator = NULL; 1912292SN/A 1922292SN/A blockedLoadSeqNum = 0; 1939444SAndreas.Sandberg@ARM.com 1949444SAndreas.Sandberg@ARM.com stalled = false; 1959444SAndreas.Sandberg@ARM.com isLoadBlocked = false; 1969444SAndreas.Sandberg@ARM.com loadBlockedHandled = false; 1979444SAndreas.Sandberg@ARM.com 1989814Sandreas.hansson@arm.com cacheBlockMask = ~(cpu->cacheLineSize() - 1); 1992292SN/A} 2002292SN/A 2012292SN/Atemplate<class Impl> 2022292SN/Astd::string 2032292SN/ALSQUnit<Impl>::name() const 2042292SN/A{ 2052292SN/A if (Impl::MaxThreads == 1) { 2062292SN/A return iewStage->name() + ".lsq"; 2072292SN/A } else { 2088247Snate@binkert.org return iewStage->name() + ".lsq.thread" + to_string(lsqID); 2092292SN/A } 2102292SN/A} 2112292SN/A 2122292SN/Atemplate<class Impl> 2132292SN/Avoid 2142727Sktlim@umich.eduLSQUnit<Impl>::regStats() 2152727Sktlim@umich.edu{ 2162727Sktlim@umich.edu lsqForwLoads 2172727Sktlim@umich.edu .name(name() + ".forwLoads") 2182727Sktlim@umich.edu .desc("Number of loads that had data forwarded from stores"); 2192727Sktlim@umich.edu 2202727Sktlim@umich.edu invAddrLoads 2212727Sktlim@umich.edu .name(name() + ".invAddrLoads") 2222727Sktlim@umich.edu .desc("Number of loads ignored due to an invalid address"); 2232727Sktlim@umich.edu 2242727Sktlim@umich.edu lsqSquashedLoads 2252727Sktlim@umich.edu .name(name() + ".squashedLoads") 2262727Sktlim@umich.edu .desc("Number of loads squashed"); 2272727Sktlim@umich.edu 2282727Sktlim@umich.edu lsqIgnoredResponses 2292727Sktlim@umich.edu .name(name() + ".ignoredResponses") 2302727Sktlim@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 2312727Sktlim@umich.edu 2322361SN/A lsqMemOrderViolation 2332361SN/A .name(name() + ".memOrderViolation") 2342361SN/A .desc("Number of memory ordering violations"); 2352361SN/A 2362727Sktlim@umich.edu lsqSquashedStores 2372727Sktlim@umich.edu .name(name() + ".squashedStores") 2382727Sktlim@umich.edu .desc("Number of stores squashed"); 2392727Sktlim@umich.edu 2402727Sktlim@umich.edu invAddrSwpfs 2412727Sktlim@umich.edu .name(name() + ".invAddrSwpfs") 2422727Sktlim@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 2432727Sktlim@umich.edu 2442727Sktlim@umich.edu lsqBlockedLoads 2452727Sktlim@umich.edu .name(name() + ".blockedLoads") 2462727Sktlim@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 2472727Sktlim@umich.edu 2482727Sktlim@umich.edu lsqRescheduledLoads 2492727Sktlim@umich.edu .name(name() + ".rescheduledLoads") 2502727Sktlim@umich.edu .desc("Number of loads that were rescheduled"); 2512727Sktlim@umich.edu 2522727Sktlim@umich.edu lsqCacheBlocked 2532727Sktlim@umich.edu .name(name() + ".cacheBlocked") 2542727Sktlim@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2552727Sktlim@umich.edu} 2562727Sktlim@umich.edu 2572727Sktlim@umich.edutemplate<class Impl> 2582727Sktlim@umich.eduvoid 2598922Swilliam.wang@arm.comLSQUnit<Impl>::setDcachePort(MasterPort *dcache_port) 2604329Sktlim@umich.edu{ 2614329Sktlim@umich.edu dcachePort = dcache_port; 2624329Sktlim@umich.edu} 2634329Sktlim@umich.edu 2644329Sktlim@umich.edutemplate<class Impl> 2654329Sktlim@umich.eduvoid 2662292SN/ALSQUnit<Impl>::clearLQ() 2672292SN/A{ 2682292SN/A loadQueue.clear(); 2692292SN/A} 2702292SN/A 2712292SN/Atemplate<class Impl> 2722292SN/Avoid 2732292SN/ALSQUnit<Impl>::clearSQ() 2742292SN/A{ 2752292SN/A storeQueue.clear(); 2762292SN/A} 2772292SN/A 2782292SN/Atemplate<class Impl> 2792292SN/Avoid 2809444SAndreas.Sandberg@ARM.comLSQUnit<Impl>::drainSanityCheck() const 2812307SN/A{ 2829444SAndreas.Sandberg@ARM.com for (int i = 0; i < loadQueue.size(); ++i) 2832367SN/A assert(!loadQueue[i]); 2842307SN/A 2852329SN/A assert(storesToWB == 0); 2869444SAndreas.Sandberg@ARM.com assert(!retryPkt); 2872307SN/A} 2882307SN/A 2892307SN/Atemplate<class Impl> 2902307SN/Avoid 2912307SN/ALSQUnit<Impl>::takeOverFrom() 2922307SN/A{ 2939444SAndreas.Sandberg@ARM.com resetState(); 2942307SN/A} 2952307SN/A 2962307SN/Atemplate<class Impl> 2972307SN/Avoid 2982292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 2992292SN/A{ 3002329SN/A unsigned size_plus_sentinel = size + 1; 3012329SN/A assert(size_plus_sentinel >= LQEntries); 3022292SN/A 3032329SN/A if (size_plus_sentinel > LQEntries) { 3042329SN/A while (size_plus_sentinel > loadQueue.size()) { 3052292SN/A DynInstPtr dummy; 3062292SN/A loadQueue.push_back(dummy); 3072292SN/A LQEntries++; 3082292SN/A } 3092292SN/A } else { 3102329SN/A LQEntries = size_plus_sentinel; 3112292SN/A } 3122292SN/A 3139936SFaissal.Sleiman@arm.com assert(LQEntries <= 256); 3142292SN/A} 3152292SN/A 3162292SN/Atemplate<class Impl> 3172292SN/Avoid 3182292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 3192292SN/A{ 3202329SN/A unsigned size_plus_sentinel = size + 1; 3212329SN/A if (size_plus_sentinel > SQEntries) { 3222329SN/A while (size_plus_sentinel > storeQueue.size()) { 3232292SN/A SQEntry dummy; 3242292SN/A storeQueue.push_back(dummy); 3252292SN/A SQEntries++; 3262292SN/A } 3272292SN/A } else { 3282329SN/A SQEntries = size_plus_sentinel; 3292292SN/A } 3309936SFaissal.Sleiman@arm.com 3319936SFaissal.Sleiman@arm.com assert(SQEntries <= 256); 3322292SN/A} 3332292SN/A 3342292SN/Atemplate <class Impl> 3352292SN/Avoid 3362292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 3372292SN/A{ 3382292SN/A assert(inst->isMemRef()); 3392292SN/A 3402292SN/A assert(inst->isLoad() || inst->isStore()); 3412292SN/A 3422292SN/A if (inst->isLoad()) { 3432292SN/A insertLoad(inst); 3442292SN/A } else { 3452292SN/A insertStore(inst); 3462292SN/A } 3472292SN/A 3482292SN/A inst->setInLSQ(); 3492292SN/A} 3502292SN/A 3512292SN/Atemplate <class Impl> 3522292SN/Avoid 3532292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3542292SN/A{ 3552329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3562329SN/A assert(loads < LQEntries); 3572292SN/A 3587720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 3597720Sgblack@eecs.umich.edu load_inst->pcState(), loadTail, load_inst->seqNum); 3602292SN/A 3612292SN/A load_inst->lqIdx = loadTail; 3622292SN/A 3632292SN/A if (stores == 0) { 3642292SN/A load_inst->sqIdx = -1; 3652292SN/A } else { 3662292SN/A load_inst->sqIdx = storeTail; 3672292SN/A } 3682292SN/A 3692292SN/A loadQueue[loadTail] = load_inst; 3702292SN/A 3712292SN/A incrLdIdx(loadTail); 3722292SN/A 3732292SN/A ++loads; 3742292SN/A} 3752292SN/A 3762292SN/Atemplate <class Impl> 3772292SN/Avoid 3782292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3792292SN/A{ 3802292SN/A // Make sure it is not full before inserting an instruction. 3812292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3822292SN/A assert(stores < SQEntries); 3832292SN/A 3847720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 3857720Sgblack@eecs.umich.edu store_inst->pcState(), storeTail, store_inst->seqNum); 3862292SN/A 3872292SN/A store_inst->sqIdx = storeTail; 3882292SN/A store_inst->lqIdx = loadTail; 3892292SN/A 3902292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3912292SN/A 3922292SN/A incrStIdx(storeTail); 3932292SN/A 3942292SN/A ++stores; 3952292SN/A} 3962292SN/A 3972292SN/Atemplate <class Impl> 3982292SN/Atypename Impl::DynInstPtr 3992292SN/ALSQUnit<Impl>::getMemDepViolator() 4002292SN/A{ 4012292SN/A DynInstPtr temp = memDepViolator; 4022292SN/A 4032292SN/A memDepViolator = NULL; 4042292SN/A 4052292SN/A return temp; 4062292SN/A} 4072292SN/A 4082292SN/Atemplate <class Impl> 4092292SN/Aunsigned 4102292SN/ALSQUnit<Impl>::numFreeEntries() 4112292SN/A{ 4122292SN/A unsigned free_lq_entries = LQEntries - loads; 4132292SN/A unsigned free_sq_entries = SQEntries - stores; 4142292SN/A 4152292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 4162292SN/A // empty/full conditions. Subtract 1 from the free entries. 4172292SN/A if (free_lq_entries < free_sq_entries) { 4182292SN/A return free_lq_entries - 1; 4192292SN/A } else { 4202292SN/A return free_sq_entries - 1; 4212292SN/A } 4222292SN/A} 4232292SN/A 4242292SN/Atemplate <class Impl> 4258545Ssaidi@eecs.umich.eduvoid 4268545Ssaidi@eecs.umich.eduLSQUnit<Impl>::checkSnoop(PacketPtr pkt) 4278545Ssaidi@eecs.umich.edu{ 4288545Ssaidi@eecs.umich.edu int load_idx = loadHead; 4298545Ssaidi@eecs.umich.edu 4309383SAli.Saidi@ARM.com // Unlock the cpu-local monitor when the CPU sees a snoop to a locked 4319383SAli.Saidi@ARM.com // address. The CPU can speculatively execute a LL operation after a pending 4329383SAli.Saidi@ARM.com // SC operation in the pipeline and that can make the cache monitor the CPU 4339383SAli.Saidi@ARM.com // is connected to valid while it really shouldn't be. 4349383SAli.Saidi@ARM.com for (int x = 0; x < cpu->numActiveThreads(); x++) { 4359383SAli.Saidi@ARM.com ThreadContext *tc = cpu->getContext(x); 4369383SAli.Saidi@ARM.com bool no_squash = cpu->thread[x]->noSquashFromTC; 4379383SAli.Saidi@ARM.com cpu->thread[x]->noSquashFromTC = true; 4389383SAli.Saidi@ARM.com TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask); 4399383SAli.Saidi@ARM.com cpu->thread[x]->noSquashFromTC = no_squash; 4409383SAli.Saidi@ARM.com } 4419383SAli.Saidi@ARM.com 4428545Ssaidi@eecs.umich.edu // If this is the only load in the LSQ we don't care 4438545Ssaidi@eecs.umich.edu if (load_idx == loadTail) 4448545Ssaidi@eecs.umich.edu return; 4458545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 4468545Ssaidi@eecs.umich.edu 4478545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr()); 4488545Ssaidi@eecs.umich.edu Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 4498545Ssaidi@eecs.umich.edu while (load_idx != loadTail) { 4508545Ssaidi@eecs.umich.edu DynInstPtr ld_inst = loadQueue[load_idx]; 4518545Ssaidi@eecs.umich.edu 4529046SAli.Saidi@ARM.com if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) { 4538545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 4548545Ssaidi@eecs.umich.edu continue; 4558545Ssaidi@eecs.umich.edu } 4568545Ssaidi@eecs.umich.edu 4578545Ssaidi@eecs.umich.edu Addr load_addr = ld_inst->physEffAddr & cacheBlockMask; 4588545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n", 4598545Ssaidi@eecs.umich.edu ld_inst->seqNum, load_addr, invalidate_addr); 4608545Ssaidi@eecs.umich.edu 4618545Ssaidi@eecs.umich.edu if (load_addr == invalidate_addr) { 4629046SAli.Saidi@ARM.com if (ld_inst->possibleLoadViolation()) { 4638545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n", 4648545Ssaidi@eecs.umich.edu ld_inst->physEffAddr, pkt->getAddr(), ld_inst->seqNum); 4658545Ssaidi@eecs.umich.edu 4668545Ssaidi@eecs.umich.edu // Mark the load for re-execution 4678545Ssaidi@eecs.umich.edu ld_inst->fault = new ReExec; 4688545Ssaidi@eecs.umich.edu } else { 4698545Ssaidi@eecs.umich.edu // If a older load checks this and it's true 4708545Ssaidi@eecs.umich.edu // then we might have missed the snoop 4718545Ssaidi@eecs.umich.edu // in which case we need to invalidate to be sure 4729046SAli.Saidi@ARM.com ld_inst->hitExternalSnoop(true); 4738545Ssaidi@eecs.umich.edu } 4748545Ssaidi@eecs.umich.edu } 4758545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 4768545Ssaidi@eecs.umich.edu } 4778545Ssaidi@eecs.umich.edu return; 4788545Ssaidi@eecs.umich.edu} 4798545Ssaidi@eecs.umich.edu 4808545Ssaidi@eecs.umich.edutemplate <class Impl> 4812292SN/AFault 4828199SAli.Saidi@ARM.comLSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) 4838199SAli.Saidi@ARM.com{ 4848199SAli.Saidi@ARM.com Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 4858199SAli.Saidi@ARM.com Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 4868199SAli.Saidi@ARM.com 4878199SAli.Saidi@ARM.com /** @todo in theory you only need to check an instruction that has executed 4888199SAli.Saidi@ARM.com * however, there isn't a good way in the pipeline at the moment to check 4898199SAli.Saidi@ARM.com * all instructions that will execute before the store writes back. Thus, 4908199SAli.Saidi@ARM.com * like the implementation that came before it, we're overly conservative. 4918199SAli.Saidi@ARM.com */ 4928199SAli.Saidi@ARM.com while (load_idx != loadTail) { 4938199SAli.Saidi@ARM.com DynInstPtr ld_inst = loadQueue[load_idx]; 4949046SAli.Saidi@ARM.com if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) { 4958199SAli.Saidi@ARM.com incrLdIdx(load_idx); 4968199SAli.Saidi@ARM.com continue; 4978199SAli.Saidi@ARM.com } 4988199SAli.Saidi@ARM.com 4998199SAli.Saidi@ARM.com Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 5008199SAli.Saidi@ARM.com Addr ld_eff_addr2 = 5018199SAli.Saidi@ARM.com (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 5028199SAli.Saidi@ARM.com 5038272SAli.Saidi@ARM.com if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 5048545Ssaidi@eecs.umich.edu if (inst->isLoad()) { 5058545Ssaidi@eecs.umich.edu // If this load is to the same block as an external snoop 5068545Ssaidi@eecs.umich.edu // invalidate that we've observed then the load needs to be 5078545Ssaidi@eecs.umich.edu // squashed as it could have newer data 5089046SAli.Saidi@ARM.com if (ld_inst->hitExternalSnoop()) { 5098545Ssaidi@eecs.umich.edu if (!memDepViolator || 5108545Ssaidi@eecs.umich.edu ld_inst->seqNum < memDepViolator->seqNum) { 5118545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] " 5128592Sgblack@eecs.umich.edu "and [sn:%lli] at address %#x\n", 5138592Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5148545Ssaidi@eecs.umich.edu memDepViolator = ld_inst; 5158199SAli.Saidi@ARM.com 5168545Ssaidi@eecs.umich.edu ++lsqMemOrderViolation; 5178199SAli.Saidi@ARM.com 5188591Sgblack@eecs.umich.edu return new GenericISA::M5PanicFault( 5198591Sgblack@eecs.umich.edu "Detected fault with inst [sn:%lli] and " 5208591Sgblack@eecs.umich.edu "[sn:%lli] at address %#x\n", 5218591Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5228545Ssaidi@eecs.umich.edu } 5238545Ssaidi@eecs.umich.edu } 5248199SAli.Saidi@ARM.com 5258545Ssaidi@eecs.umich.edu // Otherwise, mark the load has a possible load violation 5268545Ssaidi@eecs.umich.edu // and if we see a snoop before it's commited, we need to squash 5279046SAli.Saidi@ARM.com ld_inst->possibleLoadViolation(true); 5288545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Found possible load violaiton at addr: %#x" 5298545Ssaidi@eecs.umich.edu " between instructions [sn:%lli] and [sn:%lli]\n", 5308545Ssaidi@eecs.umich.edu inst_eff_addr1, inst->seqNum, ld_inst->seqNum); 5318545Ssaidi@eecs.umich.edu } else { 5328545Ssaidi@eecs.umich.edu // A load/store incorrectly passed this store. 5338545Ssaidi@eecs.umich.edu // Check if we already have a violator, or if it's newer 5348545Ssaidi@eecs.umich.edu // squash and refetch. 5358545Ssaidi@eecs.umich.edu if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 5368545Ssaidi@eecs.umich.edu break; 5378545Ssaidi@eecs.umich.edu 5388592Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and " 5398592Sgblack@eecs.umich.edu "[sn:%lli] at address %#x\n", 5408592Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5418545Ssaidi@eecs.umich.edu memDepViolator = ld_inst; 5428545Ssaidi@eecs.umich.edu 5438545Ssaidi@eecs.umich.edu ++lsqMemOrderViolation; 5448545Ssaidi@eecs.umich.edu 5458591Sgblack@eecs.umich.edu return new GenericISA::M5PanicFault("Detected fault with " 5468591Sgblack@eecs.umich.edu "inst [sn:%lli] and [sn:%lli] at address %#x\n", 5478591Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5488545Ssaidi@eecs.umich.edu } 5498199SAli.Saidi@ARM.com } 5508199SAli.Saidi@ARM.com 5518199SAli.Saidi@ARM.com incrLdIdx(load_idx); 5528199SAli.Saidi@ARM.com } 5538199SAli.Saidi@ARM.com return NoFault; 5548199SAli.Saidi@ARM.com} 5558199SAli.Saidi@ARM.com 5568199SAli.Saidi@ARM.com 5578199SAli.Saidi@ARM.com 5588199SAli.Saidi@ARM.com 5598199SAli.Saidi@ARM.comtemplate <class Impl> 5608199SAli.Saidi@ARM.comFault 5612292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 5622292SN/A{ 5634032Sktlim@umich.edu using namespace TheISA; 5642292SN/A // Execute a specific load. 5652292SN/A Fault load_fault = NoFault; 5662292SN/A 5677720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 5687944SGiacomo.Gabrielli@arm.com inst->pcState(), inst->seqNum); 5692292SN/A 5704032Sktlim@umich.edu assert(!inst->isSquashed()); 5714032Sktlim@umich.edu 5722669Sktlim@umich.edu load_fault = inst->initiateAcc(); 5732292SN/A 5747944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 5757944SGiacomo.Gabrielli@arm.com load_fault == NoFault) 5767944SGiacomo.Gabrielli@arm.com return load_fault; 5777944SGiacomo.Gabrielli@arm.com 5787597Sminkyu.jeong@arm.com // If the instruction faulted or predicated false, then we need to send it 5797597Sminkyu.jeong@arm.com // along to commit without the instruction completing. 5807597Sminkyu.jeong@arm.com if (load_fault != NoFault || inst->readPredicate() == false) { 5812329SN/A // Send this instruction to commit, also make sure iew stage 5822329SN/A // realizes there is activity. 5832367SN/A // Mark it as executed unless it is an uncached load that 5842367SN/A // needs to hit the head of commit. 5857848SAli.Saidi@ARM.com if (inst->readPredicate() == false) 5867848SAli.Saidi@ARM.com inst->forwardOldRegs(); 5877600Sminkyu.jeong@arm.com DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 5887600Sminkyu.jeong@arm.com inst->seqNum, 5897600Sminkyu.jeong@arm.com (load_fault != NoFault ? "fault" : "predication")); 5904032Sktlim@umich.edu if (!(inst->hasRequest() && inst->uncacheable()) || 5913731Sktlim@umich.edu inst->isAtCommit()) { 5922367SN/A inst->setExecuted(); 5932367SN/A } 5942292SN/A iewStage->instToCommit(inst); 5952292SN/A iewStage->activityThisCycle(); 5964032Sktlim@umich.edu } else if (!loadBlocked()) { 5979046SAli.Saidi@ARM.com assert(inst->effAddrValid()); 5984032Sktlim@umich.edu int load_idx = inst->lqIdx; 5994032Sktlim@umich.edu incrLdIdx(load_idx); 6004032Sktlim@umich.edu 6018199SAli.Saidi@ARM.com if (checkLoads) 6028199SAli.Saidi@ARM.com return checkViolations(load_idx, inst); 6032292SN/A } 6042292SN/A 6052292SN/A return load_fault; 6062292SN/A} 6072292SN/A 6082292SN/Atemplate <class Impl> 6092292SN/AFault 6102292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 6112292SN/A{ 6122292SN/A using namespace TheISA; 6132292SN/A // Make sure that a store exists. 6142292SN/A assert(stores != 0); 6152292SN/A 6162292SN/A int store_idx = store_inst->sqIdx; 6172292SN/A 6187720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 6197720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 6202292SN/A 6214032Sktlim@umich.edu assert(!store_inst->isSquashed()); 6224032Sktlim@umich.edu 6232292SN/A // Check the recently completed loads to see if any match this store's 6242292SN/A // address. If so, then we have a memory ordering violation. 6252292SN/A int load_idx = store_inst->lqIdx; 6262292SN/A 6272292SN/A Fault store_fault = store_inst->initiateAcc(); 6282292SN/A 6297944SGiacomo.Gabrielli@arm.com if (store_inst->isTranslationDelayed() && 6307944SGiacomo.Gabrielli@arm.com store_fault == NoFault) 6317944SGiacomo.Gabrielli@arm.com return store_fault; 6327944SGiacomo.Gabrielli@arm.com 6337848SAli.Saidi@ARM.com if (store_inst->readPredicate() == false) 6347848SAli.Saidi@ARM.com store_inst->forwardOldRegs(); 6357848SAli.Saidi@ARM.com 6362329SN/A if (storeQueue[store_idx].size == 0) { 6377782Sminkyu.jeong@arm.com DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 6387720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 6392292SN/A 6402292SN/A return store_fault; 6417782Sminkyu.jeong@arm.com } else if (store_inst->readPredicate() == false) { 6427782Sminkyu.jeong@arm.com DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 6437782Sminkyu.jeong@arm.com store_inst->seqNum); 6447782Sminkyu.jeong@arm.com return store_fault; 6452292SN/A } 6462292SN/A 6472292SN/A assert(store_fault == NoFault); 6482292SN/A 6492336SN/A if (store_inst->isStoreConditional()) { 6502336SN/A // Store conditionals need to set themselves as able to 6512336SN/A // writeback if we haven't had a fault by here. 6522329SN/A storeQueue[store_idx].canWB = true; 6532292SN/A 6542329SN/A ++storesToWB; 6552292SN/A } 6562292SN/A 6578199SAli.Saidi@ARM.com return checkViolations(load_idx, store_inst); 6582292SN/A 6592292SN/A} 6602292SN/A 6612292SN/Atemplate <class Impl> 6622292SN/Avoid 6632292SN/ALSQUnit<Impl>::commitLoad() 6642292SN/A{ 6652292SN/A assert(loadQueue[loadHead]); 6662292SN/A 6677720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 6687720Sgblack@eecs.umich.edu loadQueue[loadHead]->pcState()); 6692292SN/A 6702292SN/A loadQueue[loadHead] = NULL; 6712292SN/A 6722292SN/A incrLdIdx(loadHead); 6732292SN/A 6742292SN/A --loads; 6752292SN/A} 6762292SN/A 6772292SN/Atemplate <class Impl> 6782292SN/Avoid 6792292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 6802292SN/A{ 6812292SN/A assert(loads == 0 || loadQueue[loadHead]); 6822292SN/A 6832292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 6842292SN/A commitLoad(); 6852292SN/A } 6862292SN/A} 6872292SN/A 6882292SN/Atemplate <class Impl> 6892292SN/Avoid 6902292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 6912292SN/A{ 6922292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 6932292SN/A 6942292SN/A int store_idx = storeHead; 6952292SN/A 6962292SN/A while (store_idx != storeTail) { 6972292SN/A assert(storeQueue[store_idx].inst); 6982329SN/A // Mark any stores that are now committed and have not yet 6992329SN/A // been marked as able to write back. 7002292SN/A if (!storeQueue[store_idx].canWB) { 7012292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 7022292SN/A break; 7032292SN/A } 7042292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 7057720Sgblack@eecs.umich.edu "%s [sn:%lli]\n", 7067720Sgblack@eecs.umich.edu storeQueue[store_idx].inst->pcState(), 7072292SN/A storeQueue[store_idx].inst->seqNum); 7082292SN/A 7092292SN/A storeQueue[store_idx].canWB = true; 7102292SN/A 7112292SN/A ++storesToWB; 7122292SN/A } 7132292SN/A 7142292SN/A incrStIdx(store_idx); 7152292SN/A } 7162292SN/A} 7172292SN/A 7182292SN/Atemplate <class Impl> 7192292SN/Avoid 7206974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::writebackPendingStore() 7216974Stjones1@inf.ed.ac.uk{ 7226974Stjones1@inf.ed.ac.uk if (hasPendingPkt) { 7236974Stjones1@inf.ed.ac.uk assert(pendingPkt != NULL); 7246974Stjones1@inf.ed.ac.uk 7256974Stjones1@inf.ed.ac.uk // If the cache is blocked, this will store the packet for retry. 7266974Stjones1@inf.ed.ac.uk if (sendStore(pendingPkt)) { 7276974Stjones1@inf.ed.ac.uk storePostSend(pendingPkt); 7286974Stjones1@inf.ed.ac.uk } 7296974Stjones1@inf.ed.ac.uk pendingPkt = NULL; 7306974Stjones1@inf.ed.ac.uk hasPendingPkt = false; 7316974Stjones1@inf.ed.ac.uk } 7326974Stjones1@inf.ed.ac.uk} 7336974Stjones1@inf.ed.ac.uk 7346974Stjones1@inf.ed.ac.uktemplate <class Impl> 7356974Stjones1@inf.ed.ac.ukvoid 7362292SN/ALSQUnit<Impl>::writebackStores() 7372292SN/A{ 7386974Stjones1@inf.ed.ac.uk // First writeback the second packet from any split store that didn't 7396974Stjones1@inf.ed.ac.uk // complete last cycle because there weren't enough cache ports available. 7406974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc) { 7416974Stjones1@inf.ed.ac.uk writebackPendingStore(); 7426974Stjones1@inf.ed.ac.uk } 7436974Stjones1@inf.ed.ac.uk 7442292SN/A while (storesToWB > 0 && 7452292SN/A storeWBIdx != storeTail && 7462292SN/A storeQueue[storeWBIdx].inst && 7472292SN/A storeQueue[storeWBIdx].canWB && 7488727Snilay@cs.wisc.edu ((!needsTSO) || (!storeInFlight)) && 7492292SN/A usedPorts < cachePorts) { 7502292SN/A 7512907Sktlim@umich.edu if (isStoreBlocked || lsq->cacheBlocked()) { 7522678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 7532678Sktlim@umich.edu " is blocked!\n"); 7542678Sktlim@umich.edu break; 7552678Sktlim@umich.edu } 7562678Sktlim@umich.edu 7572329SN/A // Store didn't write any data so no need to write it back to 7582329SN/A // memory. 7592292SN/A if (storeQueue[storeWBIdx].size == 0) { 7602292SN/A completeStore(storeWBIdx); 7612292SN/A 7622292SN/A incrStIdx(storeWBIdx); 7632292SN/A 7642292SN/A continue; 7652292SN/A } 7662678Sktlim@umich.edu 7672292SN/A ++usedPorts; 7682292SN/A 7692292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 7702292SN/A incrStIdx(storeWBIdx); 7712292SN/A 7722292SN/A continue; 7732292SN/A } 7742292SN/A 7752292SN/A assert(storeQueue[storeWBIdx].req); 7762292SN/A assert(!storeQueue[storeWBIdx].committed); 7772292SN/A 7786974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 7796974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqLow); 7806974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqHigh); 7816974Stjones1@inf.ed.ac.uk } 7826974Stjones1@inf.ed.ac.uk 7832669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 7842669Sktlim@umich.edu 7852669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 7868481Sgblack@eecs.umich.edu RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 7878481Sgblack@eecs.umich.edu RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 7888481Sgblack@eecs.umich.edu 7892292SN/A storeQueue[storeWBIdx].committed = true; 7902292SN/A 7912669Sktlim@umich.edu assert(!inst->memData); 7922669Sktlim@umich.edu inst->memData = new uint8_t[64]; 7933772Sgblack@eecs.umich.edu 7944326Sgblack@eecs.umich.edu memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 7952669Sktlim@umich.edu 7964878Sstever@eecs.umich.edu MemCmd command = 7974878Sstever@eecs.umich.edu req->isSwap() ? MemCmd::SwapReq : 7986102Sgblack@eecs.umich.edu (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 7996974Stjones1@inf.ed.ac.uk PacketPtr data_pkt; 8006974Stjones1@inf.ed.ac.uk PacketPtr snd_data_pkt = NULL; 8012292SN/A 8022678Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 8032678Sktlim@umich.edu state->isLoad = false; 8042678Sktlim@umich.edu state->idx = storeWBIdx; 8052678Sktlim@umich.edu state->inst = inst; 8066974Stjones1@inf.ed.ac.uk 8076974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 8086974Stjones1@inf.ed.ac.uk 8096974Stjones1@inf.ed.ac.uk // Build a single data packet if the store isn't split. 8108949Sandreas.hansson@arm.com data_pkt = new Packet(req, command); 8116974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 8126974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 8136974Stjones1@inf.ed.ac.uk } else { 8146974Stjones1@inf.ed.ac.uk // Create two packets if the store is split in two. 8158949Sandreas.hansson@arm.com data_pkt = new Packet(sreqLow, command); 8168949Sandreas.hansson@arm.com snd_data_pkt = new Packet(sreqHigh, command); 8176974Stjones1@inf.ed.ac.uk 8186974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 8196974Stjones1@inf.ed.ac.uk snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 8206974Stjones1@inf.ed.ac.uk 8216974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 8226974Stjones1@inf.ed.ac.uk snd_data_pkt->senderState = state; 8236974Stjones1@inf.ed.ac.uk 8246974Stjones1@inf.ed.ac.uk state->isSplit = true; 8256974Stjones1@inf.ed.ac.uk state->outstanding = 2; 8266974Stjones1@inf.ed.ac.uk 8276974Stjones1@inf.ed.ac.uk // Can delete the main request now. 8286974Stjones1@inf.ed.ac.uk delete req; 8296974Stjones1@inf.ed.ac.uk req = sreqLow; 8306974Stjones1@inf.ed.ac.uk } 8312678Sktlim@umich.edu 8327720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 8332292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 8347720Sgblack@eecs.umich.edu storeWBIdx, inst->pcState(), 8353797Sgblack@eecs.umich.edu req->getPaddr(), (int)*(inst->memData), 8363221Sktlim@umich.edu inst->seqNum); 8372292SN/A 8382693Sktlim@umich.edu // @todo: Remove this SC hack once the memory system handles it. 8394350Sgblack@eecs.umich.edu if (inst->isStoreConditional()) { 8406974Stjones1@inf.ed.ac.uk assert(!storeQueue[storeWBIdx].isSplit); 8413326Sktlim@umich.edu // Disable recording the result temporarily. Writing to 8423326Sktlim@umich.edu // misc regs normally updates the result, but this is not 8433326Sktlim@umich.edu // the desired behavior when handling store conditionals. 8449046SAli.Saidi@ARM.com inst->recordResult(false); 8453326Sktlim@umich.edu bool success = TheISA::handleLockedWrite(inst.get(), req); 8469046SAli.Saidi@ARM.com inst->recordResult(true); 8473326Sktlim@umich.edu 8483326Sktlim@umich.edu if (!success) { 8493326Sktlim@umich.edu // Instantly complete this store. 8503326Sktlim@umich.edu DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 8513326Sktlim@umich.edu "Instantly completing it.\n", 8523326Sktlim@umich.edu inst->seqNum); 8533326Sktlim@umich.edu WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 8547823Ssteve.reinhardt@amd.com cpu->schedule(wb, curTick() + 1); 8558887Sgeoffrey.blake@arm.com if (cpu->checker) { 8568887Sgeoffrey.blake@arm.com // Make sure to set the LLSC data for verification 8578887Sgeoffrey.blake@arm.com // if checker is loaded 8588887Sgeoffrey.blake@arm.com inst->reqToVerify->setExtraData(0); 8598887Sgeoffrey.blake@arm.com inst->completeAcc(data_pkt); 8608887Sgeoffrey.blake@arm.com } 8613326Sktlim@umich.edu completeStore(storeWBIdx); 8623326Sktlim@umich.edu incrStIdx(storeWBIdx); 8633326Sktlim@umich.edu continue; 8642693Sktlim@umich.edu } 8652693Sktlim@umich.edu } else { 8662693Sktlim@umich.edu // Non-store conditionals do not need a writeback. 8672693Sktlim@umich.edu state->noWB = true; 8682693Sktlim@umich.edu } 8692693Sktlim@umich.edu 8708481Sgblack@eecs.umich.edu bool split = 8718481Sgblack@eecs.umich.edu TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit; 8728481Sgblack@eecs.umich.edu 8738481Sgblack@eecs.umich.edu ThreadContext *thread = cpu->tcBase(lsqID); 8748481Sgblack@eecs.umich.edu 8758481Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 8768481Sgblack@eecs.umich.edu assert(!inst->isStoreConditional()); 8778481Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread, data_pkt); 8788481Sgblack@eecs.umich.edu delete data_pkt; 8798481Sgblack@eecs.umich.edu if (split) { 8808481Sgblack@eecs.umich.edu assert(snd_data_pkt->req->isMmappedIpr()); 8818481Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread, snd_data_pkt); 8828481Sgblack@eecs.umich.edu delete snd_data_pkt; 8838481Sgblack@eecs.umich.edu delete sreqLow; 8848481Sgblack@eecs.umich.edu delete sreqHigh; 8858481Sgblack@eecs.umich.edu } 8868481Sgblack@eecs.umich.edu delete state; 8878481Sgblack@eecs.umich.edu delete req; 8888481Sgblack@eecs.umich.edu completeStore(storeWBIdx); 8898481Sgblack@eecs.umich.edu incrStIdx(storeWBIdx); 8908481Sgblack@eecs.umich.edu } else if (!sendStore(data_pkt)) { 8914032Sktlim@umich.edu DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 8923221Sktlim@umich.edu "retry later\n", 8933221Sktlim@umich.edu inst->seqNum); 8946974Stjones1@inf.ed.ac.uk 8956974Stjones1@inf.ed.ac.uk // Need to store the second packet, if split. 8968481Sgblack@eecs.umich.edu if (split) { 8976974Stjones1@inf.ed.ac.uk state->pktToSend = true; 8986974Stjones1@inf.ed.ac.uk state->pendingPacket = snd_data_pkt; 8996974Stjones1@inf.ed.ac.uk } 9002669Sktlim@umich.edu } else { 9016974Stjones1@inf.ed.ac.uk 9026974Stjones1@inf.ed.ac.uk // If split, try to send the second packet too 9038481Sgblack@eecs.umich.edu if (split) { 9046974Stjones1@inf.ed.ac.uk assert(snd_data_pkt); 9056974Stjones1@inf.ed.ac.uk 9066974Stjones1@inf.ed.ac.uk // Ensure there are enough ports to use. 9076974Stjones1@inf.ed.ac.uk if (usedPorts < cachePorts) { 9086974Stjones1@inf.ed.ac.uk ++usedPorts; 9096974Stjones1@inf.ed.ac.uk if (sendStore(snd_data_pkt)) { 9106974Stjones1@inf.ed.ac.uk storePostSend(snd_data_pkt); 9116974Stjones1@inf.ed.ac.uk } else { 9126974Stjones1@inf.ed.ac.uk DPRINTF(IEW, "D-Cache became blocked when writing" 9136974Stjones1@inf.ed.ac.uk " [sn:%lli] second packet, will retry later\n", 9146974Stjones1@inf.ed.ac.uk inst->seqNum); 9156974Stjones1@inf.ed.ac.uk } 9166974Stjones1@inf.ed.ac.uk } else { 9176974Stjones1@inf.ed.ac.uk 9186974Stjones1@inf.ed.ac.uk // Store the packet for when there's free ports. 9196974Stjones1@inf.ed.ac.uk assert(pendingPkt == NULL); 9206974Stjones1@inf.ed.ac.uk pendingPkt = snd_data_pkt; 9216974Stjones1@inf.ed.ac.uk hasPendingPkt = true; 9226974Stjones1@inf.ed.ac.uk } 9236974Stjones1@inf.ed.ac.uk } else { 9246974Stjones1@inf.ed.ac.uk 9256974Stjones1@inf.ed.ac.uk // Not a split store. 9266974Stjones1@inf.ed.ac.uk storePostSend(data_pkt); 9276974Stjones1@inf.ed.ac.uk } 9282292SN/A } 9292292SN/A } 9302292SN/A 9312292SN/A // Not sure this should set it to 0. 9322292SN/A usedPorts = 0; 9332292SN/A 9342292SN/A assert(stores >= 0 && storesToWB >= 0); 9352292SN/A} 9362292SN/A 9372292SN/A/*template <class Impl> 9382292SN/Avoid 9392292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 9402292SN/A{ 9412292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 9422292SN/A mshrSeqNums.end(), 9432292SN/A seqNum); 9442292SN/A 9452292SN/A if (mshr_it != mshrSeqNums.end()) { 9462292SN/A mshrSeqNums.erase(mshr_it); 9472292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 9482292SN/A } 9492292SN/A}*/ 9502292SN/A 9512292SN/Atemplate <class Impl> 9522292SN/Avoid 9532292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 9542292SN/A{ 9552292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 9562329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 9572292SN/A 9582292SN/A int load_idx = loadTail; 9592292SN/A decrLdIdx(load_idx); 9602292SN/A 9612292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 9627720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 9632292SN/A "[sn:%lli]\n", 9647720Sgblack@eecs.umich.edu loadQueue[load_idx]->pcState(), 9652292SN/A loadQueue[load_idx]->seqNum); 9662292SN/A 9672292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 9682292SN/A stalled = false; 9692292SN/A stallingStoreIsn = 0; 9702292SN/A stallingLoadIdx = 0; 9712292SN/A } 9722292SN/A 9732329SN/A // Clear the smart pointer to make sure it is decremented. 9742731Sktlim@umich.edu loadQueue[load_idx]->setSquashed(); 9752292SN/A loadQueue[load_idx] = NULL; 9762292SN/A --loads; 9772292SN/A 9782292SN/A // Inefficient! 9792292SN/A loadTail = load_idx; 9802292SN/A 9812292SN/A decrLdIdx(load_idx); 9822727Sktlim@umich.edu ++lsqSquashedLoads; 9832292SN/A } 9842292SN/A 9852292SN/A if (isLoadBlocked) { 9862292SN/A if (squashed_num < blockedLoadSeqNum) { 9872292SN/A isLoadBlocked = false; 9882292SN/A loadBlockedHandled = false; 9892292SN/A blockedLoadSeqNum = 0; 9902292SN/A } 9912292SN/A } 9922292SN/A 9934032Sktlim@umich.edu if (memDepViolator && squashed_num < memDepViolator->seqNum) { 9944032Sktlim@umich.edu memDepViolator = NULL; 9954032Sktlim@umich.edu } 9964032Sktlim@umich.edu 9972292SN/A int store_idx = storeTail; 9982292SN/A decrStIdx(store_idx); 9992292SN/A 10002292SN/A while (stores != 0 && 10012292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 10022329SN/A // Instructions marked as can WB are already committed. 10032292SN/A if (storeQueue[store_idx].canWB) { 10042292SN/A break; 10052292SN/A } 10062292SN/A 10077720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 10082292SN/A "idx:%i [sn:%lli]\n", 10097720Sgblack@eecs.umich.edu storeQueue[store_idx].inst->pcState(), 10102292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 10112292SN/A 10122329SN/A // I don't think this can happen. It should have been cleared 10132329SN/A // by the stalling load. 10142292SN/A if (isStalled() && 10152292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 10162292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 10172292SN/A stalled = false; 10182292SN/A stallingStoreIsn = 0; 10192292SN/A } 10202292SN/A 10212329SN/A // Clear the smart pointer to make sure it is decremented. 10222731Sktlim@umich.edu storeQueue[store_idx].inst->setSquashed(); 10232292SN/A storeQueue[store_idx].inst = NULL; 10242292SN/A storeQueue[store_idx].canWB = 0; 10252292SN/A 10264032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 10274032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the proper 10284032Sktlim@umich.edu // place to really handle request deletes. 10294032Sktlim@umich.edu delete storeQueue[store_idx].req; 10306974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 10316974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqLow; 10326974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqHigh; 10336974Stjones1@inf.ed.ac.uk 10346974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqLow = NULL; 10356974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqHigh = NULL; 10366974Stjones1@inf.ed.ac.uk } 10374032Sktlim@umich.edu 10382292SN/A storeQueue[store_idx].req = NULL; 10392292SN/A --stores; 10402292SN/A 10412292SN/A // Inefficient! 10422292SN/A storeTail = store_idx; 10432292SN/A 10442292SN/A decrStIdx(store_idx); 10452727Sktlim@umich.edu ++lsqSquashedStores; 10462292SN/A } 10472292SN/A} 10482292SN/A 10492292SN/Atemplate <class Impl> 10502292SN/Avoid 10513349Sbinkertn@umich.eduLSQUnit<Impl>::storePostSend(PacketPtr pkt) 10522693Sktlim@umich.edu{ 10532693Sktlim@umich.edu if (isStalled() && 10542693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 10552693Sktlim@umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 10562693Sktlim@umich.edu "load idx:%i\n", 10572693Sktlim@umich.edu stallingStoreIsn, stallingLoadIdx); 10582693Sktlim@umich.edu stalled = false; 10592693Sktlim@umich.edu stallingStoreIsn = 0; 10602693Sktlim@umich.edu iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 10612693Sktlim@umich.edu } 10622693Sktlim@umich.edu 10632693Sktlim@umich.edu if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 10642693Sktlim@umich.edu // The store is basically completed at this time. This 10652693Sktlim@umich.edu // only works so long as the checker doesn't try to 10662693Sktlim@umich.edu // verify the value in memory for stores. 10672693Sktlim@umich.edu storeQueue[storeWBIdx].inst->setCompleted(); 10688887Sgeoffrey.blake@arm.com 10692693Sktlim@umich.edu if (cpu->checker) { 10702732Sktlim@umich.edu cpu->checker->verify(storeQueue[storeWBIdx].inst); 10712693Sktlim@umich.edu } 10722693Sktlim@umich.edu } 10732693Sktlim@umich.edu 10748727Snilay@cs.wisc.edu if (needsTSO) { 10758727Snilay@cs.wisc.edu storeInFlight = true; 10768727Snilay@cs.wisc.edu } 10778727Snilay@cs.wisc.edu 10782693Sktlim@umich.edu incrStIdx(storeWBIdx); 10792693Sktlim@umich.edu} 10802693Sktlim@umich.edu 10812693Sktlim@umich.edutemplate <class Impl> 10822693Sktlim@umich.eduvoid 10832678Sktlim@umich.eduLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 10842678Sktlim@umich.edu{ 10852678Sktlim@umich.edu iewStage->wakeCPU(); 10862678Sktlim@umich.edu 10872678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 10882678Sktlim@umich.edu if (inst->isSquashed()) { 10892927Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 10902678Sktlim@umich.edu assert(!inst->isStore()); 10912727Sktlim@umich.edu ++lsqIgnoredResponses; 10922678Sktlim@umich.edu return; 10932678Sktlim@umich.edu } 10942678Sktlim@umich.edu 10952678Sktlim@umich.edu if (!inst->isExecuted()) { 10962678Sktlim@umich.edu inst->setExecuted(); 10972678Sktlim@umich.edu 10982678Sktlim@umich.edu // Complete access to copy data to proper place. 10992678Sktlim@umich.edu inst->completeAcc(pkt); 11002678Sktlim@umich.edu } 11012678Sktlim@umich.edu 11022678Sktlim@umich.edu // Need to insert instruction into queue to commit 11032678Sktlim@umich.edu iewStage->instToCommit(inst); 11042678Sktlim@umich.edu 11052678Sktlim@umich.edu iewStage->activityThisCycle(); 11067598Sminkyu.jeong@arm.com 11077598Sminkyu.jeong@arm.com // see if this load changed the PC 11087598Sminkyu.jeong@arm.com iewStage->checkMisprediction(inst); 11092678Sktlim@umich.edu} 11102678Sktlim@umich.edu 11112678Sktlim@umich.edutemplate <class Impl> 11122678Sktlim@umich.eduvoid 11132292SN/ALSQUnit<Impl>::completeStore(int store_idx) 11142292SN/A{ 11152292SN/A assert(storeQueue[store_idx].inst); 11162292SN/A storeQueue[store_idx].completed = true; 11172292SN/A --storesToWB; 11182292SN/A // A bit conservative because a store completion may not free up entries, 11192292SN/A // but hopefully avoids two store completions in one cycle from making 11202292SN/A // the CPU tick twice. 11213126Sktlim@umich.edu cpu->wakeCPU(); 11222292SN/A cpu->activityThisCycle(); 11232292SN/A 11242292SN/A if (store_idx == storeHead) { 11252292SN/A do { 11262292SN/A incrStIdx(storeHead); 11272292SN/A 11282292SN/A --stores; 11292292SN/A } while (storeQueue[storeHead].completed && 11302292SN/A storeHead != storeTail); 11312292SN/A 11322292SN/A iewStage->updateLSQNextCycle = true; 11332292SN/A } 11342292SN/A 11352329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 11362329SN/A "idx:%i\n", 11372329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 11382292SN/A 11399527SMatt.Horsnell@arm.com#if TRACING_ON 11409527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 11419527SMatt.Horsnell@arm.com storeQueue[store_idx].inst->storeTick = 11429527SMatt.Horsnell@arm.com curTick() - storeQueue[store_idx].inst->fetchTick; 11439527SMatt.Horsnell@arm.com } 11449527SMatt.Horsnell@arm.com#endif 11459527SMatt.Horsnell@arm.com 11462292SN/A if (isStalled() && 11472292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 11482292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 11492292SN/A "load idx:%i\n", 11502292SN/A stallingStoreIsn, stallingLoadIdx); 11512292SN/A stalled = false; 11522292SN/A stallingStoreIsn = 0; 11532292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 11542292SN/A } 11552316SN/A 11562316SN/A storeQueue[store_idx].inst->setCompleted(); 11572329SN/A 11588727Snilay@cs.wisc.edu if (needsTSO) { 11598727Snilay@cs.wisc.edu storeInFlight = false; 11608727Snilay@cs.wisc.edu } 11618727Snilay@cs.wisc.edu 11622329SN/A // Tell the checker we've completed this instruction. Some stores 11632329SN/A // may get reported twice to the checker, but the checker can 11642329SN/A // handle that case. 11652316SN/A if (cpu->checker) { 11662732Sktlim@umich.edu cpu->checker->verify(storeQueue[store_idx].inst); 11672316SN/A } 11682292SN/A} 11692292SN/A 11702292SN/Atemplate <class Impl> 11716974Stjones1@inf.ed.ac.ukbool 11726974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::sendStore(PacketPtr data_pkt) 11736974Stjones1@inf.ed.ac.uk{ 11748975Sandreas.hansson@arm.com if (!dcachePort->sendTimingReq(data_pkt)) { 11756974Stjones1@inf.ed.ac.uk // Need to handle becoming blocked on a store. 11766974Stjones1@inf.ed.ac.uk isStoreBlocked = true; 11776974Stjones1@inf.ed.ac.uk ++lsqCacheBlocked; 11786974Stjones1@inf.ed.ac.uk assert(retryPkt == NULL); 11796974Stjones1@inf.ed.ac.uk retryPkt = data_pkt; 11806974Stjones1@inf.ed.ac.uk lsq->setRetryTid(lsqID); 11816974Stjones1@inf.ed.ac.uk return false; 11826974Stjones1@inf.ed.ac.uk } 11836974Stjones1@inf.ed.ac.uk return true; 11846974Stjones1@inf.ed.ac.uk} 11856974Stjones1@inf.ed.ac.uk 11866974Stjones1@inf.ed.ac.uktemplate <class Impl> 11872693Sktlim@umich.eduvoid 11882693Sktlim@umich.eduLSQUnit<Impl>::recvRetry() 11892693Sktlim@umich.edu{ 11902698Sktlim@umich.edu if (isStoreBlocked) { 11914985Sktlim@umich.edu DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 11922698Sktlim@umich.edu assert(retryPkt != NULL); 11932693Sktlim@umich.edu 11948587Snilay@cs.wisc.edu LSQSenderState *state = 11958587Snilay@cs.wisc.edu dynamic_cast<LSQSenderState *>(retryPkt->senderState); 11968587Snilay@cs.wisc.edu 11978975Sandreas.hansson@arm.com if (dcachePort->sendTimingReq(retryPkt)) { 11986974Stjones1@inf.ed.ac.uk // Don't finish the store unless this is the last packet. 11998133SAli.Saidi@ARM.com if (!TheISA::HasUnalignedMemAcc || !state->pktToSend || 12008133SAli.Saidi@ARM.com state->pendingPacket == retryPkt) { 12018133SAli.Saidi@ARM.com state->pktToSend = false; 12026974Stjones1@inf.ed.ac.uk storePostSend(retryPkt); 12036974Stjones1@inf.ed.ac.uk } 12042699Sktlim@umich.edu retryPkt = NULL; 12052693Sktlim@umich.edu isStoreBlocked = false; 12066221Snate@binkert.org lsq->setRetryTid(InvalidThreadID); 12076974Stjones1@inf.ed.ac.uk 12086974Stjones1@inf.ed.ac.uk // Send any outstanding packet. 12096974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 12106974Stjones1@inf.ed.ac.uk assert(state->pendingPacket); 12116974Stjones1@inf.ed.ac.uk if (sendStore(state->pendingPacket)) { 12126974Stjones1@inf.ed.ac.uk storePostSend(state->pendingPacket); 12136974Stjones1@inf.ed.ac.uk } 12146974Stjones1@inf.ed.ac.uk } 12152693Sktlim@umich.edu } else { 12162693Sktlim@umich.edu // Still blocked! 12172727Sktlim@umich.edu ++lsqCacheBlocked; 12182907Sktlim@umich.edu lsq->setRetryTid(lsqID); 12192693Sktlim@umich.edu } 12202693Sktlim@umich.edu } else if (isLoadBlocked) { 12212693Sktlim@umich.edu DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 12222693Sktlim@umich.edu "no need to resend packet.\n"); 12232693Sktlim@umich.edu } else { 12242693Sktlim@umich.edu DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 12252693Sktlim@umich.edu } 12262693Sktlim@umich.edu} 12272693Sktlim@umich.edu 12282693Sktlim@umich.edutemplate <class Impl> 12292292SN/Ainline void 12309440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::incrStIdx(int &store_idx) const 12312292SN/A{ 12322292SN/A if (++store_idx >= SQEntries) 12332292SN/A store_idx = 0; 12342292SN/A} 12352292SN/A 12362292SN/Atemplate <class Impl> 12372292SN/Ainline void 12389440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::decrStIdx(int &store_idx) const 12392292SN/A{ 12402292SN/A if (--store_idx < 0) 12412292SN/A store_idx += SQEntries; 12422292SN/A} 12432292SN/A 12442292SN/Atemplate <class Impl> 12452292SN/Ainline void 12469440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::incrLdIdx(int &load_idx) const 12472292SN/A{ 12482292SN/A if (++load_idx >= LQEntries) 12492292SN/A load_idx = 0; 12502292SN/A} 12512292SN/A 12522292SN/Atemplate <class Impl> 12532292SN/Ainline void 12549440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::decrLdIdx(int &load_idx) const 12552292SN/A{ 12562292SN/A if (--load_idx < 0) 12572292SN/A load_idx += LQEntries; 12582292SN/A} 12592329SN/A 12602329SN/Atemplate <class Impl> 12612329SN/Avoid 12629440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::dumpInsts() const 12632329SN/A{ 12642329SN/A cprintf("Load store queue: Dumping instructions.\n"); 12652329SN/A cprintf("Load queue size: %i\n", loads); 12662329SN/A cprintf("Load queue: "); 12672329SN/A 12682329SN/A int load_idx = loadHead; 12692329SN/A 12702329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 12719440SAndreas.Sandberg@ARM.com const DynInstPtr &inst(loadQueue[load_idx]); 12729440SAndreas.Sandberg@ARM.com cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 12732329SN/A 12742329SN/A incrLdIdx(load_idx); 12752329SN/A } 12769440SAndreas.Sandberg@ARM.com cprintf("\n"); 12772329SN/A 12782329SN/A cprintf("Store queue size: %i\n", stores); 12792329SN/A cprintf("Store queue: "); 12802329SN/A 12812329SN/A int store_idx = storeHead; 12822329SN/A 12832329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 12849440SAndreas.Sandberg@ARM.com const DynInstPtr &inst(storeQueue[store_idx].inst); 12859440SAndreas.Sandberg@ARM.com cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 12862329SN/A 12872329SN/A incrStIdx(store_idx); 12882329SN/A } 12892329SN/A 12902329SN/A cprintf("\n"); 12912329SN/A} 1292