lsq_unit_impl.hh revision 8922
12292SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2010-2011 ARM Limited 37597Sminkyu.jeong@arm.com * All rights reserved 47597Sminkyu.jeong@arm.com * 57597Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67597Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77597Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87597Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97597Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107597Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117597Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127597Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137597Sminkyu.jeong@arm.com * 142292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 152292SN/A * All rights reserved. 162292SN/A * 172292SN/A * Redistribution and use in source and binary forms, with or without 182292SN/A * modification, are permitted provided that the following conditions are 192292SN/A * met: redistributions of source code must retain the above copyright 202292SN/A * notice, this list of conditions and the following disclaimer; 212292SN/A * redistributions in binary form must reproduce the above copyright 222292SN/A * notice, this list of conditions and the following disclaimer in the 232292SN/A * documentation and/or other materials provided with the distribution; 242292SN/A * neither the name of the copyright holders nor the names of its 252292SN/A * contributors may be used to endorse or promote products derived from 262292SN/A * this software without specific prior written permission. 272292SN/A * 282292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392689Sktlim@umich.edu * 402689Sktlim@umich.edu * Authors: Kevin Lim 412689Sktlim@umich.edu * Korey Sewell 422292SN/A */ 432292SN/A 448591Sgblack@eecs.umich.edu#include "arch/generic/debugfaults.hh" 453326Sktlim@umich.edu#include "arch/locked_mem.hh" 468229Snate@binkert.org#include "base/str.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 492907Sktlim@umich.edu#include "cpu/o3/lsq.hh" 502292SN/A#include "cpu/o3/lsq_unit.hh" 518232Snate@binkert.org#include "debug/Activity.hh" 528232Snate@binkert.org#include "debug/IEW.hh" 538232Snate@binkert.org#include "debug/LSQUnit.hh" 542722Sktlim@umich.edu#include "mem/packet.hh" 552669Sktlim@umich.edu#include "mem/request.hh" 562292SN/A 572669Sktlim@umich.edutemplate<class Impl> 582678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 592678Sktlim@umich.edu LSQUnit *lsq_ptr) 608581Ssteve.reinhardt@amd.com : Event(Default_Pri, AutoDelete), 618581Ssteve.reinhardt@amd.com inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 622292SN/A{ 632292SN/A} 642292SN/A 652669Sktlim@umich.edutemplate<class Impl> 662292SN/Avoid 672678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 682292SN/A{ 692678Sktlim@umich.edu if (!lsqPtr->isSwitchedOut()) { 702678Sktlim@umich.edu lsqPtr->writeback(inst, pkt); 712678Sktlim@umich.edu } 724319Sktlim@umich.edu 734319Sktlim@umich.edu if (pkt->senderState) 744319Sktlim@umich.edu delete pkt->senderState; 754319Sktlim@umich.edu 764319Sktlim@umich.edu delete pkt->req; 772678Sktlim@umich.edu delete pkt; 782678Sktlim@umich.edu} 792292SN/A 802678Sktlim@umich.edutemplate<class Impl> 812678Sktlim@umich.educonst char * 825336Shines@cs.fsu.eduLSQUnit<Impl>::WritebackEvent::description() const 832678Sktlim@umich.edu{ 844873Sstever@eecs.umich.edu return "Store writeback"; 852678Sktlim@umich.edu} 862292SN/A 872678Sktlim@umich.edutemplate<class Impl> 882678Sktlim@umich.eduvoid 892678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 902678Sktlim@umich.edu{ 912678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 922678Sktlim@umich.edu DynInstPtr inst = state->inst; 937852SMatt.Horsnell@arm.com DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum); 947852SMatt.Horsnell@arm.com DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum); 952344SN/A 962678Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 972678Sktlim@umich.edu 984986Ssaidi@eecs.umich.edu assert(!pkt->wasNacked()); 994986Ssaidi@eecs.umich.edu 1006974Stjones1@inf.ed.ac.uk // If this is a split access, wait until all packets are received. 1016974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && !state->complete()) { 1026974Stjones1@inf.ed.ac.uk delete pkt->req; 1036974Stjones1@inf.ed.ac.uk delete pkt; 1046974Stjones1@inf.ed.ac.uk return; 1056974Stjones1@inf.ed.ac.uk } 1066974Stjones1@inf.ed.ac.uk 1072678Sktlim@umich.edu if (isSwitchedOut() || inst->isSquashed()) { 1082820Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 1092678Sktlim@umich.edu } else { 1102678Sktlim@umich.edu if (!state->noWB) { 1116974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 1126974Stjones1@inf.ed.ac.uk !state->isLoad) { 1136974Stjones1@inf.ed.ac.uk writeback(inst, pkt); 1146974Stjones1@inf.ed.ac.uk } else { 1156974Stjones1@inf.ed.ac.uk writeback(inst, state->mainPkt); 1166974Stjones1@inf.ed.ac.uk } 1172678Sktlim@umich.edu } 1182678Sktlim@umich.edu 1192678Sktlim@umich.edu if (inst->isStore()) { 1202678Sktlim@umich.edu completeStore(state->idx); 1212678Sktlim@umich.edu } 1222344SN/A } 1232307SN/A 1246974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 1256974Stjones1@inf.ed.ac.uk delete state->mainPkt->req; 1266974Stjones1@inf.ed.ac.uk delete state->mainPkt; 1276974Stjones1@inf.ed.ac.uk } 1282678Sktlim@umich.edu delete state; 1294032Sktlim@umich.edu delete pkt->req; 1302678Sktlim@umich.edu delete pkt; 1312292SN/A} 1322292SN/A 1332292SN/Atemplate <class Impl> 1342292SN/ALSQUnit<Impl>::LSQUnit() 1358545Ssaidi@eecs.umich.edu : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 1362678Sktlim@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1378727Snilay@cs.wisc.edu loadBlockedHandled(false), storeInFlight(false), hasPendingPkt(false) 1382292SN/A{ 1392292SN/A} 1402292SN/A 1412292SN/Atemplate<class Impl> 1422292SN/Avoid 1435529Snate@binkert.orgLSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 1445529Snate@binkert.org LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 1455529Snate@binkert.org unsigned id) 1462292SN/A{ 1474329Sktlim@umich.edu cpu = cpu_ptr; 1484329Sktlim@umich.edu iewStage = iew_ptr; 1494329Sktlim@umich.edu 1504329Sktlim@umich.edu DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1512292SN/A 1522307SN/A switchedOut = false; 1532307SN/A 1548545Ssaidi@eecs.umich.edu cacheBlockMask = 0; 1558545Ssaidi@eecs.umich.edu 1562907Sktlim@umich.edu lsq = lsq_ptr; 1572907Sktlim@umich.edu 1582292SN/A lsqID = id; 1592292SN/A 1602329SN/A // Add 1 for the sentinel entry (they are circular queues). 1612329SN/A LQEntries = maxLQEntries + 1; 1622329SN/A SQEntries = maxSQEntries + 1; 1632292SN/A 1642292SN/A loadQueue.resize(LQEntries); 1652292SN/A storeQueue.resize(SQEntries); 1662292SN/A 1678199SAli.Saidi@ARM.com depCheckShift = params->LSQDepCheckShift; 1688199SAli.Saidi@ARM.com checkLoads = params->LSQCheckLoads; 1698199SAli.Saidi@ARM.com 1702292SN/A loadHead = loadTail = 0; 1712292SN/A 1722292SN/A storeHead = storeWBIdx = storeTail = 0; 1732292SN/A 1742292SN/A usedPorts = 0; 1752292SN/A cachePorts = params->cachePorts; 1762292SN/A 1773492Sktlim@umich.edu retryPkt = NULL; 1782329SN/A memDepViolator = NULL; 1792292SN/A 1802292SN/A blockedLoadSeqNum = 0; 1818727Snilay@cs.wisc.edu needsTSO = params->needsTSO; 1822292SN/A} 1832292SN/A 1842292SN/Atemplate<class Impl> 1852292SN/Astd::string 1862292SN/ALSQUnit<Impl>::name() const 1872292SN/A{ 1882292SN/A if (Impl::MaxThreads == 1) { 1892292SN/A return iewStage->name() + ".lsq"; 1902292SN/A } else { 1918247Snate@binkert.org return iewStage->name() + ".lsq.thread" + to_string(lsqID); 1922292SN/A } 1932292SN/A} 1942292SN/A 1952292SN/Atemplate<class Impl> 1962292SN/Avoid 1972727Sktlim@umich.eduLSQUnit<Impl>::regStats() 1982727Sktlim@umich.edu{ 1992727Sktlim@umich.edu lsqForwLoads 2002727Sktlim@umich.edu .name(name() + ".forwLoads") 2012727Sktlim@umich.edu .desc("Number of loads that had data forwarded from stores"); 2022727Sktlim@umich.edu 2032727Sktlim@umich.edu invAddrLoads 2042727Sktlim@umich.edu .name(name() + ".invAddrLoads") 2052727Sktlim@umich.edu .desc("Number of loads ignored due to an invalid address"); 2062727Sktlim@umich.edu 2072727Sktlim@umich.edu lsqSquashedLoads 2082727Sktlim@umich.edu .name(name() + ".squashedLoads") 2092727Sktlim@umich.edu .desc("Number of loads squashed"); 2102727Sktlim@umich.edu 2112727Sktlim@umich.edu lsqIgnoredResponses 2122727Sktlim@umich.edu .name(name() + ".ignoredResponses") 2132727Sktlim@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 2142727Sktlim@umich.edu 2152361SN/A lsqMemOrderViolation 2162361SN/A .name(name() + ".memOrderViolation") 2172361SN/A .desc("Number of memory ordering violations"); 2182361SN/A 2192727Sktlim@umich.edu lsqSquashedStores 2202727Sktlim@umich.edu .name(name() + ".squashedStores") 2212727Sktlim@umich.edu .desc("Number of stores squashed"); 2222727Sktlim@umich.edu 2232727Sktlim@umich.edu invAddrSwpfs 2242727Sktlim@umich.edu .name(name() + ".invAddrSwpfs") 2252727Sktlim@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 2262727Sktlim@umich.edu 2272727Sktlim@umich.edu lsqBlockedLoads 2282727Sktlim@umich.edu .name(name() + ".blockedLoads") 2292727Sktlim@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 2302727Sktlim@umich.edu 2312727Sktlim@umich.edu lsqRescheduledLoads 2322727Sktlim@umich.edu .name(name() + ".rescheduledLoads") 2332727Sktlim@umich.edu .desc("Number of loads that were rescheduled"); 2342727Sktlim@umich.edu 2352727Sktlim@umich.edu lsqCacheBlocked 2362727Sktlim@umich.edu .name(name() + ".cacheBlocked") 2372727Sktlim@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2382727Sktlim@umich.edu} 2392727Sktlim@umich.edu 2402727Sktlim@umich.edutemplate<class Impl> 2412727Sktlim@umich.eduvoid 2428922Swilliam.wang@arm.comLSQUnit<Impl>::setDcachePort(MasterPort *dcache_port) 2434329Sktlim@umich.edu{ 2444329Sktlim@umich.edu dcachePort = dcache_port; 2454329Sktlim@umich.edu} 2464329Sktlim@umich.edu 2474329Sktlim@umich.edutemplate<class Impl> 2484329Sktlim@umich.eduvoid 2492292SN/ALSQUnit<Impl>::clearLQ() 2502292SN/A{ 2512292SN/A loadQueue.clear(); 2522292SN/A} 2532292SN/A 2542292SN/Atemplate<class Impl> 2552292SN/Avoid 2562292SN/ALSQUnit<Impl>::clearSQ() 2572292SN/A{ 2582292SN/A storeQueue.clear(); 2592292SN/A} 2602292SN/A 2612292SN/Atemplate<class Impl> 2622292SN/Avoid 2632307SN/ALSQUnit<Impl>::switchOut() 2642307SN/A{ 2652307SN/A switchedOut = true; 2662367SN/A for (int i = 0; i < loadQueue.size(); ++i) { 2672367SN/A assert(!loadQueue[i]); 2682307SN/A loadQueue[i] = NULL; 2692367SN/A } 2702307SN/A 2712329SN/A assert(storesToWB == 0); 2722307SN/A} 2732307SN/A 2742307SN/Atemplate<class Impl> 2752307SN/Avoid 2762307SN/ALSQUnit<Impl>::takeOverFrom() 2772307SN/A{ 2782307SN/A switchedOut = false; 2792307SN/A loads = stores = storesToWB = 0; 2802307SN/A 2812307SN/A loadHead = loadTail = 0; 2822307SN/A 2832307SN/A storeHead = storeWBIdx = storeTail = 0; 2842307SN/A 2852307SN/A usedPorts = 0; 2862307SN/A 2872329SN/A memDepViolator = NULL; 2882307SN/A 2892307SN/A blockedLoadSeqNum = 0; 2902307SN/A 2912307SN/A stalled = false; 2922307SN/A isLoadBlocked = false; 2932307SN/A loadBlockedHandled = false; 2948545Ssaidi@eecs.umich.edu 2958545Ssaidi@eecs.umich.edu // Just incase the memory system changed out from under us 2968545Ssaidi@eecs.umich.edu cacheBlockMask = 0; 2972307SN/A} 2982307SN/A 2992307SN/Atemplate<class Impl> 3002307SN/Avoid 3012292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 3022292SN/A{ 3032329SN/A unsigned size_plus_sentinel = size + 1; 3042329SN/A assert(size_plus_sentinel >= LQEntries); 3052292SN/A 3062329SN/A if (size_plus_sentinel > LQEntries) { 3072329SN/A while (size_plus_sentinel > loadQueue.size()) { 3082292SN/A DynInstPtr dummy; 3092292SN/A loadQueue.push_back(dummy); 3102292SN/A LQEntries++; 3112292SN/A } 3122292SN/A } else { 3132329SN/A LQEntries = size_plus_sentinel; 3142292SN/A } 3152292SN/A 3162292SN/A} 3172292SN/A 3182292SN/Atemplate<class Impl> 3192292SN/Avoid 3202292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 3212292SN/A{ 3222329SN/A unsigned size_plus_sentinel = size + 1; 3232329SN/A if (size_plus_sentinel > SQEntries) { 3242329SN/A while (size_plus_sentinel > storeQueue.size()) { 3252292SN/A SQEntry dummy; 3262292SN/A storeQueue.push_back(dummy); 3272292SN/A SQEntries++; 3282292SN/A } 3292292SN/A } else { 3302329SN/A SQEntries = size_plus_sentinel; 3312292SN/A } 3322292SN/A} 3332292SN/A 3342292SN/Atemplate <class Impl> 3352292SN/Avoid 3362292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 3372292SN/A{ 3382292SN/A assert(inst->isMemRef()); 3392292SN/A 3402292SN/A assert(inst->isLoad() || inst->isStore()); 3412292SN/A 3422292SN/A if (inst->isLoad()) { 3432292SN/A insertLoad(inst); 3442292SN/A } else { 3452292SN/A insertStore(inst); 3462292SN/A } 3472292SN/A 3482292SN/A inst->setInLSQ(); 3492292SN/A} 3502292SN/A 3512292SN/Atemplate <class Impl> 3522292SN/Avoid 3532292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3542292SN/A{ 3552329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3562329SN/A assert(loads < LQEntries); 3572292SN/A 3587720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 3597720Sgblack@eecs.umich.edu load_inst->pcState(), loadTail, load_inst->seqNum); 3602292SN/A 3612292SN/A load_inst->lqIdx = loadTail; 3622292SN/A 3632292SN/A if (stores == 0) { 3642292SN/A load_inst->sqIdx = -1; 3652292SN/A } else { 3662292SN/A load_inst->sqIdx = storeTail; 3672292SN/A } 3682292SN/A 3692292SN/A loadQueue[loadTail] = load_inst; 3702292SN/A 3712292SN/A incrLdIdx(loadTail); 3722292SN/A 3732292SN/A ++loads; 3742292SN/A} 3752292SN/A 3762292SN/Atemplate <class Impl> 3772292SN/Avoid 3782292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3792292SN/A{ 3802292SN/A // Make sure it is not full before inserting an instruction. 3812292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3822292SN/A assert(stores < SQEntries); 3832292SN/A 3847720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 3857720Sgblack@eecs.umich.edu store_inst->pcState(), storeTail, store_inst->seqNum); 3862292SN/A 3872292SN/A store_inst->sqIdx = storeTail; 3882292SN/A store_inst->lqIdx = loadTail; 3892292SN/A 3902292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3912292SN/A 3922292SN/A incrStIdx(storeTail); 3932292SN/A 3942292SN/A ++stores; 3952292SN/A} 3962292SN/A 3972292SN/Atemplate <class Impl> 3982292SN/Atypename Impl::DynInstPtr 3992292SN/ALSQUnit<Impl>::getMemDepViolator() 4002292SN/A{ 4012292SN/A DynInstPtr temp = memDepViolator; 4022292SN/A 4032292SN/A memDepViolator = NULL; 4042292SN/A 4052292SN/A return temp; 4062292SN/A} 4072292SN/A 4082292SN/Atemplate <class Impl> 4092292SN/Aunsigned 4102292SN/ALSQUnit<Impl>::numFreeEntries() 4112292SN/A{ 4122292SN/A unsigned free_lq_entries = LQEntries - loads; 4132292SN/A unsigned free_sq_entries = SQEntries - stores; 4142292SN/A 4152292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 4162292SN/A // empty/full conditions. Subtract 1 from the free entries. 4172292SN/A if (free_lq_entries < free_sq_entries) { 4182292SN/A return free_lq_entries - 1; 4192292SN/A } else { 4202292SN/A return free_sq_entries - 1; 4212292SN/A } 4222292SN/A} 4232292SN/A 4242292SN/Atemplate <class Impl> 4252292SN/Aint 4262292SN/ALSQUnit<Impl>::numLoadsReady() 4272292SN/A{ 4282292SN/A int load_idx = loadHead; 4292292SN/A int retval = 0; 4302292SN/A 4312292SN/A while (load_idx != loadTail) { 4322292SN/A assert(loadQueue[load_idx]); 4332292SN/A 4342292SN/A if (loadQueue[load_idx]->readyToIssue()) { 4352292SN/A ++retval; 4362292SN/A } 4372292SN/A } 4382292SN/A 4392292SN/A return retval; 4402292SN/A} 4412292SN/A 4422292SN/Atemplate <class Impl> 4438545Ssaidi@eecs.umich.eduvoid 4448545Ssaidi@eecs.umich.eduLSQUnit<Impl>::checkSnoop(PacketPtr pkt) 4458545Ssaidi@eecs.umich.edu{ 4468545Ssaidi@eecs.umich.edu int load_idx = loadHead; 4478545Ssaidi@eecs.umich.edu 4488545Ssaidi@eecs.umich.edu if (!cacheBlockMask) { 4498545Ssaidi@eecs.umich.edu assert(dcachePort); 4508545Ssaidi@eecs.umich.edu Addr bs = dcachePort->peerBlockSize(); 4518545Ssaidi@eecs.umich.edu 4528545Ssaidi@eecs.umich.edu // Make sure we actually got a size 4538545Ssaidi@eecs.umich.edu assert(bs != 0); 4548545Ssaidi@eecs.umich.edu 4558545Ssaidi@eecs.umich.edu cacheBlockMask = ~(bs - 1); 4568545Ssaidi@eecs.umich.edu } 4578545Ssaidi@eecs.umich.edu 4588545Ssaidi@eecs.umich.edu // If this is the only load in the LSQ we don't care 4598545Ssaidi@eecs.umich.edu if (load_idx == loadTail) 4608545Ssaidi@eecs.umich.edu return; 4618545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 4628545Ssaidi@eecs.umich.edu 4638545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr()); 4648545Ssaidi@eecs.umich.edu Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 4658545Ssaidi@eecs.umich.edu while (load_idx != loadTail) { 4668545Ssaidi@eecs.umich.edu DynInstPtr ld_inst = loadQueue[load_idx]; 4678545Ssaidi@eecs.umich.edu 4688545Ssaidi@eecs.umich.edu if (!ld_inst->effAddrValid || ld_inst->uncacheable()) { 4698545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 4708545Ssaidi@eecs.umich.edu continue; 4718545Ssaidi@eecs.umich.edu } 4728545Ssaidi@eecs.umich.edu 4738545Ssaidi@eecs.umich.edu Addr load_addr = ld_inst->physEffAddr & cacheBlockMask; 4748545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n", 4758545Ssaidi@eecs.umich.edu ld_inst->seqNum, load_addr, invalidate_addr); 4768545Ssaidi@eecs.umich.edu 4778545Ssaidi@eecs.umich.edu if (load_addr == invalidate_addr) { 4788545Ssaidi@eecs.umich.edu if (ld_inst->possibleLoadViolation) { 4798545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n", 4808545Ssaidi@eecs.umich.edu ld_inst->physEffAddr, pkt->getAddr(), ld_inst->seqNum); 4818545Ssaidi@eecs.umich.edu 4828545Ssaidi@eecs.umich.edu // Mark the load for re-execution 4838545Ssaidi@eecs.umich.edu ld_inst->fault = new ReExec; 4848545Ssaidi@eecs.umich.edu } else { 4858545Ssaidi@eecs.umich.edu // If a older load checks this and it's true 4868545Ssaidi@eecs.umich.edu // then we might have missed the snoop 4878545Ssaidi@eecs.umich.edu // in which case we need to invalidate to be sure 4888545Ssaidi@eecs.umich.edu ld_inst->hitExternalSnoop = true; 4898545Ssaidi@eecs.umich.edu } 4908545Ssaidi@eecs.umich.edu } 4918545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 4928545Ssaidi@eecs.umich.edu } 4938545Ssaidi@eecs.umich.edu return; 4948545Ssaidi@eecs.umich.edu} 4958545Ssaidi@eecs.umich.edu 4968545Ssaidi@eecs.umich.edutemplate <class Impl> 4972292SN/AFault 4988199SAli.Saidi@ARM.comLSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) 4998199SAli.Saidi@ARM.com{ 5008199SAli.Saidi@ARM.com Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 5018199SAli.Saidi@ARM.com Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 5028199SAli.Saidi@ARM.com 5038199SAli.Saidi@ARM.com /** @todo in theory you only need to check an instruction that has executed 5048199SAli.Saidi@ARM.com * however, there isn't a good way in the pipeline at the moment to check 5058199SAli.Saidi@ARM.com * all instructions that will execute before the store writes back. Thus, 5068199SAli.Saidi@ARM.com * like the implementation that came before it, we're overly conservative. 5078199SAli.Saidi@ARM.com */ 5088199SAli.Saidi@ARM.com while (load_idx != loadTail) { 5098199SAli.Saidi@ARM.com DynInstPtr ld_inst = loadQueue[load_idx]; 5108199SAli.Saidi@ARM.com if (!ld_inst->effAddrValid || ld_inst->uncacheable()) { 5118199SAli.Saidi@ARM.com incrLdIdx(load_idx); 5128199SAli.Saidi@ARM.com continue; 5138199SAli.Saidi@ARM.com } 5148199SAli.Saidi@ARM.com 5158199SAli.Saidi@ARM.com Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 5168199SAli.Saidi@ARM.com Addr ld_eff_addr2 = 5178199SAli.Saidi@ARM.com (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 5188199SAli.Saidi@ARM.com 5198272SAli.Saidi@ARM.com if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 5208545Ssaidi@eecs.umich.edu if (inst->isLoad()) { 5218545Ssaidi@eecs.umich.edu // If this load is to the same block as an external snoop 5228545Ssaidi@eecs.umich.edu // invalidate that we've observed then the load needs to be 5238545Ssaidi@eecs.umich.edu // squashed as it could have newer data 5248545Ssaidi@eecs.umich.edu if (ld_inst->hitExternalSnoop) { 5258545Ssaidi@eecs.umich.edu if (!memDepViolator || 5268545Ssaidi@eecs.umich.edu ld_inst->seqNum < memDepViolator->seqNum) { 5278545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] " 5288592Sgblack@eecs.umich.edu "and [sn:%lli] at address %#x\n", 5298592Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5308545Ssaidi@eecs.umich.edu memDepViolator = ld_inst; 5318199SAli.Saidi@ARM.com 5328545Ssaidi@eecs.umich.edu ++lsqMemOrderViolation; 5338199SAli.Saidi@ARM.com 5348591Sgblack@eecs.umich.edu return new GenericISA::M5PanicFault( 5358591Sgblack@eecs.umich.edu "Detected fault with inst [sn:%lli] and " 5368591Sgblack@eecs.umich.edu "[sn:%lli] at address %#x\n", 5378591Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5388545Ssaidi@eecs.umich.edu } 5398545Ssaidi@eecs.umich.edu } 5408199SAli.Saidi@ARM.com 5418545Ssaidi@eecs.umich.edu // Otherwise, mark the load has a possible load violation 5428545Ssaidi@eecs.umich.edu // and if we see a snoop before it's commited, we need to squash 5438545Ssaidi@eecs.umich.edu ld_inst->possibleLoadViolation = true; 5448545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Found possible load violaiton at addr: %#x" 5458545Ssaidi@eecs.umich.edu " between instructions [sn:%lli] and [sn:%lli]\n", 5468545Ssaidi@eecs.umich.edu inst_eff_addr1, inst->seqNum, ld_inst->seqNum); 5478545Ssaidi@eecs.umich.edu } else { 5488545Ssaidi@eecs.umich.edu // A load/store incorrectly passed this store. 5498545Ssaidi@eecs.umich.edu // Check if we already have a violator, or if it's newer 5508545Ssaidi@eecs.umich.edu // squash and refetch. 5518545Ssaidi@eecs.umich.edu if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 5528545Ssaidi@eecs.umich.edu break; 5538545Ssaidi@eecs.umich.edu 5548592Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and " 5558592Sgblack@eecs.umich.edu "[sn:%lli] at address %#x\n", 5568592Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5578545Ssaidi@eecs.umich.edu memDepViolator = ld_inst; 5588545Ssaidi@eecs.umich.edu 5598545Ssaidi@eecs.umich.edu ++lsqMemOrderViolation; 5608545Ssaidi@eecs.umich.edu 5618591Sgblack@eecs.umich.edu return new GenericISA::M5PanicFault("Detected fault with " 5628591Sgblack@eecs.umich.edu "inst [sn:%lli] and [sn:%lli] at address %#x\n", 5638591Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5648545Ssaidi@eecs.umich.edu } 5658199SAli.Saidi@ARM.com } 5668199SAli.Saidi@ARM.com 5678199SAli.Saidi@ARM.com incrLdIdx(load_idx); 5688199SAli.Saidi@ARM.com } 5698199SAli.Saidi@ARM.com return NoFault; 5708199SAli.Saidi@ARM.com} 5718199SAli.Saidi@ARM.com 5728199SAli.Saidi@ARM.com 5738199SAli.Saidi@ARM.com 5748199SAli.Saidi@ARM.com 5758199SAli.Saidi@ARM.comtemplate <class Impl> 5768199SAli.Saidi@ARM.comFault 5772292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 5782292SN/A{ 5794032Sktlim@umich.edu using namespace TheISA; 5802292SN/A // Execute a specific load. 5812292SN/A Fault load_fault = NoFault; 5822292SN/A 5837720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 5847944SGiacomo.Gabrielli@arm.com inst->pcState(), inst->seqNum); 5852292SN/A 5864032Sktlim@umich.edu assert(!inst->isSquashed()); 5874032Sktlim@umich.edu 5882669Sktlim@umich.edu load_fault = inst->initiateAcc(); 5892292SN/A 5907944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 5917944SGiacomo.Gabrielli@arm.com load_fault == NoFault) 5927944SGiacomo.Gabrielli@arm.com return load_fault; 5937944SGiacomo.Gabrielli@arm.com 5947597Sminkyu.jeong@arm.com // If the instruction faulted or predicated false, then we need to send it 5957597Sminkyu.jeong@arm.com // along to commit without the instruction completing. 5967597Sminkyu.jeong@arm.com if (load_fault != NoFault || inst->readPredicate() == false) { 5972329SN/A // Send this instruction to commit, also make sure iew stage 5982329SN/A // realizes there is activity. 5992367SN/A // Mark it as executed unless it is an uncached load that 6002367SN/A // needs to hit the head of commit. 6017848SAli.Saidi@ARM.com if (inst->readPredicate() == false) 6027848SAli.Saidi@ARM.com inst->forwardOldRegs(); 6037600Sminkyu.jeong@arm.com DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 6047600Sminkyu.jeong@arm.com inst->seqNum, 6057600Sminkyu.jeong@arm.com (load_fault != NoFault ? "fault" : "predication")); 6064032Sktlim@umich.edu if (!(inst->hasRequest() && inst->uncacheable()) || 6073731Sktlim@umich.edu inst->isAtCommit()) { 6082367SN/A inst->setExecuted(); 6092367SN/A } 6102292SN/A iewStage->instToCommit(inst); 6112292SN/A iewStage->activityThisCycle(); 6124032Sktlim@umich.edu } else if (!loadBlocked()) { 6134032Sktlim@umich.edu assert(inst->effAddrValid); 6144032Sktlim@umich.edu int load_idx = inst->lqIdx; 6154032Sktlim@umich.edu incrLdIdx(load_idx); 6164032Sktlim@umich.edu 6178199SAli.Saidi@ARM.com if (checkLoads) 6188199SAli.Saidi@ARM.com return checkViolations(load_idx, inst); 6192292SN/A } 6202292SN/A 6212292SN/A return load_fault; 6222292SN/A} 6232292SN/A 6242292SN/Atemplate <class Impl> 6252292SN/AFault 6262292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 6272292SN/A{ 6282292SN/A using namespace TheISA; 6292292SN/A // Make sure that a store exists. 6302292SN/A assert(stores != 0); 6312292SN/A 6322292SN/A int store_idx = store_inst->sqIdx; 6332292SN/A 6347720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 6357720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 6362292SN/A 6374032Sktlim@umich.edu assert(!store_inst->isSquashed()); 6384032Sktlim@umich.edu 6392292SN/A // Check the recently completed loads to see if any match this store's 6402292SN/A // address. If so, then we have a memory ordering violation. 6412292SN/A int load_idx = store_inst->lqIdx; 6422292SN/A 6432292SN/A Fault store_fault = store_inst->initiateAcc(); 6442292SN/A 6457944SGiacomo.Gabrielli@arm.com if (store_inst->isTranslationDelayed() && 6467944SGiacomo.Gabrielli@arm.com store_fault == NoFault) 6477944SGiacomo.Gabrielli@arm.com return store_fault; 6487944SGiacomo.Gabrielli@arm.com 6497848SAli.Saidi@ARM.com if (store_inst->readPredicate() == false) 6507848SAli.Saidi@ARM.com store_inst->forwardOldRegs(); 6517848SAli.Saidi@ARM.com 6522329SN/A if (storeQueue[store_idx].size == 0) { 6537782Sminkyu.jeong@arm.com DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 6547720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 6552292SN/A 6562292SN/A return store_fault; 6577782Sminkyu.jeong@arm.com } else if (store_inst->readPredicate() == false) { 6587782Sminkyu.jeong@arm.com DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 6597782Sminkyu.jeong@arm.com store_inst->seqNum); 6607782Sminkyu.jeong@arm.com return store_fault; 6612292SN/A } 6622292SN/A 6632292SN/A assert(store_fault == NoFault); 6642292SN/A 6652336SN/A if (store_inst->isStoreConditional()) { 6662336SN/A // Store conditionals need to set themselves as able to 6672336SN/A // writeback if we haven't had a fault by here. 6682329SN/A storeQueue[store_idx].canWB = true; 6692292SN/A 6702329SN/A ++storesToWB; 6712292SN/A } 6722292SN/A 6738199SAli.Saidi@ARM.com return checkViolations(load_idx, store_inst); 6742292SN/A 6752292SN/A} 6762292SN/A 6772292SN/Atemplate <class Impl> 6782292SN/Avoid 6792292SN/ALSQUnit<Impl>::commitLoad() 6802292SN/A{ 6812292SN/A assert(loadQueue[loadHead]); 6822292SN/A 6837720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 6847720Sgblack@eecs.umich.edu loadQueue[loadHead]->pcState()); 6852292SN/A 6862292SN/A loadQueue[loadHead] = NULL; 6872292SN/A 6882292SN/A incrLdIdx(loadHead); 6892292SN/A 6902292SN/A --loads; 6912292SN/A} 6922292SN/A 6932292SN/Atemplate <class Impl> 6942292SN/Avoid 6952292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 6962292SN/A{ 6972292SN/A assert(loads == 0 || loadQueue[loadHead]); 6982292SN/A 6992292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 7002292SN/A commitLoad(); 7012292SN/A } 7022292SN/A} 7032292SN/A 7042292SN/Atemplate <class Impl> 7052292SN/Avoid 7062292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 7072292SN/A{ 7082292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 7092292SN/A 7102292SN/A int store_idx = storeHead; 7112292SN/A 7122292SN/A while (store_idx != storeTail) { 7132292SN/A assert(storeQueue[store_idx].inst); 7142329SN/A // Mark any stores that are now committed and have not yet 7152329SN/A // been marked as able to write back. 7162292SN/A if (!storeQueue[store_idx].canWB) { 7172292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 7182292SN/A break; 7192292SN/A } 7202292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 7217720Sgblack@eecs.umich.edu "%s [sn:%lli]\n", 7227720Sgblack@eecs.umich.edu storeQueue[store_idx].inst->pcState(), 7232292SN/A storeQueue[store_idx].inst->seqNum); 7242292SN/A 7252292SN/A storeQueue[store_idx].canWB = true; 7262292SN/A 7272292SN/A ++storesToWB; 7282292SN/A } 7292292SN/A 7302292SN/A incrStIdx(store_idx); 7312292SN/A } 7322292SN/A} 7332292SN/A 7342292SN/Atemplate <class Impl> 7352292SN/Avoid 7366974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::writebackPendingStore() 7376974Stjones1@inf.ed.ac.uk{ 7386974Stjones1@inf.ed.ac.uk if (hasPendingPkt) { 7396974Stjones1@inf.ed.ac.uk assert(pendingPkt != NULL); 7406974Stjones1@inf.ed.ac.uk 7416974Stjones1@inf.ed.ac.uk // If the cache is blocked, this will store the packet for retry. 7426974Stjones1@inf.ed.ac.uk if (sendStore(pendingPkt)) { 7436974Stjones1@inf.ed.ac.uk storePostSend(pendingPkt); 7446974Stjones1@inf.ed.ac.uk } 7456974Stjones1@inf.ed.ac.uk pendingPkt = NULL; 7466974Stjones1@inf.ed.ac.uk hasPendingPkt = false; 7476974Stjones1@inf.ed.ac.uk } 7486974Stjones1@inf.ed.ac.uk} 7496974Stjones1@inf.ed.ac.uk 7506974Stjones1@inf.ed.ac.uktemplate <class Impl> 7516974Stjones1@inf.ed.ac.ukvoid 7522292SN/ALSQUnit<Impl>::writebackStores() 7532292SN/A{ 7546974Stjones1@inf.ed.ac.uk // First writeback the second packet from any split store that didn't 7556974Stjones1@inf.ed.ac.uk // complete last cycle because there weren't enough cache ports available. 7566974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc) { 7576974Stjones1@inf.ed.ac.uk writebackPendingStore(); 7586974Stjones1@inf.ed.ac.uk } 7596974Stjones1@inf.ed.ac.uk 7602292SN/A while (storesToWB > 0 && 7612292SN/A storeWBIdx != storeTail && 7622292SN/A storeQueue[storeWBIdx].inst && 7632292SN/A storeQueue[storeWBIdx].canWB && 7648727Snilay@cs.wisc.edu ((!needsTSO) || (!storeInFlight)) && 7652292SN/A usedPorts < cachePorts) { 7662292SN/A 7672907Sktlim@umich.edu if (isStoreBlocked || lsq->cacheBlocked()) { 7682678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 7692678Sktlim@umich.edu " is blocked!\n"); 7702678Sktlim@umich.edu break; 7712678Sktlim@umich.edu } 7722678Sktlim@umich.edu 7732329SN/A // Store didn't write any data so no need to write it back to 7742329SN/A // memory. 7752292SN/A if (storeQueue[storeWBIdx].size == 0) { 7762292SN/A completeStore(storeWBIdx); 7772292SN/A 7782292SN/A incrStIdx(storeWBIdx); 7792292SN/A 7802292SN/A continue; 7812292SN/A } 7822678Sktlim@umich.edu 7832292SN/A ++usedPorts; 7842292SN/A 7852292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 7862292SN/A incrStIdx(storeWBIdx); 7872292SN/A 7882292SN/A continue; 7892292SN/A } 7902292SN/A 7912292SN/A assert(storeQueue[storeWBIdx].req); 7922292SN/A assert(!storeQueue[storeWBIdx].committed); 7932292SN/A 7946974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 7956974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqLow); 7966974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqHigh); 7976974Stjones1@inf.ed.ac.uk } 7986974Stjones1@inf.ed.ac.uk 7992669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 8002669Sktlim@umich.edu 8012669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 8028481Sgblack@eecs.umich.edu RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 8038481Sgblack@eecs.umich.edu RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 8048481Sgblack@eecs.umich.edu 8052292SN/A storeQueue[storeWBIdx].committed = true; 8062292SN/A 8072669Sktlim@umich.edu assert(!inst->memData); 8082669Sktlim@umich.edu inst->memData = new uint8_t[64]; 8093772Sgblack@eecs.umich.edu 8104326Sgblack@eecs.umich.edu memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 8112669Sktlim@umich.edu 8124878Sstever@eecs.umich.edu MemCmd command = 8134878Sstever@eecs.umich.edu req->isSwap() ? MemCmd::SwapReq : 8146102Sgblack@eecs.umich.edu (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 8156974Stjones1@inf.ed.ac.uk PacketPtr data_pkt; 8166974Stjones1@inf.ed.ac.uk PacketPtr snd_data_pkt = NULL; 8172292SN/A 8182678Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 8192678Sktlim@umich.edu state->isLoad = false; 8202678Sktlim@umich.edu state->idx = storeWBIdx; 8212678Sktlim@umich.edu state->inst = inst; 8226974Stjones1@inf.ed.ac.uk 8236974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 8246974Stjones1@inf.ed.ac.uk 8256974Stjones1@inf.ed.ac.uk // Build a single data packet if the store isn't split. 8266974Stjones1@inf.ed.ac.uk data_pkt = new Packet(req, command, Packet::Broadcast); 8276974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 8286974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 8296974Stjones1@inf.ed.ac.uk } else { 8306974Stjones1@inf.ed.ac.uk // Create two packets if the store is split in two. 8316974Stjones1@inf.ed.ac.uk data_pkt = new Packet(sreqLow, command, Packet::Broadcast); 8326974Stjones1@inf.ed.ac.uk snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast); 8336974Stjones1@inf.ed.ac.uk 8346974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 8356974Stjones1@inf.ed.ac.uk snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 8366974Stjones1@inf.ed.ac.uk 8376974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 8386974Stjones1@inf.ed.ac.uk snd_data_pkt->senderState = state; 8396974Stjones1@inf.ed.ac.uk 8406974Stjones1@inf.ed.ac.uk state->isSplit = true; 8416974Stjones1@inf.ed.ac.uk state->outstanding = 2; 8426974Stjones1@inf.ed.ac.uk 8436974Stjones1@inf.ed.ac.uk // Can delete the main request now. 8446974Stjones1@inf.ed.ac.uk delete req; 8456974Stjones1@inf.ed.ac.uk req = sreqLow; 8466974Stjones1@inf.ed.ac.uk } 8472678Sktlim@umich.edu 8487720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 8492292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 8507720Sgblack@eecs.umich.edu storeWBIdx, inst->pcState(), 8513797Sgblack@eecs.umich.edu req->getPaddr(), (int)*(inst->memData), 8523221Sktlim@umich.edu inst->seqNum); 8532292SN/A 8542693Sktlim@umich.edu // @todo: Remove this SC hack once the memory system handles it. 8554350Sgblack@eecs.umich.edu if (inst->isStoreConditional()) { 8566974Stjones1@inf.ed.ac.uk assert(!storeQueue[storeWBIdx].isSplit); 8573326Sktlim@umich.edu // Disable recording the result temporarily. Writing to 8583326Sktlim@umich.edu // misc regs normally updates the result, but this is not 8593326Sktlim@umich.edu // the desired behavior when handling store conditionals. 8603326Sktlim@umich.edu inst->recordResult = false; 8613326Sktlim@umich.edu bool success = TheISA::handleLockedWrite(inst.get(), req); 8623326Sktlim@umich.edu inst->recordResult = true; 8633326Sktlim@umich.edu 8643326Sktlim@umich.edu if (!success) { 8653326Sktlim@umich.edu // Instantly complete this store. 8663326Sktlim@umich.edu DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 8673326Sktlim@umich.edu "Instantly completing it.\n", 8683326Sktlim@umich.edu inst->seqNum); 8693326Sktlim@umich.edu WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 8707823Ssteve.reinhardt@amd.com cpu->schedule(wb, curTick() + 1); 8718887Sgeoffrey.blake@arm.com if (cpu->checker) { 8728887Sgeoffrey.blake@arm.com // Make sure to set the LLSC data for verification 8738887Sgeoffrey.blake@arm.com // if checker is loaded 8748887Sgeoffrey.blake@arm.com inst->reqToVerify->setExtraData(0); 8758887Sgeoffrey.blake@arm.com inst->completeAcc(data_pkt); 8768887Sgeoffrey.blake@arm.com } 8773326Sktlim@umich.edu completeStore(storeWBIdx); 8783326Sktlim@umich.edu incrStIdx(storeWBIdx); 8793326Sktlim@umich.edu continue; 8802693Sktlim@umich.edu } 8812693Sktlim@umich.edu } else { 8822693Sktlim@umich.edu // Non-store conditionals do not need a writeback. 8832693Sktlim@umich.edu state->noWB = true; 8842693Sktlim@umich.edu } 8852693Sktlim@umich.edu 8868481Sgblack@eecs.umich.edu bool split = 8878481Sgblack@eecs.umich.edu TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit; 8888481Sgblack@eecs.umich.edu 8898481Sgblack@eecs.umich.edu ThreadContext *thread = cpu->tcBase(lsqID); 8908481Sgblack@eecs.umich.edu 8918481Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 8928481Sgblack@eecs.umich.edu assert(!inst->isStoreConditional()); 8938481Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread, data_pkt); 8948481Sgblack@eecs.umich.edu delete data_pkt; 8958481Sgblack@eecs.umich.edu if (split) { 8968481Sgblack@eecs.umich.edu assert(snd_data_pkt->req->isMmappedIpr()); 8978481Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread, snd_data_pkt); 8988481Sgblack@eecs.umich.edu delete snd_data_pkt; 8998481Sgblack@eecs.umich.edu delete sreqLow; 9008481Sgblack@eecs.umich.edu delete sreqHigh; 9018481Sgblack@eecs.umich.edu } 9028481Sgblack@eecs.umich.edu delete state; 9038481Sgblack@eecs.umich.edu delete req; 9048481Sgblack@eecs.umich.edu completeStore(storeWBIdx); 9058481Sgblack@eecs.umich.edu incrStIdx(storeWBIdx); 9068481Sgblack@eecs.umich.edu } else if (!sendStore(data_pkt)) { 9074032Sktlim@umich.edu DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 9083221Sktlim@umich.edu "retry later\n", 9093221Sktlim@umich.edu inst->seqNum); 9106974Stjones1@inf.ed.ac.uk 9116974Stjones1@inf.ed.ac.uk // Need to store the second packet, if split. 9128481Sgblack@eecs.umich.edu if (split) { 9136974Stjones1@inf.ed.ac.uk state->pktToSend = true; 9146974Stjones1@inf.ed.ac.uk state->pendingPacket = snd_data_pkt; 9156974Stjones1@inf.ed.ac.uk } 9162669Sktlim@umich.edu } else { 9176974Stjones1@inf.ed.ac.uk 9186974Stjones1@inf.ed.ac.uk // If split, try to send the second packet too 9198481Sgblack@eecs.umich.edu if (split) { 9206974Stjones1@inf.ed.ac.uk assert(snd_data_pkt); 9216974Stjones1@inf.ed.ac.uk 9226974Stjones1@inf.ed.ac.uk // Ensure there are enough ports to use. 9236974Stjones1@inf.ed.ac.uk if (usedPorts < cachePorts) { 9246974Stjones1@inf.ed.ac.uk ++usedPorts; 9256974Stjones1@inf.ed.ac.uk if (sendStore(snd_data_pkt)) { 9266974Stjones1@inf.ed.ac.uk storePostSend(snd_data_pkt); 9276974Stjones1@inf.ed.ac.uk } else { 9286974Stjones1@inf.ed.ac.uk DPRINTF(IEW, "D-Cache became blocked when writing" 9296974Stjones1@inf.ed.ac.uk " [sn:%lli] second packet, will retry later\n", 9306974Stjones1@inf.ed.ac.uk inst->seqNum); 9316974Stjones1@inf.ed.ac.uk } 9326974Stjones1@inf.ed.ac.uk } else { 9336974Stjones1@inf.ed.ac.uk 9346974Stjones1@inf.ed.ac.uk // Store the packet for when there's free ports. 9356974Stjones1@inf.ed.ac.uk assert(pendingPkt == NULL); 9366974Stjones1@inf.ed.ac.uk pendingPkt = snd_data_pkt; 9376974Stjones1@inf.ed.ac.uk hasPendingPkt = true; 9386974Stjones1@inf.ed.ac.uk } 9396974Stjones1@inf.ed.ac.uk } else { 9406974Stjones1@inf.ed.ac.uk 9416974Stjones1@inf.ed.ac.uk // Not a split store. 9426974Stjones1@inf.ed.ac.uk storePostSend(data_pkt); 9436974Stjones1@inf.ed.ac.uk } 9442292SN/A } 9452292SN/A } 9462292SN/A 9472292SN/A // Not sure this should set it to 0. 9482292SN/A usedPorts = 0; 9492292SN/A 9502292SN/A assert(stores >= 0 && storesToWB >= 0); 9512292SN/A} 9522292SN/A 9532292SN/A/*template <class Impl> 9542292SN/Avoid 9552292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 9562292SN/A{ 9572292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 9582292SN/A mshrSeqNums.end(), 9592292SN/A seqNum); 9602292SN/A 9612292SN/A if (mshr_it != mshrSeqNums.end()) { 9622292SN/A mshrSeqNums.erase(mshr_it); 9632292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 9642292SN/A } 9652292SN/A}*/ 9662292SN/A 9672292SN/Atemplate <class Impl> 9682292SN/Avoid 9692292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 9702292SN/A{ 9712292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 9722329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 9732292SN/A 9742292SN/A int load_idx = loadTail; 9752292SN/A decrLdIdx(load_idx); 9762292SN/A 9772292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 9787720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 9792292SN/A "[sn:%lli]\n", 9807720Sgblack@eecs.umich.edu loadQueue[load_idx]->pcState(), 9812292SN/A loadQueue[load_idx]->seqNum); 9822292SN/A 9832292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 9842292SN/A stalled = false; 9852292SN/A stallingStoreIsn = 0; 9862292SN/A stallingLoadIdx = 0; 9872292SN/A } 9882292SN/A 9892329SN/A // Clear the smart pointer to make sure it is decremented. 9902731Sktlim@umich.edu loadQueue[load_idx]->setSquashed(); 9912292SN/A loadQueue[load_idx] = NULL; 9922292SN/A --loads; 9932292SN/A 9942292SN/A // Inefficient! 9952292SN/A loadTail = load_idx; 9962292SN/A 9972292SN/A decrLdIdx(load_idx); 9982727Sktlim@umich.edu ++lsqSquashedLoads; 9992292SN/A } 10002292SN/A 10012292SN/A if (isLoadBlocked) { 10022292SN/A if (squashed_num < blockedLoadSeqNum) { 10032292SN/A isLoadBlocked = false; 10042292SN/A loadBlockedHandled = false; 10052292SN/A blockedLoadSeqNum = 0; 10062292SN/A } 10072292SN/A } 10082292SN/A 10094032Sktlim@umich.edu if (memDepViolator && squashed_num < memDepViolator->seqNum) { 10104032Sktlim@umich.edu memDepViolator = NULL; 10114032Sktlim@umich.edu } 10124032Sktlim@umich.edu 10132292SN/A int store_idx = storeTail; 10142292SN/A decrStIdx(store_idx); 10152292SN/A 10162292SN/A while (stores != 0 && 10172292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 10182329SN/A // Instructions marked as can WB are already committed. 10192292SN/A if (storeQueue[store_idx].canWB) { 10202292SN/A break; 10212292SN/A } 10222292SN/A 10237720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 10242292SN/A "idx:%i [sn:%lli]\n", 10257720Sgblack@eecs.umich.edu storeQueue[store_idx].inst->pcState(), 10262292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 10272292SN/A 10282329SN/A // I don't think this can happen. It should have been cleared 10292329SN/A // by the stalling load. 10302292SN/A if (isStalled() && 10312292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 10322292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 10332292SN/A stalled = false; 10342292SN/A stallingStoreIsn = 0; 10352292SN/A } 10362292SN/A 10372329SN/A // Clear the smart pointer to make sure it is decremented. 10382731Sktlim@umich.edu storeQueue[store_idx].inst->setSquashed(); 10392292SN/A storeQueue[store_idx].inst = NULL; 10402292SN/A storeQueue[store_idx].canWB = 0; 10412292SN/A 10424032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 10434032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the proper 10444032Sktlim@umich.edu // place to really handle request deletes. 10454032Sktlim@umich.edu delete storeQueue[store_idx].req; 10466974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 10476974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqLow; 10486974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqHigh; 10496974Stjones1@inf.ed.ac.uk 10506974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqLow = NULL; 10516974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqHigh = NULL; 10526974Stjones1@inf.ed.ac.uk } 10534032Sktlim@umich.edu 10542292SN/A storeQueue[store_idx].req = NULL; 10552292SN/A --stores; 10562292SN/A 10572292SN/A // Inefficient! 10582292SN/A storeTail = store_idx; 10592292SN/A 10602292SN/A decrStIdx(store_idx); 10612727Sktlim@umich.edu ++lsqSquashedStores; 10622292SN/A } 10632292SN/A} 10642292SN/A 10652292SN/Atemplate <class Impl> 10662292SN/Avoid 10673349Sbinkertn@umich.eduLSQUnit<Impl>::storePostSend(PacketPtr pkt) 10682693Sktlim@umich.edu{ 10692693Sktlim@umich.edu if (isStalled() && 10702693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 10712693Sktlim@umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 10722693Sktlim@umich.edu "load idx:%i\n", 10732693Sktlim@umich.edu stallingStoreIsn, stallingLoadIdx); 10742693Sktlim@umich.edu stalled = false; 10752693Sktlim@umich.edu stallingStoreIsn = 0; 10762693Sktlim@umich.edu iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 10772693Sktlim@umich.edu } 10782693Sktlim@umich.edu 10792693Sktlim@umich.edu if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 10802693Sktlim@umich.edu // The store is basically completed at this time. This 10812693Sktlim@umich.edu // only works so long as the checker doesn't try to 10822693Sktlim@umich.edu // verify the value in memory for stores. 10832693Sktlim@umich.edu storeQueue[storeWBIdx].inst->setCompleted(); 10848887Sgeoffrey.blake@arm.com 10852693Sktlim@umich.edu if (cpu->checker) { 10862732Sktlim@umich.edu cpu->checker->verify(storeQueue[storeWBIdx].inst); 10872693Sktlim@umich.edu } 10882693Sktlim@umich.edu } 10892693Sktlim@umich.edu 10908727Snilay@cs.wisc.edu if (needsTSO) { 10918727Snilay@cs.wisc.edu storeInFlight = true; 10928727Snilay@cs.wisc.edu } 10938727Snilay@cs.wisc.edu 10942693Sktlim@umich.edu incrStIdx(storeWBIdx); 10952693Sktlim@umich.edu} 10962693Sktlim@umich.edu 10972693Sktlim@umich.edutemplate <class Impl> 10982693Sktlim@umich.eduvoid 10992678Sktlim@umich.eduLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 11002678Sktlim@umich.edu{ 11012678Sktlim@umich.edu iewStage->wakeCPU(); 11022678Sktlim@umich.edu 11032678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 11042678Sktlim@umich.edu if (inst->isSquashed()) { 11052927Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 11062678Sktlim@umich.edu assert(!inst->isStore()); 11072727Sktlim@umich.edu ++lsqIgnoredResponses; 11082678Sktlim@umich.edu return; 11092678Sktlim@umich.edu } 11102678Sktlim@umich.edu 11112678Sktlim@umich.edu if (!inst->isExecuted()) { 11122678Sktlim@umich.edu inst->setExecuted(); 11132678Sktlim@umich.edu 11142678Sktlim@umich.edu // Complete access to copy data to proper place. 11152678Sktlim@umich.edu inst->completeAcc(pkt); 11162678Sktlim@umich.edu } 11172678Sktlim@umich.edu 11182678Sktlim@umich.edu // Need to insert instruction into queue to commit 11192678Sktlim@umich.edu iewStage->instToCommit(inst); 11202678Sktlim@umich.edu 11212678Sktlim@umich.edu iewStage->activityThisCycle(); 11227598Sminkyu.jeong@arm.com 11237598Sminkyu.jeong@arm.com // see if this load changed the PC 11247598Sminkyu.jeong@arm.com iewStage->checkMisprediction(inst); 11252678Sktlim@umich.edu} 11262678Sktlim@umich.edu 11272678Sktlim@umich.edutemplate <class Impl> 11282678Sktlim@umich.eduvoid 11292292SN/ALSQUnit<Impl>::completeStore(int store_idx) 11302292SN/A{ 11312292SN/A assert(storeQueue[store_idx].inst); 11322292SN/A storeQueue[store_idx].completed = true; 11332292SN/A --storesToWB; 11342292SN/A // A bit conservative because a store completion may not free up entries, 11352292SN/A // but hopefully avoids two store completions in one cycle from making 11362292SN/A // the CPU tick twice. 11373126Sktlim@umich.edu cpu->wakeCPU(); 11382292SN/A cpu->activityThisCycle(); 11392292SN/A 11402292SN/A if (store_idx == storeHead) { 11412292SN/A do { 11422292SN/A incrStIdx(storeHead); 11432292SN/A 11442292SN/A --stores; 11452292SN/A } while (storeQueue[storeHead].completed && 11462292SN/A storeHead != storeTail); 11472292SN/A 11482292SN/A iewStage->updateLSQNextCycle = true; 11492292SN/A } 11502292SN/A 11512329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 11522329SN/A "idx:%i\n", 11532329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 11542292SN/A 11552292SN/A if (isStalled() && 11562292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 11572292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 11582292SN/A "load idx:%i\n", 11592292SN/A stallingStoreIsn, stallingLoadIdx); 11602292SN/A stalled = false; 11612292SN/A stallingStoreIsn = 0; 11622292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 11632292SN/A } 11642316SN/A 11652316SN/A storeQueue[store_idx].inst->setCompleted(); 11662329SN/A 11678727Snilay@cs.wisc.edu if (needsTSO) { 11688727Snilay@cs.wisc.edu storeInFlight = false; 11698727Snilay@cs.wisc.edu } 11708727Snilay@cs.wisc.edu 11712329SN/A // Tell the checker we've completed this instruction. Some stores 11722329SN/A // may get reported twice to the checker, but the checker can 11732329SN/A // handle that case. 11742316SN/A if (cpu->checker) { 11752732Sktlim@umich.edu cpu->checker->verify(storeQueue[store_idx].inst); 11762316SN/A } 11772292SN/A} 11782292SN/A 11792292SN/Atemplate <class Impl> 11806974Stjones1@inf.ed.ac.ukbool 11816974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::sendStore(PacketPtr data_pkt) 11826974Stjones1@inf.ed.ac.uk{ 11836974Stjones1@inf.ed.ac.uk if (!dcachePort->sendTiming(data_pkt)) { 11846974Stjones1@inf.ed.ac.uk // Need to handle becoming blocked on a store. 11856974Stjones1@inf.ed.ac.uk isStoreBlocked = true; 11866974Stjones1@inf.ed.ac.uk ++lsqCacheBlocked; 11876974Stjones1@inf.ed.ac.uk assert(retryPkt == NULL); 11886974Stjones1@inf.ed.ac.uk retryPkt = data_pkt; 11896974Stjones1@inf.ed.ac.uk lsq->setRetryTid(lsqID); 11906974Stjones1@inf.ed.ac.uk return false; 11916974Stjones1@inf.ed.ac.uk } 11926974Stjones1@inf.ed.ac.uk return true; 11936974Stjones1@inf.ed.ac.uk} 11946974Stjones1@inf.ed.ac.uk 11956974Stjones1@inf.ed.ac.uktemplate <class Impl> 11962693Sktlim@umich.eduvoid 11972693Sktlim@umich.eduLSQUnit<Impl>::recvRetry() 11982693Sktlim@umich.edu{ 11992698Sktlim@umich.edu if (isStoreBlocked) { 12004985Sktlim@umich.edu DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 12012698Sktlim@umich.edu assert(retryPkt != NULL); 12022693Sktlim@umich.edu 12038587Snilay@cs.wisc.edu LSQSenderState *state = 12048587Snilay@cs.wisc.edu dynamic_cast<LSQSenderState *>(retryPkt->senderState); 12058587Snilay@cs.wisc.edu 12062698Sktlim@umich.edu if (dcachePort->sendTiming(retryPkt)) { 12076974Stjones1@inf.ed.ac.uk // Don't finish the store unless this is the last packet. 12088133SAli.Saidi@ARM.com if (!TheISA::HasUnalignedMemAcc || !state->pktToSend || 12098133SAli.Saidi@ARM.com state->pendingPacket == retryPkt) { 12108133SAli.Saidi@ARM.com state->pktToSend = false; 12116974Stjones1@inf.ed.ac.uk storePostSend(retryPkt); 12126974Stjones1@inf.ed.ac.uk } 12132699Sktlim@umich.edu retryPkt = NULL; 12142693Sktlim@umich.edu isStoreBlocked = false; 12156221Snate@binkert.org lsq->setRetryTid(InvalidThreadID); 12166974Stjones1@inf.ed.ac.uk 12176974Stjones1@inf.ed.ac.uk // Send any outstanding packet. 12186974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 12196974Stjones1@inf.ed.ac.uk assert(state->pendingPacket); 12206974Stjones1@inf.ed.ac.uk if (sendStore(state->pendingPacket)) { 12216974Stjones1@inf.ed.ac.uk storePostSend(state->pendingPacket); 12226974Stjones1@inf.ed.ac.uk } 12236974Stjones1@inf.ed.ac.uk } 12242693Sktlim@umich.edu } else { 12252693Sktlim@umich.edu // Still blocked! 12262727Sktlim@umich.edu ++lsqCacheBlocked; 12272907Sktlim@umich.edu lsq->setRetryTid(lsqID); 12282693Sktlim@umich.edu } 12292693Sktlim@umich.edu } else if (isLoadBlocked) { 12302693Sktlim@umich.edu DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 12312693Sktlim@umich.edu "no need to resend packet.\n"); 12322693Sktlim@umich.edu } else { 12332693Sktlim@umich.edu DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 12342693Sktlim@umich.edu } 12352693Sktlim@umich.edu} 12362693Sktlim@umich.edu 12372693Sktlim@umich.edutemplate <class Impl> 12382292SN/Ainline void 12392292SN/ALSQUnit<Impl>::incrStIdx(int &store_idx) 12402292SN/A{ 12412292SN/A if (++store_idx >= SQEntries) 12422292SN/A store_idx = 0; 12432292SN/A} 12442292SN/A 12452292SN/Atemplate <class Impl> 12462292SN/Ainline void 12472292SN/ALSQUnit<Impl>::decrStIdx(int &store_idx) 12482292SN/A{ 12492292SN/A if (--store_idx < 0) 12502292SN/A store_idx += SQEntries; 12512292SN/A} 12522292SN/A 12532292SN/Atemplate <class Impl> 12542292SN/Ainline void 12552292SN/ALSQUnit<Impl>::incrLdIdx(int &load_idx) 12562292SN/A{ 12572292SN/A if (++load_idx >= LQEntries) 12582292SN/A load_idx = 0; 12592292SN/A} 12602292SN/A 12612292SN/Atemplate <class Impl> 12622292SN/Ainline void 12632292SN/ALSQUnit<Impl>::decrLdIdx(int &load_idx) 12642292SN/A{ 12652292SN/A if (--load_idx < 0) 12662292SN/A load_idx += LQEntries; 12672292SN/A} 12682329SN/A 12692329SN/Atemplate <class Impl> 12702329SN/Avoid 12712329SN/ALSQUnit<Impl>::dumpInsts() 12722329SN/A{ 12732329SN/A cprintf("Load store queue: Dumping instructions.\n"); 12742329SN/A cprintf("Load queue size: %i\n", loads); 12752329SN/A cprintf("Load queue: "); 12762329SN/A 12772329SN/A int load_idx = loadHead; 12782329SN/A 12792329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 12807720Sgblack@eecs.umich.edu cprintf("%s ", loadQueue[load_idx]->pcState()); 12812329SN/A 12822329SN/A incrLdIdx(load_idx); 12832329SN/A } 12842329SN/A 12852329SN/A cprintf("Store queue size: %i\n", stores); 12862329SN/A cprintf("Store queue: "); 12872329SN/A 12882329SN/A int store_idx = storeHead; 12892329SN/A 12902329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 12917720Sgblack@eecs.umich.edu cprintf("%s ", storeQueue[store_idx].inst->pcState()); 12922329SN/A 12932329SN/A incrStIdx(store_idx); 12942329SN/A } 12952329SN/A 12962329SN/A cprintf("\n"); 12972329SN/A} 1298