lsq_unit_impl.hh revision 8591
12292SN/A/* 27597Sminkyu.jeong@arm.com * Copyright (c) 2010 ARM Limited 37597Sminkyu.jeong@arm.com * All rights reserved 47597Sminkyu.jeong@arm.com * 57597Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67597Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77597Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87597Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97597Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107597Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117597Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127597Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137597Sminkyu.jeong@arm.com * 142292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 152292SN/A * All rights reserved. 162292SN/A * 172292SN/A * Redistribution and use in source and binary forms, with or without 182292SN/A * modification, are permitted provided that the following conditions are 192292SN/A * met: redistributions of source code must retain the above copyright 202292SN/A * notice, this list of conditions and the following disclaimer; 212292SN/A * redistributions in binary form must reproduce the above copyright 222292SN/A * notice, this list of conditions and the following disclaimer in the 232292SN/A * documentation and/or other materials provided with the distribution; 242292SN/A * neither the name of the copyright holders nor the names of its 252292SN/A * contributors may be used to endorse or promote products derived from 262292SN/A * this software without specific prior written permission. 272292SN/A * 282292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392689Sktlim@umich.edu * 402689Sktlim@umich.edu * Authors: Kevin Lim 412689Sktlim@umich.edu * Korey Sewell 422292SN/A */ 432292SN/A 448591Sgblack@eecs.umich.edu#include "arch/generic/debugfaults.hh" 453326Sktlim@umich.edu#include "arch/locked_mem.hh" 468229Snate@binkert.org#include "base/str.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 482733Sktlim@umich.edu#include "config/use_checker.hh" 492907Sktlim@umich.edu#include "cpu/o3/lsq.hh" 502292SN/A#include "cpu/o3/lsq_unit.hh" 518232Snate@binkert.org#include "debug/Activity.hh" 528232Snate@binkert.org#include "debug/IEW.hh" 538232Snate@binkert.org#include "debug/LSQUnit.hh" 542722Sktlim@umich.edu#include "mem/packet.hh" 552669Sktlim@umich.edu#include "mem/request.hh" 562292SN/A 572790Sktlim@umich.edu#if USE_CHECKER 582790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 592790Sktlim@umich.edu#endif 602790Sktlim@umich.edu 612669Sktlim@umich.edutemplate<class Impl> 622678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 632678Sktlim@umich.edu LSQUnit *lsq_ptr) 648581Ssteve.reinhardt@amd.com : Event(Default_Pri, AutoDelete), 658581Ssteve.reinhardt@amd.com inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 662292SN/A{ 672292SN/A} 682292SN/A 692669Sktlim@umich.edutemplate<class Impl> 702292SN/Avoid 712678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 722292SN/A{ 732678Sktlim@umich.edu if (!lsqPtr->isSwitchedOut()) { 742678Sktlim@umich.edu lsqPtr->writeback(inst, pkt); 752678Sktlim@umich.edu } 764319Sktlim@umich.edu 774319Sktlim@umich.edu if (pkt->senderState) 784319Sktlim@umich.edu delete pkt->senderState; 794319Sktlim@umich.edu 804319Sktlim@umich.edu delete pkt->req; 812678Sktlim@umich.edu delete pkt; 822678Sktlim@umich.edu} 832292SN/A 842678Sktlim@umich.edutemplate<class Impl> 852678Sktlim@umich.educonst char * 865336Shines@cs.fsu.eduLSQUnit<Impl>::WritebackEvent::description() const 872678Sktlim@umich.edu{ 884873Sstever@eecs.umich.edu return "Store writeback"; 892678Sktlim@umich.edu} 902292SN/A 912678Sktlim@umich.edutemplate<class Impl> 922678Sktlim@umich.eduvoid 932678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 942678Sktlim@umich.edu{ 952678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 962678Sktlim@umich.edu DynInstPtr inst = state->inst; 977852SMatt.Horsnell@arm.com DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum); 987852SMatt.Horsnell@arm.com DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum); 992344SN/A 1002678Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 1012678Sktlim@umich.edu 1024986Ssaidi@eecs.umich.edu assert(!pkt->wasNacked()); 1034986Ssaidi@eecs.umich.edu 1046974Stjones1@inf.ed.ac.uk // If this is a split access, wait until all packets are received. 1056974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && !state->complete()) { 1066974Stjones1@inf.ed.ac.uk delete pkt->req; 1076974Stjones1@inf.ed.ac.uk delete pkt; 1086974Stjones1@inf.ed.ac.uk return; 1096974Stjones1@inf.ed.ac.uk } 1106974Stjones1@inf.ed.ac.uk 1112678Sktlim@umich.edu if (isSwitchedOut() || inst->isSquashed()) { 1122820Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 1132678Sktlim@umich.edu } else { 1142678Sktlim@umich.edu if (!state->noWB) { 1156974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 1166974Stjones1@inf.ed.ac.uk !state->isLoad) { 1176974Stjones1@inf.ed.ac.uk writeback(inst, pkt); 1186974Stjones1@inf.ed.ac.uk } else { 1196974Stjones1@inf.ed.ac.uk writeback(inst, state->mainPkt); 1206974Stjones1@inf.ed.ac.uk } 1212678Sktlim@umich.edu } 1222678Sktlim@umich.edu 1232678Sktlim@umich.edu if (inst->isStore()) { 1242678Sktlim@umich.edu completeStore(state->idx); 1252678Sktlim@umich.edu } 1262344SN/A } 1272307SN/A 1286974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 1296974Stjones1@inf.ed.ac.uk delete state->mainPkt->req; 1306974Stjones1@inf.ed.ac.uk delete state->mainPkt; 1316974Stjones1@inf.ed.ac.uk } 1322678Sktlim@umich.edu delete state; 1334032Sktlim@umich.edu delete pkt->req; 1342678Sktlim@umich.edu delete pkt; 1352292SN/A} 1362292SN/A 1372292SN/Atemplate <class Impl> 1382292SN/ALSQUnit<Impl>::LSQUnit() 1398545Ssaidi@eecs.umich.edu : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 1402678Sktlim@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1416974Stjones1@inf.ed.ac.uk loadBlockedHandled(false), hasPendingPkt(false) 1422292SN/A{ 1432292SN/A} 1442292SN/A 1452292SN/Atemplate<class Impl> 1462292SN/Avoid 1475529Snate@binkert.orgLSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 1485529Snate@binkert.org LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 1495529Snate@binkert.org unsigned id) 1502292SN/A{ 1514329Sktlim@umich.edu cpu = cpu_ptr; 1524329Sktlim@umich.edu iewStage = iew_ptr; 1534329Sktlim@umich.edu 1544329Sktlim@umich.edu DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1552292SN/A 1562307SN/A switchedOut = false; 1572307SN/A 1588545Ssaidi@eecs.umich.edu cacheBlockMask = 0; 1598545Ssaidi@eecs.umich.edu 1602907Sktlim@umich.edu lsq = lsq_ptr; 1612907Sktlim@umich.edu 1622292SN/A lsqID = id; 1632292SN/A 1642329SN/A // Add 1 for the sentinel entry (they are circular queues). 1652329SN/A LQEntries = maxLQEntries + 1; 1662329SN/A SQEntries = maxSQEntries + 1; 1672292SN/A 1682292SN/A loadQueue.resize(LQEntries); 1692292SN/A storeQueue.resize(SQEntries); 1702292SN/A 1718199SAli.Saidi@ARM.com depCheckShift = params->LSQDepCheckShift; 1728199SAli.Saidi@ARM.com checkLoads = params->LSQCheckLoads; 1738199SAli.Saidi@ARM.com 1742292SN/A loadHead = loadTail = 0; 1752292SN/A 1762292SN/A storeHead = storeWBIdx = storeTail = 0; 1772292SN/A 1782292SN/A usedPorts = 0; 1792292SN/A cachePorts = params->cachePorts; 1802292SN/A 1813492Sktlim@umich.edu retryPkt = NULL; 1822329SN/A memDepViolator = NULL; 1832292SN/A 1842292SN/A blockedLoadSeqNum = 0; 1852292SN/A} 1862292SN/A 1872292SN/Atemplate<class Impl> 1882292SN/Astd::string 1892292SN/ALSQUnit<Impl>::name() const 1902292SN/A{ 1912292SN/A if (Impl::MaxThreads == 1) { 1922292SN/A return iewStage->name() + ".lsq"; 1932292SN/A } else { 1948247Snate@binkert.org return iewStage->name() + ".lsq.thread" + to_string(lsqID); 1952292SN/A } 1962292SN/A} 1972292SN/A 1982292SN/Atemplate<class Impl> 1992292SN/Avoid 2002727Sktlim@umich.eduLSQUnit<Impl>::regStats() 2012727Sktlim@umich.edu{ 2022727Sktlim@umich.edu lsqForwLoads 2032727Sktlim@umich.edu .name(name() + ".forwLoads") 2042727Sktlim@umich.edu .desc("Number of loads that had data forwarded from stores"); 2052727Sktlim@umich.edu 2062727Sktlim@umich.edu invAddrLoads 2072727Sktlim@umich.edu .name(name() + ".invAddrLoads") 2082727Sktlim@umich.edu .desc("Number of loads ignored due to an invalid address"); 2092727Sktlim@umich.edu 2102727Sktlim@umich.edu lsqSquashedLoads 2112727Sktlim@umich.edu .name(name() + ".squashedLoads") 2122727Sktlim@umich.edu .desc("Number of loads squashed"); 2132727Sktlim@umich.edu 2142727Sktlim@umich.edu lsqIgnoredResponses 2152727Sktlim@umich.edu .name(name() + ".ignoredResponses") 2162727Sktlim@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 2172727Sktlim@umich.edu 2182361SN/A lsqMemOrderViolation 2192361SN/A .name(name() + ".memOrderViolation") 2202361SN/A .desc("Number of memory ordering violations"); 2212361SN/A 2222727Sktlim@umich.edu lsqSquashedStores 2232727Sktlim@umich.edu .name(name() + ".squashedStores") 2242727Sktlim@umich.edu .desc("Number of stores squashed"); 2252727Sktlim@umich.edu 2262727Sktlim@umich.edu invAddrSwpfs 2272727Sktlim@umich.edu .name(name() + ".invAddrSwpfs") 2282727Sktlim@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 2292727Sktlim@umich.edu 2302727Sktlim@umich.edu lsqBlockedLoads 2312727Sktlim@umich.edu .name(name() + ".blockedLoads") 2322727Sktlim@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 2332727Sktlim@umich.edu 2342727Sktlim@umich.edu lsqRescheduledLoads 2352727Sktlim@umich.edu .name(name() + ".rescheduledLoads") 2362727Sktlim@umich.edu .desc("Number of loads that were rescheduled"); 2372727Sktlim@umich.edu 2382727Sktlim@umich.edu lsqCacheBlocked 2392727Sktlim@umich.edu .name(name() + ".cacheBlocked") 2402727Sktlim@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2412727Sktlim@umich.edu} 2422727Sktlim@umich.edu 2432727Sktlim@umich.edutemplate<class Impl> 2442727Sktlim@umich.eduvoid 2454329Sktlim@umich.eduLSQUnit<Impl>::setDcachePort(Port *dcache_port) 2464329Sktlim@umich.edu{ 2474329Sktlim@umich.edu dcachePort = dcache_port; 2484329Sktlim@umich.edu 2494329Sktlim@umich.edu#if USE_CHECKER 2504329Sktlim@umich.edu if (cpu->checker) { 2514329Sktlim@umich.edu cpu->checker->setDcachePort(dcachePort); 2524329Sktlim@umich.edu } 2534329Sktlim@umich.edu#endif 2544329Sktlim@umich.edu} 2554329Sktlim@umich.edu 2564329Sktlim@umich.edutemplate<class Impl> 2574329Sktlim@umich.eduvoid 2582292SN/ALSQUnit<Impl>::clearLQ() 2592292SN/A{ 2602292SN/A loadQueue.clear(); 2612292SN/A} 2622292SN/A 2632292SN/Atemplate<class Impl> 2642292SN/Avoid 2652292SN/ALSQUnit<Impl>::clearSQ() 2662292SN/A{ 2672292SN/A storeQueue.clear(); 2682292SN/A} 2692292SN/A 2702292SN/Atemplate<class Impl> 2712292SN/Avoid 2722307SN/ALSQUnit<Impl>::switchOut() 2732307SN/A{ 2742307SN/A switchedOut = true; 2752367SN/A for (int i = 0; i < loadQueue.size(); ++i) { 2762367SN/A assert(!loadQueue[i]); 2772307SN/A loadQueue[i] = NULL; 2782367SN/A } 2792307SN/A 2802329SN/A assert(storesToWB == 0); 2812307SN/A} 2822307SN/A 2832307SN/Atemplate<class Impl> 2842307SN/Avoid 2852307SN/ALSQUnit<Impl>::takeOverFrom() 2862307SN/A{ 2872307SN/A switchedOut = false; 2882307SN/A loads = stores = storesToWB = 0; 2892307SN/A 2902307SN/A loadHead = loadTail = 0; 2912307SN/A 2922307SN/A storeHead = storeWBIdx = storeTail = 0; 2932307SN/A 2942307SN/A usedPorts = 0; 2952307SN/A 2962329SN/A memDepViolator = NULL; 2972307SN/A 2982307SN/A blockedLoadSeqNum = 0; 2992307SN/A 3002307SN/A stalled = false; 3012307SN/A isLoadBlocked = false; 3022307SN/A loadBlockedHandled = false; 3038545Ssaidi@eecs.umich.edu 3048545Ssaidi@eecs.umich.edu // Just incase the memory system changed out from under us 3058545Ssaidi@eecs.umich.edu cacheBlockMask = 0; 3062307SN/A} 3072307SN/A 3082307SN/Atemplate<class Impl> 3092307SN/Avoid 3102292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 3112292SN/A{ 3122329SN/A unsigned size_plus_sentinel = size + 1; 3132329SN/A assert(size_plus_sentinel >= LQEntries); 3142292SN/A 3152329SN/A if (size_plus_sentinel > LQEntries) { 3162329SN/A while (size_plus_sentinel > loadQueue.size()) { 3172292SN/A DynInstPtr dummy; 3182292SN/A loadQueue.push_back(dummy); 3192292SN/A LQEntries++; 3202292SN/A } 3212292SN/A } else { 3222329SN/A LQEntries = size_plus_sentinel; 3232292SN/A } 3242292SN/A 3252292SN/A} 3262292SN/A 3272292SN/Atemplate<class Impl> 3282292SN/Avoid 3292292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 3302292SN/A{ 3312329SN/A unsigned size_plus_sentinel = size + 1; 3322329SN/A if (size_plus_sentinel > SQEntries) { 3332329SN/A while (size_plus_sentinel > storeQueue.size()) { 3342292SN/A SQEntry dummy; 3352292SN/A storeQueue.push_back(dummy); 3362292SN/A SQEntries++; 3372292SN/A } 3382292SN/A } else { 3392329SN/A SQEntries = size_plus_sentinel; 3402292SN/A } 3412292SN/A} 3422292SN/A 3432292SN/Atemplate <class Impl> 3442292SN/Avoid 3452292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 3462292SN/A{ 3472292SN/A assert(inst->isMemRef()); 3482292SN/A 3492292SN/A assert(inst->isLoad() || inst->isStore()); 3502292SN/A 3512292SN/A if (inst->isLoad()) { 3522292SN/A insertLoad(inst); 3532292SN/A } else { 3542292SN/A insertStore(inst); 3552292SN/A } 3562292SN/A 3572292SN/A inst->setInLSQ(); 3582292SN/A} 3592292SN/A 3602292SN/Atemplate <class Impl> 3612292SN/Avoid 3622292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3632292SN/A{ 3642329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3652329SN/A assert(loads < LQEntries); 3662292SN/A 3677720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 3687720Sgblack@eecs.umich.edu load_inst->pcState(), loadTail, load_inst->seqNum); 3692292SN/A 3702292SN/A load_inst->lqIdx = loadTail; 3712292SN/A 3722292SN/A if (stores == 0) { 3732292SN/A load_inst->sqIdx = -1; 3742292SN/A } else { 3752292SN/A load_inst->sqIdx = storeTail; 3762292SN/A } 3772292SN/A 3782292SN/A loadQueue[loadTail] = load_inst; 3792292SN/A 3802292SN/A incrLdIdx(loadTail); 3812292SN/A 3822292SN/A ++loads; 3832292SN/A} 3842292SN/A 3852292SN/Atemplate <class Impl> 3862292SN/Avoid 3872292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3882292SN/A{ 3892292SN/A // Make sure it is not full before inserting an instruction. 3902292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3912292SN/A assert(stores < SQEntries); 3922292SN/A 3937720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 3947720Sgblack@eecs.umich.edu store_inst->pcState(), storeTail, store_inst->seqNum); 3952292SN/A 3962292SN/A store_inst->sqIdx = storeTail; 3972292SN/A store_inst->lqIdx = loadTail; 3982292SN/A 3992292SN/A storeQueue[storeTail] = SQEntry(store_inst); 4002292SN/A 4012292SN/A incrStIdx(storeTail); 4022292SN/A 4032292SN/A ++stores; 4042292SN/A} 4052292SN/A 4062292SN/Atemplate <class Impl> 4072292SN/Atypename Impl::DynInstPtr 4082292SN/ALSQUnit<Impl>::getMemDepViolator() 4092292SN/A{ 4102292SN/A DynInstPtr temp = memDepViolator; 4112292SN/A 4122292SN/A memDepViolator = NULL; 4132292SN/A 4142292SN/A return temp; 4152292SN/A} 4162292SN/A 4172292SN/Atemplate <class Impl> 4182292SN/Aunsigned 4192292SN/ALSQUnit<Impl>::numFreeEntries() 4202292SN/A{ 4212292SN/A unsigned free_lq_entries = LQEntries - loads; 4222292SN/A unsigned free_sq_entries = SQEntries - stores; 4232292SN/A 4242292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 4252292SN/A // empty/full conditions. Subtract 1 from the free entries. 4262292SN/A if (free_lq_entries < free_sq_entries) { 4272292SN/A return free_lq_entries - 1; 4282292SN/A } else { 4292292SN/A return free_sq_entries - 1; 4302292SN/A } 4312292SN/A} 4322292SN/A 4332292SN/Atemplate <class Impl> 4342292SN/Aint 4352292SN/ALSQUnit<Impl>::numLoadsReady() 4362292SN/A{ 4372292SN/A int load_idx = loadHead; 4382292SN/A int retval = 0; 4392292SN/A 4402292SN/A while (load_idx != loadTail) { 4412292SN/A assert(loadQueue[load_idx]); 4422292SN/A 4432292SN/A if (loadQueue[load_idx]->readyToIssue()) { 4442292SN/A ++retval; 4452292SN/A } 4462292SN/A } 4472292SN/A 4482292SN/A return retval; 4492292SN/A} 4502292SN/A 4512292SN/Atemplate <class Impl> 4528545Ssaidi@eecs.umich.eduvoid 4538545Ssaidi@eecs.umich.eduLSQUnit<Impl>::checkSnoop(PacketPtr pkt) 4548545Ssaidi@eecs.umich.edu{ 4558545Ssaidi@eecs.umich.edu int load_idx = loadHead; 4568545Ssaidi@eecs.umich.edu 4578545Ssaidi@eecs.umich.edu if (!cacheBlockMask) { 4588545Ssaidi@eecs.umich.edu assert(dcachePort); 4598545Ssaidi@eecs.umich.edu Addr bs = dcachePort->peerBlockSize(); 4608545Ssaidi@eecs.umich.edu 4618545Ssaidi@eecs.umich.edu // Make sure we actually got a size 4628545Ssaidi@eecs.umich.edu assert(bs != 0); 4638545Ssaidi@eecs.umich.edu 4648545Ssaidi@eecs.umich.edu cacheBlockMask = ~(bs - 1); 4658545Ssaidi@eecs.umich.edu } 4668545Ssaidi@eecs.umich.edu 4678545Ssaidi@eecs.umich.edu // If this is the only load in the LSQ we don't care 4688545Ssaidi@eecs.umich.edu if (load_idx == loadTail) 4698545Ssaidi@eecs.umich.edu return; 4708545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 4718545Ssaidi@eecs.umich.edu 4728545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr()); 4738545Ssaidi@eecs.umich.edu Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 4748545Ssaidi@eecs.umich.edu while (load_idx != loadTail) { 4758545Ssaidi@eecs.umich.edu DynInstPtr ld_inst = loadQueue[load_idx]; 4768545Ssaidi@eecs.umich.edu 4778545Ssaidi@eecs.umich.edu if (!ld_inst->effAddrValid || ld_inst->uncacheable()) { 4788545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 4798545Ssaidi@eecs.umich.edu continue; 4808545Ssaidi@eecs.umich.edu } 4818545Ssaidi@eecs.umich.edu 4828545Ssaidi@eecs.umich.edu Addr load_addr = ld_inst->physEffAddr & cacheBlockMask; 4838545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n", 4848545Ssaidi@eecs.umich.edu ld_inst->seqNum, load_addr, invalidate_addr); 4858545Ssaidi@eecs.umich.edu 4868545Ssaidi@eecs.umich.edu if (load_addr == invalidate_addr) { 4878545Ssaidi@eecs.umich.edu if (ld_inst->possibleLoadViolation) { 4888545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n", 4898545Ssaidi@eecs.umich.edu ld_inst->physEffAddr, pkt->getAddr(), ld_inst->seqNum); 4908545Ssaidi@eecs.umich.edu 4918545Ssaidi@eecs.umich.edu // Mark the load for re-execution 4928545Ssaidi@eecs.umich.edu ld_inst->fault = new ReExec; 4938545Ssaidi@eecs.umich.edu } else { 4948545Ssaidi@eecs.umich.edu // If a older load checks this and it's true 4958545Ssaidi@eecs.umich.edu // then we might have missed the snoop 4968545Ssaidi@eecs.umich.edu // in which case we need to invalidate to be sure 4978545Ssaidi@eecs.umich.edu ld_inst->hitExternalSnoop = true; 4988545Ssaidi@eecs.umich.edu } 4998545Ssaidi@eecs.umich.edu } 5008545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 5018545Ssaidi@eecs.umich.edu } 5028545Ssaidi@eecs.umich.edu return; 5038545Ssaidi@eecs.umich.edu} 5048545Ssaidi@eecs.umich.edu 5058545Ssaidi@eecs.umich.edutemplate <class Impl> 5062292SN/AFault 5078199SAli.Saidi@ARM.comLSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) 5088199SAli.Saidi@ARM.com{ 5098199SAli.Saidi@ARM.com Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 5108199SAli.Saidi@ARM.com Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 5118199SAli.Saidi@ARM.com 5128199SAli.Saidi@ARM.com /** @todo in theory you only need to check an instruction that has executed 5138199SAli.Saidi@ARM.com * however, there isn't a good way in the pipeline at the moment to check 5148199SAli.Saidi@ARM.com * all instructions that will execute before the store writes back. Thus, 5158199SAli.Saidi@ARM.com * like the implementation that came before it, we're overly conservative. 5168199SAli.Saidi@ARM.com */ 5178199SAli.Saidi@ARM.com while (load_idx != loadTail) { 5188199SAli.Saidi@ARM.com DynInstPtr ld_inst = loadQueue[load_idx]; 5198199SAli.Saidi@ARM.com if (!ld_inst->effAddrValid || ld_inst->uncacheable()) { 5208199SAli.Saidi@ARM.com incrLdIdx(load_idx); 5218199SAli.Saidi@ARM.com continue; 5228199SAli.Saidi@ARM.com } 5238199SAli.Saidi@ARM.com 5248199SAli.Saidi@ARM.com Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 5258199SAli.Saidi@ARM.com Addr ld_eff_addr2 = 5268199SAli.Saidi@ARM.com (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 5278199SAli.Saidi@ARM.com 5288272SAli.Saidi@ARM.com if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 5298545Ssaidi@eecs.umich.edu if (inst->isLoad()) { 5308545Ssaidi@eecs.umich.edu // If this load is to the same block as an external snoop 5318545Ssaidi@eecs.umich.edu // invalidate that we've observed then the load needs to be 5328545Ssaidi@eecs.umich.edu // squashed as it could have newer data 5338545Ssaidi@eecs.umich.edu if (ld_inst->hitExternalSnoop) { 5348545Ssaidi@eecs.umich.edu if (!memDepViolator || 5358545Ssaidi@eecs.umich.edu ld_inst->seqNum < memDepViolator->seqNum) { 5368545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] " 5378545Ssaidi@eecs.umich.edu " and [sn:%lli] at address %#x\n", inst->seqNum, 5388545Ssaidi@eecs.umich.edu ld_inst->seqNum, ld_eff_addr1); 5398545Ssaidi@eecs.umich.edu memDepViolator = ld_inst; 5408199SAli.Saidi@ARM.com 5418545Ssaidi@eecs.umich.edu ++lsqMemOrderViolation; 5428199SAli.Saidi@ARM.com 5438591Sgblack@eecs.umich.edu return new GenericISA::M5PanicFault( 5448591Sgblack@eecs.umich.edu "Detected fault with inst [sn:%lli] and " 5458591Sgblack@eecs.umich.edu "[sn:%lli] at address %#x\n", 5468591Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5478545Ssaidi@eecs.umich.edu } 5488545Ssaidi@eecs.umich.edu } 5498199SAli.Saidi@ARM.com 5508545Ssaidi@eecs.umich.edu // Otherwise, mark the load has a possible load violation 5518545Ssaidi@eecs.umich.edu // and if we see a snoop before it's commited, we need to squash 5528545Ssaidi@eecs.umich.edu ld_inst->possibleLoadViolation = true; 5538545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Found possible load violaiton at addr: %#x" 5548545Ssaidi@eecs.umich.edu " between instructions [sn:%lli] and [sn:%lli]\n", 5558545Ssaidi@eecs.umich.edu inst_eff_addr1, inst->seqNum, ld_inst->seqNum); 5568545Ssaidi@eecs.umich.edu } else { 5578545Ssaidi@eecs.umich.edu // A load/store incorrectly passed this store. 5588545Ssaidi@eecs.umich.edu // Check if we already have a violator, or if it's newer 5598545Ssaidi@eecs.umich.edu // squash and refetch. 5608545Ssaidi@eecs.umich.edu if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 5618545Ssaidi@eecs.umich.edu break; 5628545Ssaidi@eecs.umich.edu 5638545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and [sn:%lli]" 5648545Ssaidi@eecs.umich.edu " at address %#x\n", inst->seqNum, ld_inst->seqNum, 5658545Ssaidi@eecs.umich.edu ld_eff_addr1); 5668545Ssaidi@eecs.umich.edu memDepViolator = ld_inst; 5678545Ssaidi@eecs.umich.edu 5688545Ssaidi@eecs.umich.edu ++lsqMemOrderViolation; 5698545Ssaidi@eecs.umich.edu 5708591Sgblack@eecs.umich.edu return new GenericISA::M5PanicFault("Detected fault with " 5718591Sgblack@eecs.umich.edu "inst [sn:%lli] and [sn:%lli] at address %#x\n", 5728591Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5738545Ssaidi@eecs.umich.edu } 5748199SAli.Saidi@ARM.com } 5758199SAli.Saidi@ARM.com 5768199SAli.Saidi@ARM.com incrLdIdx(load_idx); 5778199SAli.Saidi@ARM.com } 5788199SAli.Saidi@ARM.com return NoFault; 5798199SAli.Saidi@ARM.com} 5808199SAli.Saidi@ARM.com 5818199SAli.Saidi@ARM.com 5828199SAli.Saidi@ARM.com 5838199SAli.Saidi@ARM.com 5848199SAli.Saidi@ARM.comtemplate <class Impl> 5858199SAli.Saidi@ARM.comFault 5862292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 5872292SN/A{ 5884032Sktlim@umich.edu using namespace TheISA; 5892292SN/A // Execute a specific load. 5902292SN/A Fault load_fault = NoFault; 5912292SN/A 5927720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 5937944SGiacomo.Gabrielli@arm.com inst->pcState(), inst->seqNum); 5942292SN/A 5954032Sktlim@umich.edu assert(!inst->isSquashed()); 5964032Sktlim@umich.edu 5972669Sktlim@umich.edu load_fault = inst->initiateAcc(); 5982292SN/A 5997944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 6007944SGiacomo.Gabrielli@arm.com load_fault == NoFault) 6017944SGiacomo.Gabrielli@arm.com return load_fault; 6027944SGiacomo.Gabrielli@arm.com 6037597Sminkyu.jeong@arm.com // If the instruction faulted or predicated false, then we need to send it 6047597Sminkyu.jeong@arm.com // along to commit without the instruction completing. 6057597Sminkyu.jeong@arm.com if (load_fault != NoFault || inst->readPredicate() == false) { 6062329SN/A // Send this instruction to commit, also make sure iew stage 6072329SN/A // realizes there is activity. 6082367SN/A // Mark it as executed unless it is an uncached load that 6092367SN/A // needs to hit the head of commit. 6107848SAli.Saidi@ARM.com if (inst->readPredicate() == false) 6117848SAli.Saidi@ARM.com inst->forwardOldRegs(); 6127600Sminkyu.jeong@arm.com DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 6137600Sminkyu.jeong@arm.com inst->seqNum, 6147600Sminkyu.jeong@arm.com (load_fault != NoFault ? "fault" : "predication")); 6154032Sktlim@umich.edu if (!(inst->hasRequest() && inst->uncacheable()) || 6163731Sktlim@umich.edu inst->isAtCommit()) { 6172367SN/A inst->setExecuted(); 6182367SN/A } 6192292SN/A iewStage->instToCommit(inst); 6202292SN/A iewStage->activityThisCycle(); 6214032Sktlim@umich.edu } else if (!loadBlocked()) { 6224032Sktlim@umich.edu assert(inst->effAddrValid); 6234032Sktlim@umich.edu int load_idx = inst->lqIdx; 6244032Sktlim@umich.edu incrLdIdx(load_idx); 6254032Sktlim@umich.edu 6268199SAli.Saidi@ARM.com if (checkLoads) 6278199SAli.Saidi@ARM.com return checkViolations(load_idx, inst); 6282292SN/A } 6292292SN/A 6302292SN/A return load_fault; 6312292SN/A} 6322292SN/A 6332292SN/Atemplate <class Impl> 6342292SN/AFault 6352292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 6362292SN/A{ 6372292SN/A using namespace TheISA; 6382292SN/A // Make sure that a store exists. 6392292SN/A assert(stores != 0); 6402292SN/A 6412292SN/A int store_idx = store_inst->sqIdx; 6422292SN/A 6437720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 6447720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 6452292SN/A 6464032Sktlim@umich.edu assert(!store_inst->isSquashed()); 6474032Sktlim@umich.edu 6482292SN/A // Check the recently completed loads to see if any match this store's 6492292SN/A // address. If so, then we have a memory ordering violation. 6502292SN/A int load_idx = store_inst->lqIdx; 6512292SN/A 6522292SN/A Fault store_fault = store_inst->initiateAcc(); 6532292SN/A 6547944SGiacomo.Gabrielli@arm.com if (store_inst->isTranslationDelayed() && 6557944SGiacomo.Gabrielli@arm.com store_fault == NoFault) 6567944SGiacomo.Gabrielli@arm.com return store_fault; 6577944SGiacomo.Gabrielli@arm.com 6587848SAli.Saidi@ARM.com if (store_inst->readPredicate() == false) 6597848SAli.Saidi@ARM.com store_inst->forwardOldRegs(); 6607848SAli.Saidi@ARM.com 6612329SN/A if (storeQueue[store_idx].size == 0) { 6627782Sminkyu.jeong@arm.com DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 6637720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 6642292SN/A 6652292SN/A return store_fault; 6667782Sminkyu.jeong@arm.com } else if (store_inst->readPredicate() == false) { 6677782Sminkyu.jeong@arm.com DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 6687782Sminkyu.jeong@arm.com store_inst->seqNum); 6697782Sminkyu.jeong@arm.com return store_fault; 6702292SN/A } 6712292SN/A 6722292SN/A assert(store_fault == NoFault); 6732292SN/A 6742336SN/A if (store_inst->isStoreConditional()) { 6752336SN/A // Store conditionals need to set themselves as able to 6762336SN/A // writeback if we haven't had a fault by here. 6772329SN/A storeQueue[store_idx].canWB = true; 6782292SN/A 6792329SN/A ++storesToWB; 6802292SN/A } 6812292SN/A 6828199SAli.Saidi@ARM.com return checkViolations(load_idx, store_inst); 6832292SN/A 6842292SN/A} 6852292SN/A 6862292SN/Atemplate <class Impl> 6872292SN/Avoid 6882292SN/ALSQUnit<Impl>::commitLoad() 6892292SN/A{ 6902292SN/A assert(loadQueue[loadHead]); 6912292SN/A 6927720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 6937720Sgblack@eecs.umich.edu loadQueue[loadHead]->pcState()); 6942292SN/A 6952292SN/A loadQueue[loadHead] = NULL; 6962292SN/A 6972292SN/A incrLdIdx(loadHead); 6982292SN/A 6992292SN/A --loads; 7002292SN/A} 7012292SN/A 7022292SN/Atemplate <class Impl> 7032292SN/Avoid 7042292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 7052292SN/A{ 7062292SN/A assert(loads == 0 || loadQueue[loadHead]); 7072292SN/A 7082292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 7092292SN/A commitLoad(); 7102292SN/A } 7112292SN/A} 7122292SN/A 7132292SN/Atemplate <class Impl> 7142292SN/Avoid 7152292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 7162292SN/A{ 7172292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 7182292SN/A 7192292SN/A int store_idx = storeHead; 7202292SN/A 7212292SN/A while (store_idx != storeTail) { 7222292SN/A assert(storeQueue[store_idx].inst); 7232329SN/A // Mark any stores that are now committed and have not yet 7242329SN/A // been marked as able to write back. 7252292SN/A if (!storeQueue[store_idx].canWB) { 7262292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 7272292SN/A break; 7282292SN/A } 7292292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 7307720Sgblack@eecs.umich.edu "%s [sn:%lli]\n", 7317720Sgblack@eecs.umich.edu storeQueue[store_idx].inst->pcState(), 7322292SN/A storeQueue[store_idx].inst->seqNum); 7332292SN/A 7342292SN/A storeQueue[store_idx].canWB = true; 7352292SN/A 7362292SN/A ++storesToWB; 7372292SN/A } 7382292SN/A 7392292SN/A incrStIdx(store_idx); 7402292SN/A } 7412292SN/A} 7422292SN/A 7432292SN/Atemplate <class Impl> 7442292SN/Avoid 7456974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::writebackPendingStore() 7466974Stjones1@inf.ed.ac.uk{ 7476974Stjones1@inf.ed.ac.uk if (hasPendingPkt) { 7486974Stjones1@inf.ed.ac.uk assert(pendingPkt != NULL); 7496974Stjones1@inf.ed.ac.uk 7506974Stjones1@inf.ed.ac.uk // If the cache is blocked, this will store the packet for retry. 7516974Stjones1@inf.ed.ac.uk if (sendStore(pendingPkt)) { 7526974Stjones1@inf.ed.ac.uk storePostSend(pendingPkt); 7536974Stjones1@inf.ed.ac.uk } 7546974Stjones1@inf.ed.ac.uk pendingPkt = NULL; 7556974Stjones1@inf.ed.ac.uk hasPendingPkt = false; 7566974Stjones1@inf.ed.ac.uk } 7576974Stjones1@inf.ed.ac.uk} 7586974Stjones1@inf.ed.ac.uk 7596974Stjones1@inf.ed.ac.uktemplate <class Impl> 7606974Stjones1@inf.ed.ac.ukvoid 7612292SN/ALSQUnit<Impl>::writebackStores() 7622292SN/A{ 7636974Stjones1@inf.ed.ac.uk // First writeback the second packet from any split store that didn't 7646974Stjones1@inf.ed.ac.uk // complete last cycle because there weren't enough cache ports available. 7656974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc) { 7666974Stjones1@inf.ed.ac.uk writebackPendingStore(); 7676974Stjones1@inf.ed.ac.uk } 7686974Stjones1@inf.ed.ac.uk 7692292SN/A while (storesToWB > 0 && 7702292SN/A storeWBIdx != storeTail && 7712292SN/A storeQueue[storeWBIdx].inst && 7722292SN/A storeQueue[storeWBIdx].canWB && 7732292SN/A usedPorts < cachePorts) { 7742292SN/A 7752907Sktlim@umich.edu if (isStoreBlocked || lsq->cacheBlocked()) { 7762678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 7772678Sktlim@umich.edu " is blocked!\n"); 7782678Sktlim@umich.edu break; 7792678Sktlim@umich.edu } 7802678Sktlim@umich.edu 7812329SN/A // Store didn't write any data so no need to write it back to 7822329SN/A // memory. 7832292SN/A if (storeQueue[storeWBIdx].size == 0) { 7842292SN/A completeStore(storeWBIdx); 7852292SN/A 7862292SN/A incrStIdx(storeWBIdx); 7872292SN/A 7882292SN/A continue; 7892292SN/A } 7902678Sktlim@umich.edu 7912292SN/A ++usedPorts; 7922292SN/A 7932292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 7942292SN/A incrStIdx(storeWBIdx); 7952292SN/A 7962292SN/A continue; 7972292SN/A } 7982292SN/A 7992292SN/A assert(storeQueue[storeWBIdx].req); 8002292SN/A assert(!storeQueue[storeWBIdx].committed); 8012292SN/A 8026974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 8036974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqLow); 8046974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqHigh); 8056974Stjones1@inf.ed.ac.uk } 8066974Stjones1@inf.ed.ac.uk 8072669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 8082669Sktlim@umich.edu 8092669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 8108481Sgblack@eecs.umich.edu RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 8118481Sgblack@eecs.umich.edu RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 8128481Sgblack@eecs.umich.edu 8132292SN/A storeQueue[storeWBIdx].committed = true; 8142292SN/A 8152669Sktlim@umich.edu assert(!inst->memData); 8162669Sktlim@umich.edu inst->memData = new uint8_t[64]; 8173772Sgblack@eecs.umich.edu 8184326Sgblack@eecs.umich.edu memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 8192669Sktlim@umich.edu 8204878Sstever@eecs.umich.edu MemCmd command = 8214878Sstever@eecs.umich.edu req->isSwap() ? MemCmd::SwapReq : 8226102Sgblack@eecs.umich.edu (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 8236974Stjones1@inf.ed.ac.uk PacketPtr data_pkt; 8246974Stjones1@inf.ed.ac.uk PacketPtr snd_data_pkt = NULL; 8252292SN/A 8262678Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 8272678Sktlim@umich.edu state->isLoad = false; 8282678Sktlim@umich.edu state->idx = storeWBIdx; 8292678Sktlim@umich.edu state->inst = inst; 8306974Stjones1@inf.ed.ac.uk 8316974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 8326974Stjones1@inf.ed.ac.uk 8336974Stjones1@inf.ed.ac.uk // Build a single data packet if the store isn't split. 8346974Stjones1@inf.ed.ac.uk data_pkt = new Packet(req, command, Packet::Broadcast); 8356974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 8366974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 8376974Stjones1@inf.ed.ac.uk } else { 8386974Stjones1@inf.ed.ac.uk // Create two packets if the store is split in two. 8396974Stjones1@inf.ed.ac.uk data_pkt = new Packet(sreqLow, command, Packet::Broadcast); 8406974Stjones1@inf.ed.ac.uk snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast); 8416974Stjones1@inf.ed.ac.uk 8426974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 8436974Stjones1@inf.ed.ac.uk snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 8446974Stjones1@inf.ed.ac.uk 8456974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 8466974Stjones1@inf.ed.ac.uk snd_data_pkt->senderState = state; 8476974Stjones1@inf.ed.ac.uk 8486974Stjones1@inf.ed.ac.uk state->isSplit = true; 8496974Stjones1@inf.ed.ac.uk state->outstanding = 2; 8506974Stjones1@inf.ed.ac.uk 8516974Stjones1@inf.ed.ac.uk // Can delete the main request now. 8526974Stjones1@inf.ed.ac.uk delete req; 8536974Stjones1@inf.ed.ac.uk req = sreqLow; 8546974Stjones1@inf.ed.ac.uk } 8552678Sktlim@umich.edu 8567720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 8572292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 8587720Sgblack@eecs.umich.edu storeWBIdx, inst->pcState(), 8593797Sgblack@eecs.umich.edu req->getPaddr(), (int)*(inst->memData), 8603221Sktlim@umich.edu inst->seqNum); 8612292SN/A 8622693Sktlim@umich.edu // @todo: Remove this SC hack once the memory system handles it. 8634350Sgblack@eecs.umich.edu if (inst->isStoreConditional()) { 8646974Stjones1@inf.ed.ac.uk assert(!storeQueue[storeWBIdx].isSplit); 8653326Sktlim@umich.edu // Disable recording the result temporarily. Writing to 8663326Sktlim@umich.edu // misc regs normally updates the result, but this is not 8673326Sktlim@umich.edu // the desired behavior when handling store conditionals. 8683326Sktlim@umich.edu inst->recordResult = false; 8693326Sktlim@umich.edu bool success = TheISA::handleLockedWrite(inst.get(), req); 8703326Sktlim@umich.edu inst->recordResult = true; 8713326Sktlim@umich.edu 8723326Sktlim@umich.edu if (!success) { 8733326Sktlim@umich.edu // Instantly complete this store. 8743326Sktlim@umich.edu DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 8753326Sktlim@umich.edu "Instantly completing it.\n", 8763326Sktlim@umich.edu inst->seqNum); 8773326Sktlim@umich.edu WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 8787823Ssteve.reinhardt@amd.com cpu->schedule(wb, curTick() + 1); 8793326Sktlim@umich.edu completeStore(storeWBIdx); 8803326Sktlim@umich.edu incrStIdx(storeWBIdx); 8813326Sktlim@umich.edu continue; 8822693Sktlim@umich.edu } 8832693Sktlim@umich.edu } else { 8842693Sktlim@umich.edu // Non-store conditionals do not need a writeback. 8852693Sktlim@umich.edu state->noWB = true; 8862693Sktlim@umich.edu } 8872693Sktlim@umich.edu 8888481Sgblack@eecs.umich.edu bool split = 8898481Sgblack@eecs.umich.edu TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit; 8908481Sgblack@eecs.umich.edu 8918481Sgblack@eecs.umich.edu ThreadContext *thread = cpu->tcBase(lsqID); 8928481Sgblack@eecs.umich.edu 8938481Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 8948481Sgblack@eecs.umich.edu assert(!inst->isStoreConditional()); 8958481Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread, data_pkt); 8968481Sgblack@eecs.umich.edu delete data_pkt; 8978481Sgblack@eecs.umich.edu if (split) { 8988481Sgblack@eecs.umich.edu assert(snd_data_pkt->req->isMmappedIpr()); 8998481Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread, snd_data_pkt); 9008481Sgblack@eecs.umich.edu delete snd_data_pkt; 9018481Sgblack@eecs.umich.edu delete sreqLow; 9028481Sgblack@eecs.umich.edu delete sreqHigh; 9038481Sgblack@eecs.umich.edu } 9048481Sgblack@eecs.umich.edu delete state; 9058481Sgblack@eecs.umich.edu delete req; 9068481Sgblack@eecs.umich.edu completeStore(storeWBIdx); 9078481Sgblack@eecs.umich.edu incrStIdx(storeWBIdx); 9088481Sgblack@eecs.umich.edu } else if (!sendStore(data_pkt)) { 9094032Sktlim@umich.edu DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 9103221Sktlim@umich.edu "retry later\n", 9113221Sktlim@umich.edu inst->seqNum); 9126974Stjones1@inf.ed.ac.uk 9136974Stjones1@inf.ed.ac.uk // Need to store the second packet, if split. 9148481Sgblack@eecs.umich.edu if (split) { 9156974Stjones1@inf.ed.ac.uk state->pktToSend = true; 9166974Stjones1@inf.ed.ac.uk state->pendingPacket = snd_data_pkt; 9176974Stjones1@inf.ed.ac.uk } 9182669Sktlim@umich.edu } else { 9196974Stjones1@inf.ed.ac.uk 9206974Stjones1@inf.ed.ac.uk // If split, try to send the second packet too 9218481Sgblack@eecs.umich.edu if (split) { 9226974Stjones1@inf.ed.ac.uk assert(snd_data_pkt); 9236974Stjones1@inf.ed.ac.uk 9246974Stjones1@inf.ed.ac.uk // Ensure there are enough ports to use. 9256974Stjones1@inf.ed.ac.uk if (usedPorts < cachePorts) { 9266974Stjones1@inf.ed.ac.uk ++usedPorts; 9276974Stjones1@inf.ed.ac.uk if (sendStore(snd_data_pkt)) { 9286974Stjones1@inf.ed.ac.uk storePostSend(snd_data_pkt); 9296974Stjones1@inf.ed.ac.uk } else { 9306974Stjones1@inf.ed.ac.uk DPRINTF(IEW, "D-Cache became blocked when writing" 9316974Stjones1@inf.ed.ac.uk " [sn:%lli] second packet, will retry later\n", 9326974Stjones1@inf.ed.ac.uk inst->seqNum); 9336974Stjones1@inf.ed.ac.uk } 9346974Stjones1@inf.ed.ac.uk } else { 9356974Stjones1@inf.ed.ac.uk 9366974Stjones1@inf.ed.ac.uk // Store the packet for when there's free ports. 9376974Stjones1@inf.ed.ac.uk assert(pendingPkt == NULL); 9386974Stjones1@inf.ed.ac.uk pendingPkt = snd_data_pkt; 9396974Stjones1@inf.ed.ac.uk hasPendingPkt = true; 9406974Stjones1@inf.ed.ac.uk } 9416974Stjones1@inf.ed.ac.uk } else { 9426974Stjones1@inf.ed.ac.uk 9436974Stjones1@inf.ed.ac.uk // Not a split store. 9446974Stjones1@inf.ed.ac.uk storePostSend(data_pkt); 9456974Stjones1@inf.ed.ac.uk } 9462292SN/A } 9472292SN/A } 9482292SN/A 9492292SN/A // Not sure this should set it to 0. 9502292SN/A usedPorts = 0; 9512292SN/A 9522292SN/A assert(stores >= 0 && storesToWB >= 0); 9532292SN/A} 9542292SN/A 9552292SN/A/*template <class Impl> 9562292SN/Avoid 9572292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 9582292SN/A{ 9592292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 9602292SN/A mshrSeqNums.end(), 9612292SN/A seqNum); 9622292SN/A 9632292SN/A if (mshr_it != mshrSeqNums.end()) { 9642292SN/A mshrSeqNums.erase(mshr_it); 9652292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 9662292SN/A } 9672292SN/A}*/ 9682292SN/A 9692292SN/Atemplate <class Impl> 9702292SN/Avoid 9712292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 9722292SN/A{ 9732292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 9742329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 9752292SN/A 9762292SN/A int load_idx = loadTail; 9772292SN/A decrLdIdx(load_idx); 9782292SN/A 9792292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 9807720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 9812292SN/A "[sn:%lli]\n", 9827720Sgblack@eecs.umich.edu loadQueue[load_idx]->pcState(), 9832292SN/A loadQueue[load_idx]->seqNum); 9842292SN/A 9852292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 9862292SN/A stalled = false; 9872292SN/A stallingStoreIsn = 0; 9882292SN/A stallingLoadIdx = 0; 9892292SN/A } 9902292SN/A 9912329SN/A // Clear the smart pointer to make sure it is decremented. 9922731Sktlim@umich.edu loadQueue[load_idx]->setSquashed(); 9932292SN/A loadQueue[load_idx] = NULL; 9942292SN/A --loads; 9952292SN/A 9962292SN/A // Inefficient! 9972292SN/A loadTail = load_idx; 9982292SN/A 9992292SN/A decrLdIdx(load_idx); 10002727Sktlim@umich.edu ++lsqSquashedLoads; 10012292SN/A } 10022292SN/A 10032292SN/A if (isLoadBlocked) { 10042292SN/A if (squashed_num < blockedLoadSeqNum) { 10052292SN/A isLoadBlocked = false; 10062292SN/A loadBlockedHandled = false; 10072292SN/A blockedLoadSeqNum = 0; 10082292SN/A } 10092292SN/A } 10102292SN/A 10114032Sktlim@umich.edu if (memDepViolator && squashed_num < memDepViolator->seqNum) { 10124032Sktlim@umich.edu memDepViolator = NULL; 10134032Sktlim@umich.edu } 10144032Sktlim@umich.edu 10152292SN/A int store_idx = storeTail; 10162292SN/A decrStIdx(store_idx); 10172292SN/A 10182292SN/A while (stores != 0 && 10192292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 10202329SN/A // Instructions marked as can WB are already committed. 10212292SN/A if (storeQueue[store_idx].canWB) { 10222292SN/A break; 10232292SN/A } 10242292SN/A 10257720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 10262292SN/A "idx:%i [sn:%lli]\n", 10277720Sgblack@eecs.umich.edu storeQueue[store_idx].inst->pcState(), 10282292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 10292292SN/A 10302329SN/A // I don't think this can happen. It should have been cleared 10312329SN/A // by the stalling load. 10322292SN/A if (isStalled() && 10332292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 10342292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 10352292SN/A stalled = false; 10362292SN/A stallingStoreIsn = 0; 10372292SN/A } 10382292SN/A 10392329SN/A // Clear the smart pointer to make sure it is decremented. 10402731Sktlim@umich.edu storeQueue[store_idx].inst->setSquashed(); 10412292SN/A storeQueue[store_idx].inst = NULL; 10422292SN/A storeQueue[store_idx].canWB = 0; 10432292SN/A 10444032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 10454032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the proper 10464032Sktlim@umich.edu // place to really handle request deletes. 10474032Sktlim@umich.edu delete storeQueue[store_idx].req; 10486974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 10496974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqLow; 10506974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqHigh; 10516974Stjones1@inf.ed.ac.uk 10526974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqLow = NULL; 10536974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqHigh = NULL; 10546974Stjones1@inf.ed.ac.uk } 10554032Sktlim@umich.edu 10562292SN/A storeQueue[store_idx].req = NULL; 10572292SN/A --stores; 10582292SN/A 10592292SN/A // Inefficient! 10602292SN/A storeTail = store_idx; 10612292SN/A 10622292SN/A decrStIdx(store_idx); 10632727Sktlim@umich.edu ++lsqSquashedStores; 10642292SN/A } 10652292SN/A} 10662292SN/A 10672292SN/Atemplate <class Impl> 10682292SN/Avoid 10693349Sbinkertn@umich.eduLSQUnit<Impl>::storePostSend(PacketPtr pkt) 10702693Sktlim@umich.edu{ 10712693Sktlim@umich.edu if (isStalled() && 10722693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 10732693Sktlim@umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 10742693Sktlim@umich.edu "load idx:%i\n", 10752693Sktlim@umich.edu stallingStoreIsn, stallingLoadIdx); 10762693Sktlim@umich.edu stalled = false; 10772693Sktlim@umich.edu stallingStoreIsn = 0; 10782693Sktlim@umich.edu iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 10792693Sktlim@umich.edu } 10802693Sktlim@umich.edu 10812693Sktlim@umich.edu if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 10822693Sktlim@umich.edu // The store is basically completed at this time. This 10832693Sktlim@umich.edu // only works so long as the checker doesn't try to 10842693Sktlim@umich.edu // verify the value in memory for stores. 10852693Sktlim@umich.edu storeQueue[storeWBIdx].inst->setCompleted(); 10862733Sktlim@umich.edu#if USE_CHECKER 10872693Sktlim@umich.edu if (cpu->checker) { 10882732Sktlim@umich.edu cpu->checker->verify(storeQueue[storeWBIdx].inst); 10892693Sktlim@umich.edu } 10902733Sktlim@umich.edu#endif 10912693Sktlim@umich.edu } 10922693Sktlim@umich.edu 10932693Sktlim@umich.edu incrStIdx(storeWBIdx); 10942693Sktlim@umich.edu} 10952693Sktlim@umich.edu 10962693Sktlim@umich.edutemplate <class Impl> 10972693Sktlim@umich.eduvoid 10982678Sktlim@umich.eduLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 10992678Sktlim@umich.edu{ 11002678Sktlim@umich.edu iewStage->wakeCPU(); 11012678Sktlim@umich.edu 11022678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 11032678Sktlim@umich.edu if (inst->isSquashed()) { 11042927Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 11052678Sktlim@umich.edu assert(!inst->isStore()); 11062727Sktlim@umich.edu ++lsqIgnoredResponses; 11072678Sktlim@umich.edu return; 11082678Sktlim@umich.edu } 11092678Sktlim@umich.edu 11102678Sktlim@umich.edu if (!inst->isExecuted()) { 11112678Sktlim@umich.edu inst->setExecuted(); 11122678Sktlim@umich.edu 11132678Sktlim@umich.edu // Complete access to copy data to proper place. 11142678Sktlim@umich.edu inst->completeAcc(pkt); 11152678Sktlim@umich.edu } 11162678Sktlim@umich.edu 11172678Sktlim@umich.edu // Need to insert instruction into queue to commit 11182678Sktlim@umich.edu iewStage->instToCommit(inst); 11192678Sktlim@umich.edu 11202678Sktlim@umich.edu iewStage->activityThisCycle(); 11217598Sminkyu.jeong@arm.com 11227598Sminkyu.jeong@arm.com // see if this load changed the PC 11237598Sminkyu.jeong@arm.com iewStage->checkMisprediction(inst); 11242678Sktlim@umich.edu} 11252678Sktlim@umich.edu 11262678Sktlim@umich.edutemplate <class Impl> 11272678Sktlim@umich.eduvoid 11282292SN/ALSQUnit<Impl>::completeStore(int store_idx) 11292292SN/A{ 11302292SN/A assert(storeQueue[store_idx].inst); 11312292SN/A storeQueue[store_idx].completed = true; 11322292SN/A --storesToWB; 11332292SN/A // A bit conservative because a store completion may not free up entries, 11342292SN/A // but hopefully avoids two store completions in one cycle from making 11352292SN/A // the CPU tick twice. 11363126Sktlim@umich.edu cpu->wakeCPU(); 11372292SN/A cpu->activityThisCycle(); 11382292SN/A 11392292SN/A if (store_idx == storeHead) { 11402292SN/A do { 11412292SN/A incrStIdx(storeHead); 11422292SN/A 11432292SN/A --stores; 11442292SN/A } while (storeQueue[storeHead].completed && 11452292SN/A storeHead != storeTail); 11462292SN/A 11472292SN/A iewStage->updateLSQNextCycle = true; 11482292SN/A } 11492292SN/A 11502329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 11512329SN/A "idx:%i\n", 11522329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 11532292SN/A 11542292SN/A if (isStalled() && 11552292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 11562292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 11572292SN/A "load idx:%i\n", 11582292SN/A stallingStoreIsn, stallingLoadIdx); 11592292SN/A stalled = false; 11602292SN/A stallingStoreIsn = 0; 11612292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 11622292SN/A } 11632316SN/A 11642316SN/A storeQueue[store_idx].inst->setCompleted(); 11652329SN/A 11662329SN/A // Tell the checker we've completed this instruction. Some stores 11672329SN/A // may get reported twice to the checker, but the checker can 11682329SN/A // handle that case. 11692733Sktlim@umich.edu#if USE_CHECKER 11702316SN/A if (cpu->checker) { 11712732Sktlim@umich.edu cpu->checker->verify(storeQueue[store_idx].inst); 11722316SN/A } 11732733Sktlim@umich.edu#endif 11742292SN/A} 11752292SN/A 11762292SN/Atemplate <class Impl> 11776974Stjones1@inf.ed.ac.ukbool 11786974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::sendStore(PacketPtr data_pkt) 11796974Stjones1@inf.ed.ac.uk{ 11806974Stjones1@inf.ed.ac.uk if (!dcachePort->sendTiming(data_pkt)) { 11816974Stjones1@inf.ed.ac.uk // Need to handle becoming blocked on a store. 11826974Stjones1@inf.ed.ac.uk isStoreBlocked = true; 11836974Stjones1@inf.ed.ac.uk ++lsqCacheBlocked; 11846974Stjones1@inf.ed.ac.uk assert(retryPkt == NULL); 11856974Stjones1@inf.ed.ac.uk retryPkt = data_pkt; 11866974Stjones1@inf.ed.ac.uk lsq->setRetryTid(lsqID); 11876974Stjones1@inf.ed.ac.uk return false; 11886974Stjones1@inf.ed.ac.uk } 11896974Stjones1@inf.ed.ac.uk return true; 11906974Stjones1@inf.ed.ac.uk} 11916974Stjones1@inf.ed.ac.uk 11926974Stjones1@inf.ed.ac.uktemplate <class Impl> 11932693Sktlim@umich.eduvoid 11942693Sktlim@umich.eduLSQUnit<Impl>::recvRetry() 11952693Sktlim@umich.edu{ 11962698Sktlim@umich.edu if (isStoreBlocked) { 11974985Sktlim@umich.edu DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 11982698Sktlim@umich.edu assert(retryPkt != NULL); 11992693Sktlim@umich.edu 12008587Snilay@cs.wisc.edu LSQSenderState *state = 12018587Snilay@cs.wisc.edu dynamic_cast<LSQSenderState *>(retryPkt->senderState); 12028587Snilay@cs.wisc.edu 12032698Sktlim@umich.edu if (dcachePort->sendTiming(retryPkt)) { 12046974Stjones1@inf.ed.ac.uk // Don't finish the store unless this is the last packet. 12058133SAli.Saidi@ARM.com if (!TheISA::HasUnalignedMemAcc || !state->pktToSend || 12068133SAli.Saidi@ARM.com state->pendingPacket == retryPkt) { 12078133SAli.Saidi@ARM.com state->pktToSend = false; 12086974Stjones1@inf.ed.ac.uk storePostSend(retryPkt); 12096974Stjones1@inf.ed.ac.uk } 12102699Sktlim@umich.edu retryPkt = NULL; 12112693Sktlim@umich.edu isStoreBlocked = false; 12126221Snate@binkert.org lsq->setRetryTid(InvalidThreadID); 12136974Stjones1@inf.ed.ac.uk 12146974Stjones1@inf.ed.ac.uk // Send any outstanding packet. 12156974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 12166974Stjones1@inf.ed.ac.uk assert(state->pendingPacket); 12176974Stjones1@inf.ed.ac.uk if (sendStore(state->pendingPacket)) { 12186974Stjones1@inf.ed.ac.uk storePostSend(state->pendingPacket); 12196974Stjones1@inf.ed.ac.uk } 12206974Stjones1@inf.ed.ac.uk } 12212693Sktlim@umich.edu } else { 12222693Sktlim@umich.edu // Still blocked! 12232727Sktlim@umich.edu ++lsqCacheBlocked; 12242907Sktlim@umich.edu lsq->setRetryTid(lsqID); 12252693Sktlim@umich.edu } 12262693Sktlim@umich.edu } else if (isLoadBlocked) { 12272693Sktlim@umich.edu DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 12282693Sktlim@umich.edu "no need to resend packet.\n"); 12292693Sktlim@umich.edu } else { 12302693Sktlim@umich.edu DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 12312693Sktlim@umich.edu } 12322693Sktlim@umich.edu} 12332693Sktlim@umich.edu 12342693Sktlim@umich.edutemplate <class Impl> 12352292SN/Ainline void 12362292SN/ALSQUnit<Impl>::incrStIdx(int &store_idx) 12372292SN/A{ 12382292SN/A if (++store_idx >= SQEntries) 12392292SN/A store_idx = 0; 12402292SN/A} 12412292SN/A 12422292SN/Atemplate <class Impl> 12432292SN/Ainline void 12442292SN/ALSQUnit<Impl>::decrStIdx(int &store_idx) 12452292SN/A{ 12462292SN/A if (--store_idx < 0) 12472292SN/A store_idx += SQEntries; 12482292SN/A} 12492292SN/A 12502292SN/Atemplate <class Impl> 12512292SN/Ainline void 12522292SN/ALSQUnit<Impl>::incrLdIdx(int &load_idx) 12532292SN/A{ 12542292SN/A if (++load_idx >= LQEntries) 12552292SN/A load_idx = 0; 12562292SN/A} 12572292SN/A 12582292SN/Atemplate <class Impl> 12592292SN/Ainline void 12602292SN/ALSQUnit<Impl>::decrLdIdx(int &load_idx) 12612292SN/A{ 12622292SN/A if (--load_idx < 0) 12632292SN/A load_idx += LQEntries; 12642292SN/A} 12652329SN/A 12662329SN/Atemplate <class Impl> 12672329SN/Avoid 12682329SN/ALSQUnit<Impl>::dumpInsts() 12692329SN/A{ 12702329SN/A cprintf("Load store queue: Dumping instructions.\n"); 12712329SN/A cprintf("Load queue size: %i\n", loads); 12722329SN/A cprintf("Load queue: "); 12732329SN/A 12742329SN/A int load_idx = loadHead; 12752329SN/A 12762329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 12777720Sgblack@eecs.umich.edu cprintf("%s ", loadQueue[load_idx]->pcState()); 12782329SN/A 12792329SN/A incrLdIdx(load_idx); 12802329SN/A } 12812329SN/A 12822329SN/A cprintf("Store queue size: %i\n", stores); 12832329SN/A cprintf("Store queue: "); 12842329SN/A 12852329SN/A int store_idx = storeHead; 12862329SN/A 12872329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 12887720Sgblack@eecs.umich.edu cprintf("%s ", storeQueue[store_idx].inst->pcState()); 12892329SN/A 12902329SN/A incrStIdx(store_idx); 12912329SN/A } 12922329SN/A 12932329SN/A cprintf("\n"); 12942329SN/A} 1295