lsq_unit_impl.hh revision 8272
12292SN/A/* 27597Sminkyu.jeong@arm.com * Copyright (c) 2010 ARM Limited 37597Sminkyu.jeong@arm.com * All rights reserved 47597Sminkyu.jeong@arm.com * 57597Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67597Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77597Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87597Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97597Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107597Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117597Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127597Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137597Sminkyu.jeong@arm.com * 142292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 152292SN/A * All rights reserved. 162292SN/A * 172292SN/A * Redistribution and use in source and binary forms, with or without 182292SN/A * modification, are permitted provided that the following conditions are 192292SN/A * met: redistributions of source code must retain the above copyright 202292SN/A * notice, this list of conditions and the following disclaimer; 212292SN/A * redistributions in binary form must reproduce the above copyright 222292SN/A * notice, this list of conditions and the following disclaimer in the 232292SN/A * documentation and/or other materials provided with the distribution; 242292SN/A * neither the name of the copyright holders nor the names of its 252292SN/A * contributors may be used to endorse or promote products derived from 262292SN/A * this software without specific prior written permission. 272292SN/A * 282292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392689Sktlim@umich.edu * 402689Sktlim@umich.edu * Authors: Kevin Lim 412689Sktlim@umich.edu * Korey Sewell 422292SN/A */ 432292SN/A 443326Sktlim@umich.edu#include "arch/locked_mem.hh" 458229Snate@binkert.org#include "base/str.hh" 466658Snate@binkert.org#include "config/the_isa.hh" 472733Sktlim@umich.edu#include "config/use_checker.hh" 482907Sktlim@umich.edu#include "cpu/o3/lsq.hh" 492292SN/A#include "cpu/o3/lsq_unit.hh" 508232Snate@binkert.org#include "debug/Activity.hh" 518232Snate@binkert.org#include "debug/IEW.hh" 528232Snate@binkert.org#include "debug/LSQUnit.hh" 532722Sktlim@umich.edu#include "mem/packet.hh" 542669Sktlim@umich.edu#include "mem/request.hh" 552292SN/A 562790Sktlim@umich.edu#if USE_CHECKER 572790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 582790Sktlim@umich.edu#endif 592790Sktlim@umich.edu 602669Sktlim@umich.edutemplate<class Impl> 612678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 622678Sktlim@umich.edu LSQUnit *lsq_ptr) 635606Snate@binkert.org : inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 642292SN/A{ 652678Sktlim@umich.edu this->setFlags(Event::AutoDelete); 662292SN/A} 672292SN/A 682669Sktlim@umich.edutemplate<class Impl> 692292SN/Avoid 702678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 712292SN/A{ 722678Sktlim@umich.edu if (!lsqPtr->isSwitchedOut()) { 732678Sktlim@umich.edu lsqPtr->writeback(inst, pkt); 742678Sktlim@umich.edu } 754319Sktlim@umich.edu 764319Sktlim@umich.edu if (pkt->senderState) 774319Sktlim@umich.edu delete pkt->senderState; 784319Sktlim@umich.edu 794319Sktlim@umich.edu delete pkt->req; 802678Sktlim@umich.edu delete pkt; 812678Sktlim@umich.edu} 822292SN/A 832678Sktlim@umich.edutemplate<class Impl> 842678Sktlim@umich.educonst char * 855336Shines@cs.fsu.eduLSQUnit<Impl>::WritebackEvent::description() const 862678Sktlim@umich.edu{ 874873Sstever@eecs.umich.edu return "Store writeback"; 882678Sktlim@umich.edu} 892292SN/A 902678Sktlim@umich.edutemplate<class Impl> 912678Sktlim@umich.eduvoid 922678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 932678Sktlim@umich.edu{ 942678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 952678Sktlim@umich.edu DynInstPtr inst = state->inst; 967852SMatt.Horsnell@arm.com DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum); 977852SMatt.Horsnell@arm.com DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum); 982344SN/A 992678Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 1002678Sktlim@umich.edu 1014986Ssaidi@eecs.umich.edu assert(!pkt->wasNacked()); 1024986Ssaidi@eecs.umich.edu 1036974Stjones1@inf.ed.ac.uk // If this is a split access, wait until all packets are received. 1046974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && !state->complete()) { 1056974Stjones1@inf.ed.ac.uk delete pkt->req; 1066974Stjones1@inf.ed.ac.uk delete pkt; 1076974Stjones1@inf.ed.ac.uk return; 1086974Stjones1@inf.ed.ac.uk } 1096974Stjones1@inf.ed.ac.uk 1102678Sktlim@umich.edu if (isSwitchedOut() || inst->isSquashed()) { 1112820Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 1122678Sktlim@umich.edu } else { 1132678Sktlim@umich.edu if (!state->noWB) { 1146974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 1156974Stjones1@inf.ed.ac.uk !state->isLoad) { 1166974Stjones1@inf.ed.ac.uk writeback(inst, pkt); 1176974Stjones1@inf.ed.ac.uk } else { 1186974Stjones1@inf.ed.ac.uk writeback(inst, state->mainPkt); 1196974Stjones1@inf.ed.ac.uk } 1202678Sktlim@umich.edu } 1212678Sktlim@umich.edu 1222678Sktlim@umich.edu if (inst->isStore()) { 1232678Sktlim@umich.edu completeStore(state->idx); 1242678Sktlim@umich.edu } 1252344SN/A } 1262307SN/A 1276974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 1286974Stjones1@inf.ed.ac.uk delete state->mainPkt->req; 1296974Stjones1@inf.ed.ac.uk delete state->mainPkt; 1306974Stjones1@inf.ed.ac.uk } 1312678Sktlim@umich.edu delete state; 1324032Sktlim@umich.edu delete pkt->req; 1332678Sktlim@umich.edu delete pkt; 1342292SN/A} 1352292SN/A 1362292SN/Atemplate <class Impl> 1372292SN/ALSQUnit<Impl>::LSQUnit() 1382678Sktlim@umich.edu : loads(0), stores(0), storesToWB(0), stalled(false), 1392678Sktlim@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1406974Stjones1@inf.ed.ac.uk loadBlockedHandled(false), hasPendingPkt(false) 1412292SN/A{ 1422292SN/A} 1432292SN/A 1442292SN/Atemplate<class Impl> 1452292SN/Avoid 1465529Snate@binkert.orgLSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 1475529Snate@binkert.org LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 1485529Snate@binkert.org unsigned id) 1492292SN/A{ 1504329Sktlim@umich.edu cpu = cpu_ptr; 1514329Sktlim@umich.edu iewStage = iew_ptr; 1524329Sktlim@umich.edu 1534329Sktlim@umich.edu DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1542292SN/A 1552307SN/A switchedOut = false; 1562307SN/A 1572907Sktlim@umich.edu lsq = lsq_ptr; 1582907Sktlim@umich.edu 1592292SN/A lsqID = id; 1602292SN/A 1612329SN/A // Add 1 for the sentinel entry (they are circular queues). 1622329SN/A LQEntries = maxLQEntries + 1; 1632329SN/A SQEntries = maxSQEntries + 1; 1642292SN/A 1652292SN/A loadQueue.resize(LQEntries); 1662292SN/A storeQueue.resize(SQEntries); 1672292SN/A 1688199SAli.Saidi@ARM.com depCheckShift = params->LSQDepCheckShift; 1698199SAli.Saidi@ARM.com checkLoads = params->LSQCheckLoads; 1708199SAli.Saidi@ARM.com 1712292SN/A loadHead = loadTail = 0; 1722292SN/A 1732292SN/A storeHead = storeWBIdx = storeTail = 0; 1742292SN/A 1752292SN/A usedPorts = 0; 1762292SN/A cachePorts = params->cachePorts; 1772292SN/A 1783492Sktlim@umich.edu retryPkt = NULL; 1792329SN/A memDepViolator = NULL; 1802292SN/A 1812292SN/A blockedLoadSeqNum = 0; 1822292SN/A} 1832292SN/A 1842292SN/Atemplate<class Impl> 1852292SN/Astd::string 1862292SN/ALSQUnit<Impl>::name() const 1872292SN/A{ 1882292SN/A if (Impl::MaxThreads == 1) { 1892292SN/A return iewStage->name() + ".lsq"; 1902292SN/A } else { 1918247Snate@binkert.org return iewStage->name() + ".lsq.thread" + to_string(lsqID); 1922292SN/A } 1932292SN/A} 1942292SN/A 1952292SN/Atemplate<class Impl> 1962292SN/Avoid 1972727Sktlim@umich.eduLSQUnit<Impl>::regStats() 1982727Sktlim@umich.edu{ 1992727Sktlim@umich.edu lsqForwLoads 2002727Sktlim@umich.edu .name(name() + ".forwLoads") 2012727Sktlim@umich.edu .desc("Number of loads that had data forwarded from stores"); 2022727Sktlim@umich.edu 2032727Sktlim@umich.edu invAddrLoads 2042727Sktlim@umich.edu .name(name() + ".invAddrLoads") 2052727Sktlim@umich.edu .desc("Number of loads ignored due to an invalid address"); 2062727Sktlim@umich.edu 2072727Sktlim@umich.edu lsqSquashedLoads 2082727Sktlim@umich.edu .name(name() + ".squashedLoads") 2092727Sktlim@umich.edu .desc("Number of loads squashed"); 2102727Sktlim@umich.edu 2112727Sktlim@umich.edu lsqIgnoredResponses 2122727Sktlim@umich.edu .name(name() + ".ignoredResponses") 2132727Sktlim@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 2142727Sktlim@umich.edu 2152361SN/A lsqMemOrderViolation 2162361SN/A .name(name() + ".memOrderViolation") 2172361SN/A .desc("Number of memory ordering violations"); 2182361SN/A 2192727Sktlim@umich.edu lsqSquashedStores 2202727Sktlim@umich.edu .name(name() + ".squashedStores") 2212727Sktlim@umich.edu .desc("Number of stores squashed"); 2222727Sktlim@umich.edu 2232727Sktlim@umich.edu invAddrSwpfs 2242727Sktlim@umich.edu .name(name() + ".invAddrSwpfs") 2252727Sktlim@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 2262727Sktlim@umich.edu 2272727Sktlim@umich.edu lsqBlockedLoads 2282727Sktlim@umich.edu .name(name() + ".blockedLoads") 2292727Sktlim@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 2302727Sktlim@umich.edu 2312727Sktlim@umich.edu lsqRescheduledLoads 2322727Sktlim@umich.edu .name(name() + ".rescheduledLoads") 2332727Sktlim@umich.edu .desc("Number of loads that were rescheduled"); 2342727Sktlim@umich.edu 2352727Sktlim@umich.edu lsqCacheBlocked 2362727Sktlim@umich.edu .name(name() + ".cacheBlocked") 2372727Sktlim@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2382727Sktlim@umich.edu} 2392727Sktlim@umich.edu 2402727Sktlim@umich.edutemplate<class Impl> 2412727Sktlim@umich.eduvoid 2424329Sktlim@umich.eduLSQUnit<Impl>::setDcachePort(Port *dcache_port) 2434329Sktlim@umich.edu{ 2444329Sktlim@umich.edu dcachePort = dcache_port; 2454329Sktlim@umich.edu 2464329Sktlim@umich.edu#if USE_CHECKER 2474329Sktlim@umich.edu if (cpu->checker) { 2484329Sktlim@umich.edu cpu->checker->setDcachePort(dcachePort); 2494329Sktlim@umich.edu } 2504329Sktlim@umich.edu#endif 2514329Sktlim@umich.edu} 2524329Sktlim@umich.edu 2534329Sktlim@umich.edutemplate<class Impl> 2544329Sktlim@umich.eduvoid 2552292SN/ALSQUnit<Impl>::clearLQ() 2562292SN/A{ 2572292SN/A loadQueue.clear(); 2582292SN/A} 2592292SN/A 2602292SN/Atemplate<class Impl> 2612292SN/Avoid 2622292SN/ALSQUnit<Impl>::clearSQ() 2632292SN/A{ 2642292SN/A storeQueue.clear(); 2652292SN/A} 2662292SN/A 2672292SN/Atemplate<class Impl> 2682292SN/Avoid 2692307SN/ALSQUnit<Impl>::switchOut() 2702307SN/A{ 2712307SN/A switchedOut = true; 2722367SN/A for (int i = 0; i < loadQueue.size(); ++i) { 2732367SN/A assert(!loadQueue[i]); 2742307SN/A loadQueue[i] = NULL; 2752367SN/A } 2762307SN/A 2772329SN/A assert(storesToWB == 0); 2782307SN/A} 2792307SN/A 2802307SN/Atemplate<class Impl> 2812307SN/Avoid 2822307SN/ALSQUnit<Impl>::takeOverFrom() 2832307SN/A{ 2842307SN/A switchedOut = false; 2852307SN/A loads = stores = storesToWB = 0; 2862307SN/A 2872307SN/A loadHead = loadTail = 0; 2882307SN/A 2892307SN/A storeHead = storeWBIdx = storeTail = 0; 2902307SN/A 2912307SN/A usedPorts = 0; 2922307SN/A 2932329SN/A memDepViolator = NULL; 2942307SN/A 2952307SN/A blockedLoadSeqNum = 0; 2962307SN/A 2972307SN/A stalled = false; 2982307SN/A isLoadBlocked = false; 2992307SN/A loadBlockedHandled = false; 3002307SN/A} 3012307SN/A 3022307SN/Atemplate<class Impl> 3032307SN/Avoid 3042292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 3052292SN/A{ 3062329SN/A unsigned size_plus_sentinel = size + 1; 3072329SN/A assert(size_plus_sentinel >= LQEntries); 3082292SN/A 3092329SN/A if (size_plus_sentinel > LQEntries) { 3102329SN/A while (size_plus_sentinel > loadQueue.size()) { 3112292SN/A DynInstPtr dummy; 3122292SN/A loadQueue.push_back(dummy); 3132292SN/A LQEntries++; 3142292SN/A } 3152292SN/A } else { 3162329SN/A LQEntries = size_plus_sentinel; 3172292SN/A } 3182292SN/A 3192292SN/A} 3202292SN/A 3212292SN/Atemplate<class Impl> 3222292SN/Avoid 3232292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 3242292SN/A{ 3252329SN/A unsigned size_plus_sentinel = size + 1; 3262329SN/A if (size_plus_sentinel > SQEntries) { 3272329SN/A while (size_plus_sentinel > storeQueue.size()) { 3282292SN/A SQEntry dummy; 3292292SN/A storeQueue.push_back(dummy); 3302292SN/A SQEntries++; 3312292SN/A } 3322292SN/A } else { 3332329SN/A SQEntries = size_plus_sentinel; 3342292SN/A } 3352292SN/A} 3362292SN/A 3372292SN/Atemplate <class Impl> 3382292SN/Avoid 3392292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 3402292SN/A{ 3412292SN/A assert(inst->isMemRef()); 3422292SN/A 3432292SN/A assert(inst->isLoad() || inst->isStore()); 3442292SN/A 3452292SN/A if (inst->isLoad()) { 3462292SN/A insertLoad(inst); 3472292SN/A } else { 3482292SN/A insertStore(inst); 3492292SN/A } 3502292SN/A 3512292SN/A inst->setInLSQ(); 3522292SN/A} 3532292SN/A 3542292SN/Atemplate <class Impl> 3552292SN/Avoid 3562292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3572292SN/A{ 3582329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3592329SN/A assert(loads < LQEntries); 3602292SN/A 3617720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 3627720Sgblack@eecs.umich.edu load_inst->pcState(), loadTail, load_inst->seqNum); 3632292SN/A 3642292SN/A load_inst->lqIdx = loadTail; 3652292SN/A 3662292SN/A if (stores == 0) { 3672292SN/A load_inst->sqIdx = -1; 3682292SN/A } else { 3692292SN/A load_inst->sqIdx = storeTail; 3702292SN/A } 3712292SN/A 3722292SN/A loadQueue[loadTail] = load_inst; 3732292SN/A 3742292SN/A incrLdIdx(loadTail); 3752292SN/A 3762292SN/A ++loads; 3772292SN/A} 3782292SN/A 3792292SN/Atemplate <class Impl> 3802292SN/Avoid 3812292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3822292SN/A{ 3832292SN/A // Make sure it is not full before inserting an instruction. 3842292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3852292SN/A assert(stores < SQEntries); 3862292SN/A 3877720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 3887720Sgblack@eecs.umich.edu store_inst->pcState(), storeTail, store_inst->seqNum); 3892292SN/A 3902292SN/A store_inst->sqIdx = storeTail; 3912292SN/A store_inst->lqIdx = loadTail; 3922292SN/A 3932292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3942292SN/A 3952292SN/A incrStIdx(storeTail); 3962292SN/A 3972292SN/A ++stores; 3982292SN/A} 3992292SN/A 4002292SN/Atemplate <class Impl> 4012292SN/Atypename Impl::DynInstPtr 4022292SN/ALSQUnit<Impl>::getMemDepViolator() 4032292SN/A{ 4042292SN/A DynInstPtr temp = memDepViolator; 4052292SN/A 4062292SN/A memDepViolator = NULL; 4072292SN/A 4082292SN/A return temp; 4092292SN/A} 4102292SN/A 4112292SN/Atemplate <class Impl> 4122292SN/Aunsigned 4132292SN/ALSQUnit<Impl>::numFreeEntries() 4142292SN/A{ 4152292SN/A unsigned free_lq_entries = LQEntries - loads; 4162292SN/A unsigned free_sq_entries = SQEntries - stores; 4172292SN/A 4182292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 4192292SN/A // empty/full conditions. Subtract 1 from the free entries. 4202292SN/A if (free_lq_entries < free_sq_entries) { 4212292SN/A return free_lq_entries - 1; 4222292SN/A } else { 4232292SN/A return free_sq_entries - 1; 4242292SN/A } 4252292SN/A} 4262292SN/A 4272292SN/Atemplate <class Impl> 4282292SN/Aint 4292292SN/ALSQUnit<Impl>::numLoadsReady() 4302292SN/A{ 4312292SN/A int load_idx = loadHead; 4322292SN/A int retval = 0; 4332292SN/A 4342292SN/A while (load_idx != loadTail) { 4352292SN/A assert(loadQueue[load_idx]); 4362292SN/A 4372292SN/A if (loadQueue[load_idx]->readyToIssue()) { 4382292SN/A ++retval; 4392292SN/A } 4402292SN/A } 4412292SN/A 4422292SN/A return retval; 4432292SN/A} 4442292SN/A 4452292SN/Atemplate <class Impl> 4462292SN/AFault 4478199SAli.Saidi@ARM.comLSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) 4488199SAli.Saidi@ARM.com{ 4498199SAli.Saidi@ARM.com Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 4508199SAli.Saidi@ARM.com Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 4518199SAli.Saidi@ARM.com 4528199SAli.Saidi@ARM.com /** @todo in theory you only need to check an instruction that has executed 4538199SAli.Saidi@ARM.com * however, there isn't a good way in the pipeline at the moment to check 4548199SAli.Saidi@ARM.com * all instructions that will execute before the store writes back. Thus, 4558199SAli.Saidi@ARM.com * like the implementation that came before it, we're overly conservative. 4568199SAli.Saidi@ARM.com */ 4578199SAli.Saidi@ARM.com while (load_idx != loadTail) { 4588199SAli.Saidi@ARM.com DynInstPtr ld_inst = loadQueue[load_idx]; 4598199SAli.Saidi@ARM.com if (!ld_inst->effAddrValid || ld_inst->uncacheable()) { 4608199SAli.Saidi@ARM.com incrLdIdx(load_idx); 4618199SAli.Saidi@ARM.com continue; 4628199SAli.Saidi@ARM.com } 4638199SAli.Saidi@ARM.com 4648199SAli.Saidi@ARM.com Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 4658199SAli.Saidi@ARM.com Addr ld_eff_addr2 = 4668199SAli.Saidi@ARM.com (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 4678199SAli.Saidi@ARM.com 4688272SAli.Saidi@ARM.com if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 4698199SAli.Saidi@ARM.com // A load/store incorrectly passed this load/store. 4708199SAli.Saidi@ARM.com // Check if we already have a violator, or if it's newer 4718199SAli.Saidi@ARM.com // squash and refetch. 4728199SAli.Saidi@ARM.com if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 4738199SAli.Saidi@ARM.com break; 4748199SAli.Saidi@ARM.com 4758199SAli.Saidi@ARM.com DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and [sn:%lli]" 4768199SAli.Saidi@ARM.com " at address %#x\n", inst->seqNum, ld_inst->seqNum, 4778199SAli.Saidi@ARM.com ld_eff_addr1); 4788199SAli.Saidi@ARM.com memDepViolator = ld_inst; 4798199SAli.Saidi@ARM.com 4808199SAli.Saidi@ARM.com ++lsqMemOrderViolation; 4818199SAli.Saidi@ARM.com 4828199SAli.Saidi@ARM.com return TheISA::genMachineCheckFault(); 4838199SAli.Saidi@ARM.com } 4848199SAli.Saidi@ARM.com 4858199SAli.Saidi@ARM.com incrLdIdx(load_idx); 4868199SAli.Saidi@ARM.com } 4878199SAli.Saidi@ARM.com return NoFault; 4888199SAli.Saidi@ARM.com} 4898199SAli.Saidi@ARM.com 4908199SAli.Saidi@ARM.com 4918199SAli.Saidi@ARM.com 4928199SAli.Saidi@ARM.com 4938199SAli.Saidi@ARM.comtemplate <class Impl> 4948199SAli.Saidi@ARM.comFault 4952292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 4962292SN/A{ 4974032Sktlim@umich.edu using namespace TheISA; 4982292SN/A // Execute a specific load. 4992292SN/A Fault load_fault = NoFault; 5002292SN/A 5017720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 5027944SGiacomo.Gabrielli@arm.com inst->pcState(), inst->seqNum); 5032292SN/A 5044032Sktlim@umich.edu assert(!inst->isSquashed()); 5054032Sktlim@umich.edu 5062669Sktlim@umich.edu load_fault = inst->initiateAcc(); 5072292SN/A 5087944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 5097944SGiacomo.Gabrielli@arm.com load_fault == NoFault) 5107944SGiacomo.Gabrielli@arm.com return load_fault; 5117944SGiacomo.Gabrielli@arm.com 5127597Sminkyu.jeong@arm.com // If the instruction faulted or predicated false, then we need to send it 5137597Sminkyu.jeong@arm.com // along to commit without the instruction completing. 5147597Sminkyu.jeong@arm.com if (load_fault != NoFault || inst->readPredicate() == false) { 5152329SN/A // Send this instruction to commit, also make sure iew stage 5162329SN/A // realizes there is activity. 5172367SN/A // Mark it as executed unless it is an uncached load that 5182367SN/A // needs to hit the head of commit. 5197848SAli.Saidi@ARM.com if (inst->readPredicate() == false) 5207848SAli.Saidi@ARM.com inst->forwardOldRegs(); 5217600Sminkyu.jeong@arm.com DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 5227600Sminkyu.jeong@arm.com inst->seqNum, 5237600Sminkyu.jeong@arm.com (load_fault != NoFault ? "fault" : "predication")); 5244032Sktlim@umich.edu if (!(inst->hasRequest() && inst->uncacheable()) || 5253731Sktlim@umich.edu inst->isAtCommit()) { 5262367SN/A inst->setExecuted(); 5272367SN/A } 5282292SN/A iewStage->instToCommit(inst); 5292292SN/A iewStage->activityThisCycle(); 5304032Sktlim@umich.edu } else if (!loadBlocked()) { 5314032Sktlim@umich.edu assert(inst->effAddrValid); 5324032Sktlim@umich.edu int load_idx = inst->lqIdx; 5334032Sktlim@umich.edu incrLdIdx(load_idx); 5344032Sktlim@umich.edu 5358199SAli.Saidi@ARM.com if (checkLoads) 5368199SAli.Saidi@ARM.com return checkViolations(load_idx, inst); 5372292SN/A } 5382292SN/A 5392292SN/A return load_fault; 5402292SN/A} 5412292SN/A 5422292SN/Atemplate <class Impl> 5432292SN/AFault 5442292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 5452292SN/A{ 5462292SN/A using namespace TheISA; 5472292SN/A // Make sure that a store exists. 5482292SN/A assert(stores != 0); 5492292SN/A 5502292SN/A int store_idx = store_inst->sqIdx; 5512292SN/A 5527720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 5537720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 5542292SN/A 5554032Sktlim@umich.edu assert(!store_inst->isSquashed()); 5564032Sktlim@umich.edu 5572292SN/A // Check the recently completed loads to see if any match this store's 5582292SN/A // address. If so, then we have a memory ordering violation. 5592292SN/A int load_idx = store_inst->lqIdx; 5602292SN/A 5612292SN/A Fault store_fault = store_inst->initiateAcc(); 5622292SN/A 5637944SGiacomo.Gabrielli@arm.com if (store_inst->isTranslationDelayed() && 5647944SGiacomo.Gabrielli@arm.com store_fault == NoFault) 5657944SGiacomo.Gabrielli@arm.com return store_fault; 5667944SGiacomo.Gabrielli@arm.com 5677848SAli.Saidi@ARM.com if (store_inst->readPredicate() == false) 5687848SAli.Saidi@ARM.com store_inst->forwardOldRegs(); 5697848SAli.Saidi@ARM.com 5702329SN/A if (storeQueue[store_idx].size == 0) { 5717782Sminkyu.jeong@arm.com DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 5727720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 5732292SN/A 5742292SN/A return store_fault; 5757782Sminkyu.jeong@arm.com } else if (store_inst->readPredicate() == false) { 5767782Sminkyu.jeong@arm.com DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 5777782Sminkyu.jeong@arm.com store_inst->seqNum); 5787782Sminkyu.jeong@arm.com return store_fault; 5792292SN/A } 5802292SN/A 5812292SN/A assert(store_fault == NoFault); 5822292SN/A 5832336SN/A if (store_inst->isStoreConditional()) { 5842336SN/A // Store conditionals need to set themselves as able to 5852336SN/A // writeback if we haven't had a fault by here. 5862329SN/A storeQueue[store_idx].canWB = true; 5872292SN/A 5882329SN/A ++storesToWB; 5892292SN/A } 5902292SN/A 5918199SAli.Saidi@ARM.com return checkViolations(load_idx, store_inst); 5922292SN/A 5932292SN/A} 5942292SN/A 5952292SN/Atemplate <class Impl> 5962292SN/Avoid 5972292SN/ALSQUnit<Impl>::commitLoad() 5982292SN/A{ 5992292SN/A assert(loadQueue[loadHead]); 6002292SN/A 6017720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 6027720Sgblack@eecs.umich.edu loadQueue[loadHead]->pcState()); 6032292SN/A 6042292SN/A loadQueue[loadHead] = NULL; 6052292SN/A 6062292SN/A incrLdIdx(loadHead); 6072292SN/A 6082292SN/A --loads; 6092292SN/A} 6102292SN/A 6112292SN/Atemplate <class Impl> 6122292SN/Avoid 6132292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 6142292SN/A{ 6152292SN/A assert(loads == 0 || loadQueue[loadHead]); 6162292SN/A 6172292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 6182292SN/A commitLoad(); 6192292SN/A } 6202292SN/A} 6212292SN/A 6222292SN/Atemplate <class Impl> 6232292SN/Avoid 6242292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 6252292SN/A{ 6262292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 6272292SN/A 6282292SN/A int store_idx = storeHead; 6292292SN/A 6302292SN/A while (store_idx != storeTail) { 6312292SN/A assert(storeQueue[store_idx].inst); 6322329SN/A // Mark any stores that are now committed and have not yet 6332329SN/A // been marked as able to write back. 6342292SN/A if (!storeQueue[store_idx].canWB) { 6352292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 6362292SN/A break; 6372292SN/A } 6382292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 6397720Sgblack@eecs.umich.edu "%s [sn:%lli]\n", 6407720Sgblack@eecs.umich.edu storeQueue[store_idx].inst->pcState(), 6412292SN/A storeQueue[store_idx].inst->seqNum); 6422292SN/A 6432292SN/A storeQueue[store_idx].canWB = true; 6442292SN/A 6452292SN/A ++storesToWB; 6462292SN/A } 6472292SN/A 6482292SN/A incrStIdx(store_idx); 6492292SN/A } 6502292SN/A} 6512292SN/A 6522292SN/Atemplate <class Impl> 6532292SN/Avoid 6546974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::writebackPendingStore() 6556974Stjones1@inf.ed.ac.uk{ 6566974Stjones1@inf.ed.ac.uk if (hasPendingPkt) { 6576974Stjones1@inf.ed.ac.uk assert(pendingPkt != NULL); 6586974Stjones1@inf.ed.ac.uk 6596974Stjones1@inf.ed.ac.uk // If the cache is blocked, this will store the packet for retry. 6606974Stjones1@inf.ed.ac.uk if (sendStore(pendingPkt)) { 6616974Stjones1@inf.ed.ac.uk storePostSend(pendingPkt); 6626974Stjones1@inf.ed.ac.uk } 6636974Stjones1@inf.ed.ac.uk pendingPkt = NULL; 6646974Stjones1@inf.ed.ac.uk hasPendingPkt = false; 6656974Stjones1@inf.ed.ac.uk } 6666974Stjones1@inf.ed.ac.uk} 6676974Stjones1@inf.ed.ac.uk 6686974Stjones1@inf.ed.ac.uktemplate <class Impl> 6696974Stjones1@inf.ed.ac.ukvoid 6702292SN/ALSQUnit<Impl>::writebackStores() 6712292SN/A{ 6726974Stjones1@inf.ed.ac.uk // First writeback the second packet from any split store that didn't 6736974Stjones1@inf.ed.ac.uk // complete last cycle because there weren't enough cache ports available. 6746974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc) { 6756974Stjones1@inf.ed.ac.uk writebackPendingStore(); 6766974Stjones1@inf.ed.ac.uk } 6776974Stjones1@inf.ed.ac.uk 6782292SN/A while (storesToWB > 0 && 6792292SN/A storeWBIdx != storeTail && 6802292SN/A storeQueue[storeWBIdx].inst && 6812292SN/A storeQueue[storeWBIdx].canWB && 6822292SN/A usedPorts < cachePorts) { 6832292SN/A 6842907Sktlim@umich.edu if (isStoreBlocked || lsq->cacheBlocked()) { 6852678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 6862678Sktlim@umich.edu " is blocked!\n"); 6872678Sktlim@umich.edu break; 6882678Sktlim@umich.edu } 6892678Sktlim@umich.edu 6902329SN/A // Store didn't write any data so no need to write it back to 6912329SN/A // memory. 6922292SN/A if (storeQueue[storeWBIdx].size == 0) { 6932292SN/A completeStore(storeWBIdx); 6942292SN/A 6952292SN/A incrStIdx(storeWBIdx); 6962292SN/A 6972292SN/A continue; 6982292SN/A } 6992678Sktlim@umich.edu 7002292SN/A ++usedPorts; 7012292SN/A 7022292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 7032292SN/A incrStIdx(storeWBIdx); 7042292SN/A 7052292SN/A continue; 7062292SN/A } 7072292SN/A 7082292SN/A assert(storeQueue[storeWBIdx].req); 7092292SN/A assert(!storeQueue[storeWBIdx].committed); 7102292SN/A 7116974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 7126974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqLow); 7136974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqHigh); 7146974Stjones1@inf.ed.ac.uk } 7156974Stjones1@inf.ed.ac.uk 7162669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 7172669Sktlim@umich.edu 7182669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 7192292SN/A storeQueue[storeWBIdx].committed = true; 7202292SN/A 7212669Sktlim@umich.edu assert(!inst->memData); 7222669Sktlim@umich.edu inst->memData = new uint8_t[64]; 7233772Sgblack@eecs.umich.edu 7244326Sgblack@eecs.umich.edu memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 7252669Sktlim@umich.edu 7264878Sstever@eecs.umich.edu MemCmd command = 7274878Sstever@eecs.umich.edu req->isSwap() ? MemCmd::SwapReq : 7286102Sgblack@eecs.umich.edu (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 7296974Stjones1@inf.ed.ac.uk PacketPtr data_pkt; 7306974Stjones1@inf.ed.ac.uk PacketPtr snd_data_pkt = NULL; 7312292SN/A 7322678Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 7332678Sktlim@umich.edu state->isLoad = false; 7342678Sktlim@umich.edu state->idx = storeWBIdx; 7352678Sktlim@umich.edu state->inst = inst; 7366974Stjones1@inf.ed.ac.uk 7376974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 7386974Stjones1@inf.ed.ac.uk 7396974Stjones1@inf.ed.ac.uk // Build a single data packet if the store isn't split. 7406974Stjones1@inf.ed.ac.uk data_pkt = new Packet(req, command, Packet::Broadcast); 7416974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 7426974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 7436974Stjones1@inf.ed.ac.uk } else { 7446974Stjones1@inf.ed.ac.uk RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 7456974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 7466974Stjones1@inf.ed.ac.uk 7476974Stjones1@inf.ed.ac.uk // Create two packets if the store is split in two. 7486974Stjones1@inf.ed.ac.uk data_pkt = new Packet(sreqLow, command, Packet::Broadcast); 7496974Stjones1@inf.ed.ac.uk snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast); 7506974Stjones1@inf.ed.ac.uk 7516974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 7526974Stjones1@inf.ed.ac.uk snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 7536974Stjones1@inf.ed.ac.uk 7546974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 7556974Stjones1@inf.ed.ac.uk snd_data_pkt->senderState = state; 7566974Stjones1@inf.ed.ac.uk 7576974Stjones1@inf.ed.ac.uk state->isSplit = true; 7586974Stjones1@inf.ed.ac.uk state->outstanding = 2; 7596974Stjones1@inf.ed.ac.uk 7606974Stjones1@inf.ed.ac.uk // Can delete the main request now. 7616974Stjones1@inf.ed.ac.uk delete req; 7626974Stjones1@inf.ed.ac.uk req = sreqLow; 7636974Stjones1@inf.ed.ac.uk } 7642678Sktlim@umich.edu 7657720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 7662292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 7677720Sgblack@eecs.umich.edu storeWBIdx, inst->pcState(), 7683797Sgblack@eecs.umich.edu req->getPaddr(), (int)*(inst->memData), 7693221Sktlim@umich.edu inst->seqNum); 7702292SN/A 7712693Sktlim@umich.edu // @todo: Remove this SC hack once the memory system handles it. 7724350Sgblack@eecs.umich.edu if (inst->isStoreConditional()) { 7736974Stjones1@inf.ed.ac.uk assert(!storeQueue[storeWBIdx].isSplit); 7743326Sktlim@umich.edu // Disable recording the result temporarily. Writing to 7753326Sktlim@umich.edu // misc regs normally updates the result, but this is not 7763326Sktlim@umich.edu // the desired behavior when handling store conditionals. 7773326Sktlim@umich.edu inst->recordResult = false; 7783326Sktlim@umich.edu bool success = TheISA::handleLockedWrite(inst.get(), req); 7793326Sktlim@umich.edu inst->recordResult = true; 7803326Sktlim@umich.edu 7813326Sktlim@umich.edu if (!success) { 7823326Sktlim@umich.edu // Instantly complete this store. 7833326Sktlim@umich.edu DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 7843326Sktlim@umich.edu "Instantly completing it.\n", 7853326Sktlim@umich.edu inst->seqNum); 7863326Sktlim@umich.edu WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 7877823Ssteve.reinhardt@amd.com cpu->schedule(wb, curTick() + 1); 7883326Sktlim@umich.edu completeStore(storeWBIdx); 7893326Sktlim@umich.edu incrStIdx(storeWBIdx); 7903326Sktlim@umich.edu continue; 7912693Sktlim@umich.edu } 7922693Sktlim@umich.edu } else { 7932693Sktlim@umich.edu // Non-store conditionals do not need a writeback. 7942693Sktlim@umich.edu state->noWB = true; 7952693Sktlim@umich.edu } 7962693Sktlim@umich.edu 7976974Stjones1@inf.ed.ac.uk if (!sendStore(data_pkt)) { 7984032Sktlim@umich.edu DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 7993221Sktlim@umich.edu "retry later\n", 8003221Sktlim@umich.edu inst->seqNum); 8016974Stjones1@inf.ed.ac.uk 8026974Stjones1@inf.ed.ac.uk // Need to store the second packet, if split. 8036974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 8046974Stjones1@inf.ed.ac.uk state->pktToSend = true; 8056974Stjones1@inf.ed.ac.uk state->pendingPacket = snd_data_pkt; 8066974Stjones1@inf.ed.ac.uk } 8072669Sktlim@umich.edu } else { 8086974Stjones1@inf.ed.ac.uk 8096974Stjones1@inf.ed.ac.uk // If split, try to send the second packet too 8106974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 8116974Stjones1@inf.ed.ac.uk assert(snd_data_pkt); 8126974Stjones1@inf.ed.ac.uk 8136974Stjones1@inf.ed.ac.uk // Ensure there are enough ports to use. 8146974Stjones1@inf.ed.ac.uk if (usedPorts < cachePorts) { 8156974Stjones1@inf.ed.ac.uk ++usedPorts; 8166974Stjones1@inf.ed.ac.uk if (sendStore(snd_data_pkt)) { 8176974Stjones1@inf.ed.ac.uk storePostSend(snd_data_pkt); 8186974Stjones1@inf.ed.ac.uk } else { 8196974Stjones1@inf.ed.ac.uk DPRINTF(IEW, "D-Cache became blocked when writing" 8206974Stjones1@inf.ed.ac.uk " [sn:%lli] second packet, will retry later\n", 8216974Stjones1@inf.ed.ac.uk inst->seqNum); 8226974Stjones1@inf.ed.ac.uk } 8236974Stjones1@inf.ed.ac.uk } else { 8246974Stjones1@inf.ed.ac.uk 8256974Stjones1@inf.ed.ac.uk // Store the packet for when there's free ports. 8266974Stjones1@inf.ed.ac.uk assert(pendingPkt == NULL); 8276974Stjones1@inf.ed.ac.uk pendingPkt = snd_data_pkt; 8286974Stjones1@inf.ed.ac.uk hasPendingPkt = true; 8296974Stjones1@inf.ed.ac.uk } 8306974Stjones1@inf.ed.ac.uk } else { 8316974Stjones1@inf.ed.ac.uk 8326974Stjones1@inf.ed.ac.uk // Not a split store. 8336974Stjones1@inf.ed.ac.uk storePostSend(data_pkt); 8346974Stjones1@inf.ed.ac.uk } 8352292SN/A } 8362292SN/A } 8372292SN/A 8382292SN/A // Not sure this should set it to 0. 8392292SN/A usedPorts = 0; 8402292SN/A 8412292SN/A assert(stores >= 0 && storesToWB >= 0); 8422292SN/A} 8432292SN/A 8442292SN/A/*template <class Impl> 8452292SN/Avoid 8462292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 8472292SN/A{ 8482292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 8492292SN/A mshrSeqNums.end(), 8502292SN/A seqNum); 8512292SN/A 8522292SN/A if (mshr_it != mshrSeqNums.end()) { 8532292SN/A mshrSeqNums.erase(mshr_it); 8542292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 8552292SN/A } 8562292SN/A}*/ 8572292SN/A 8582292SN/Atemplate <class Impl> 8592292SN/Avoid 8602292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 8612292SN/A{ 8622292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 8632329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 8642292SN/A 8652292SN/A int load_idx = loadTail; 8662292SN/A decrLdIdx(load_idx); 8672292SN/A 8682292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 8697720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 8702292SN/A "[sn:%lli]\n", 8717720Sgblack@eecs.umich.edu loadQueue[load_idx]->pcState(), 8722292SN/A loadQueue[load_idx]->seqNum); 8732292SN/A 8742292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 8752292SN/A stalled = false; 8762292SN/A stallingStoreIsn = 0; 8772292SN/A stallingLoadIdx = 0; 8782292SN/A } 8792292SN/A 8802329SN/A // Clear the smart pointer to make sure it is decremented. 8812731Sktlim@umich.edu loadQueue[load_idx]->setSquashed(); 8822292SN/A loadQueue[load_idx] = NULL; 8832292SN/A --loads; 8842292SN/A 8852292SN/A // Inefficient! 8862292SN/A loadTail = load_idx; 8872292SN/A 8882292SN/A decrLdIdx(load_idx); 8892727Sktlim@umich.edu ++lsqSquashedLoads; 8902292SN/A } 8912292SN/A 8922292SN/A if (isLoadBlocked) { 8932292SN/A if (squashed_num < blockedLoadSeqNum) { 8942292SN/A isLoadBlocked = false; 8952292SN/A loadBlockedHandled = false; 8962292SN/A blockedLoadSeqNum = 0; 8972292SN/A } 8982292SN/A } 8992292SN/A 9004032Sktlim@umich.edu if (memDepViolator && squashed_num < memDepViolator->seqNum) { 9014032Sktlim@umich.edu memDepViolator = NULL; 9024032Sktlim@umich.edu } 9034032Sktlim@umich.edu 9042292SN/A int store_idx = storeTail; 9052292SN/A decrStIdx(store_idx); 9062292SN/A 9072292SN/A while (stores != 0 && 9082292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 9092329SN/A // Instructions marked as can WB are already committed. 9102292SN/A if (storeQueue[store_idx].canWB) { 9112292SN/A break; 9122292SN/A } 9132292SN/A 9147720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 9152292SN/A "idx:%i [sn:%lli]\n", 9167720Sgblack@eecs.umich.edu storeQueue[store_idx].inst->pcState(), 9172292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 9182292SN/A 9192329SN/A // I don't think this can happen. It should have been cleared 9202329SN/A // by the stalling load. 9212292SN/A if (isStalled() && 9222292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 9232292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 9242292SN/A stalled = false; 9252292SN/A stallingStoreIsn = 0; 9262292SN/A } 9272292SN/A 9282329SN/A // Clear the smart pointer to make sure it is decremented. 9292731Sktlim@umich.edu storeQueue[store_idx].inst->setSquashed(); 9302292SN/A storeQueue[store_idx].inst = NULL; 9312292SN/A storeQueue[store_idx].canWB = 0; 9322292SN/A 9334032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 9344032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the proper 9354032Sktlim@umich.edu // place to really handle request deletes. 9364032Sktlim@umich.edu delete storeQueue[store_idx].req; 9376974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 9386974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqLow; 9396974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqHigh; 9406974Stjones1@inf.ed.ac.uk 9416974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqLow = NULL; 9426974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqHigh = NULL; 9436974Stjones1@inf.ed.ac.uk } 9444032Sktlim@umich.edu 9452292SN/A storeQueue[store_idx].req = NULL; 9462292SN/A --stores; 9472292SN/A 9482292SN/A // Inefficient! 9492292SN/A storeTail = store_idx; 9502292SN/A 9512292SN/A decrStIdx(store_idx); 9522727Sktlim@umich.edu ++lsqSquashedStores; 9532292SN/A } 9542292SN/A} 9552292SN/A 9562292SN/Atemplate <class Impl> 9572292SN/Avoid 9583349Sbinkertn@umich.eduLSQUnit<Impl>::storePostSend(PacketPtr pkt) 9592693Sktlim@umich.edu{ 9602693Sktlim@umich.edu if (isStalled() && 9612693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 9622693Sktlim@umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 9632693Sktlim@umich.edu "load idx:%i\n", 9642693Sktlim@umich.edu stallingStoreIsn, stallingLoadIdx); 9652693Sktlim@umich.edu stalled = false; 9662693Sktlim@umich.edu stallingStoreIsn = 0; 9672693Sktlim@umich.edu iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 9682693Sktlim@umich.edu } 9692693Sktlim@umich.edu 9702693Sktlim@umich.edu if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 9712693Sktlim@umich.edu // The store is basically completed at this time. This 9722693Sktlim@umich.edu // only works so long as the checker doesn't try to 9732693Sktlim@umich.edu // verify the value in memory for stores. 9742693Sktlim@umich.edu storeQueue[storeWBIdx].inst->setCompleted(); 9752733Sktlim@umich.edu#if USE_CHECKER 9762693Sktlim@umich.edu if (cpu->checker) { 9772732Sktlim@umich.edu cpu->checker->verify(storeQueue[storeWBIdx].inst); 9782693Sktlim@umich.edu } 9792733Sktlim@umich.edu#endif 9802693Sktlim@umich.edu } 9812693Sktlim@umich.edu 9822693Sktlim@umich.edu incrStIdx(storeWBIdx); 9832693Sktlim@umich.edu} 9842693Sktlim@umich.edu 9852693Sktlim@umich.edutemplate <class Impl> 9862693Sktlim@umich.eduvoid 9872678Sktlim@umich.eduLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 9882678Sktlim@umich.edu{ 9892678Sktlim@umich.edu iewStage->wakeCPU(); 9902678Sktlim@umich.edu 9912678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 9922678Sktlim@umich.edu if (inst->isSquashed()) { 9932927Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 9942678Sktlim@umich.edu assert(!inst->isStore()); 9952727Sktlim@umich.edu ++lsqIgnoredResponses; 9962678Sktlim@umich.edu return; 9972678Sktlim@umich.edu } 9982678Sktlim@umich.edu 9992678Sktlim@umich.edu if (!inst->isExecuted()) { 10002678Sktlim@umich.edu inst->setExecuted(); 10012678Sktlim@umich.edu 10022678Sktlim@umich.edu // Complete access to copy data to proper place. 10032678Sktlim@umich.edu inst->completeAcc(pkt); 10042678Sktlim@umich.edu } 10052678Sktlim@umich.edu 10062678Sktlim@umich.edu // Need to insert instruction into queue to commit 10072678Sktlim@umich.edu iewStage->instToCommit(inst); 10082678Sktlim@umich.edu 10092678Sktlim@umich.edu iewStage->activityThisCycle(); 10107598Sminkyu.jeong@arm.com 10117598Sminkyu.jeong@arm.com // see if this load changed the PC 10127598Sminkyu.jeong@arm.com iewStage->checkMisprediction(inst); 10132678Sktlim@umich.edu} 10142678Sktlim@umich.edu 10152678Sktlim@umich.edutemplate <class Impl> 10162678Sktlim@umich.eduvoid 10172292SN/ALSQUnit<Impl>::completeStore(int store_idx) 10182292SN/A{ 10192292SN/A assert(storeQueue[store_idx].inst); 10202292SN/A storeQueue[store_idx].completed = true; 10212292SN/A --storesToWB; 10222292SN/A // A bit conservative because a store completion may not free up entries, 10232292SN/A // but hopefully avoids two store completions in one cycle from making 10242292SN/A // the CPU tick twice. 10253126Sktlim@umich.edu cpu->wakeCPU(); 10262292SN/A cpu->activityThisCycle(); 10272292SN/A 10282292SN/A if (store_idx == storeHead) { 10292292SN/A do { 10302292SN/A incrStIdx(storeHead); 10312292SN/A 10322292SN/A --stores; 10332292SN/A } while (storeQueue[storeHead].completed && 10342292SN/A storeHead != storeTail); 10352292SN/A 10362292SN/A iewStage->updateLSQNextCycle = true; 10372292SN/A } 10382292SN/A 10392329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 10402329SN/A "idx:%i\n", 10412329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 10422292SN/A 10432292SN/A if (isStalled() && 10442292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 10452292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 10462292SN/A "load idx:%i\n", 10472292SN/A stallingStoreIsn, stallingLoadIdx); 10482292SN/A stalled = false; 10492292SN/A stallingStoreIsn = 0; 10502292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 10512292SN/A } 10522316SN/A 10532316SN/A storeQueue[store_idx].inst->setCompleted(); 10542329SN/A 10552329SN/A // Tell the checker we've completed this instruction. Some stores 10562329SN/A // may get reported twice to the checker, but the checker can 10572329SN/A // handle that case. 10582733Sktlim@umich.edu#if USE_CHECKER 10592316SN/A if (cpu->checker) { 10602732Sktlim@umich.edu cpu->checker->verify(storeQueue[store_idx].inst); 10612316SN/A } 10622733Sktlim@umich.edu#endif 10632292SN/A} 10642292SN/A 10652292SN/Atemplate <class Impl> 10666974Stjones1@inf.ed.ac.ukbool 10676974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::sendStore(PacketPtr data_pkt) 10686974Stjones1@inf.ed.ac.uk{ 10696974Stjones1@inf.ed.ac.uk if (!dcachePort->sendTiming(data_pkt)) { 10706974Stjones1@inf.ed.ac.uk // Need to handle becoming blocked on a store. 10716974Stjones1@inf.ed.ac.uk isStoreBlocked = true; 10726974Stjones1@inf.ed.ac.uk ++lsqCacheBlocked; 10736974Stjones1@inf.ed.ac.uk assert(retryPkt == NULL); 10746974Stjones1@inf.ed.ac.uk retryPkt = data_pkt; 10756974Stjones1@inf.ed.ac.uk lsq->setRetryTid(lsqID); 10766974Stjones1@inf.ed.ac.uk return false; 10776974Stjones1@inf.ed.ac.uk } 10786974Stjones1@inf.ed.ac.uk return true; 10796974Stjones1@inf.ed.ac.uk} 10806974Stjones1@inf.ed.ac.uk 10816974Stjones1@inf.ed.ac.uktemplate <class Impl> 10822693Sktlim@umich.eduvoid 10832693Sktlim@umich.eduLSQUnit<Impl>::recvRetry() 10842693Sktlim@umich.edu{ 10852698Sktlim@umich.edu if (isStoreBlocked) { 10864985Sktlim@umich.edu DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 10872698Sktlim@umich.edu assert(retryPkt != NULL); 10882693Sktlim@umich.edu 10892698Sktlim@umich.edu if (dcachePort->sendTiming(retryPkt)) { 10906974Stjones1@inf.ed.ac.uk LSQSenderState *state = 10916974Stjones1@inf.ed.ac.uk dynamic_cast<LSQSenderState *>(retryPkt->senderState); 10926974Stjones1@inf.ed.ac.uk 10936974Stjones1@inf.ed.ac.uk // Don't finish the store unless this is the last packet. 10948133SAli.Saidi@ARM.com if (!TheISA::HasUnalignedMemAcc || !state->pktToSend || 10958133SAli.Saidi@ARM.com state->pendingPacket == retryPkt) { 10968133SAli.Saidi@ARM.com state->pktToSend = false; 10976974Stjones1@inf.ed.ac.uk storePostSend(retryPkt); 10986974Stjones1@inf.ed.ac.uk } 10992699Sktlim@umich.edu retryPkt = NULL; 11002693Sktlim@umich.edu isStoreBlocked = false; 11016221Snate@binkert.org lsq->setRetryTid(InvalidThreadID); 11026974Stjones1@inf.ed.ac.uk 11036974Stjones1@inf.ed.ac.uk // Send any outstanding packet. 11046974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 11056974Stjones1@inf.ed.ac.uk assert(state->pendingPacket); 11066974Stjones1@inf.ed.ac.uk if (sendStore(state->pendingPacket)) { 11076974Stjones1@inf.ed.ac.uk storePostSend(state->pendingPacket); 11086974Stjones1@inf.ed.ac.uk } 11096974Stjones1@inf.ed.ac.uk } 11102693Sktlim@umich.edu } else { 11112693Sktlim@umich.edu // Still blocked! 11122727Sktlim@umich.edu ++lsqCacheBlocked; 11132907Sktlim@umich.edu lsq->setRetryTid(lsqID); 11142693Sktlim@umich.edu } 11152693Sktlim@umich.edu } else if (isLoadBlocked) { 11162693Sktlim@umich.edu DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 11172693Sktlim@umich.edu "no need to resend packet.\n"); 11182693Sktlim@umich.edu } else { 11192693Sktlim@umich.edu DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 11202693Sktlim@umich.edu } 11212693Sktlim@umich.edu} 11222693Sktlim@umich.edu 11232693Sktlim@umich.edutemplate <class Impl> 11242292SN/Ainline void 11252292SN/ALSQUnit<Impl>::incrStIdx(int &store_idx) 11262292SN/A{ 11272292SN/A if (++store_idx >= SQEntries) 11282292SN/A store_idx = 0; 11292292SN/A} 11302292SN/A 11312292SN/Atemplate <class Impl> 11322292SN/Ainline void 11332292SN/ALSQUnit<Impl>::decrStIdx(int &store_idx) 11342292SN/A{ 11352292SN/A if (--store_idx < 0) 11362292SN/A store_idx += SQEntries; 11372292SN/A} 11382292SN/A 11392292SN/Atemplate <class Impl> 11402292SN/Ainline void 11412292SN/ALSQUnit<Impl>::incrLdIdx(int &load_idx) 11422292SN/A{ 11432292SN/A if (++load_idx >= LQEntries) 11442292SN/A load_idx = 0; 11452292SN/A} 11462292SN/A 11472292SN/Atemplate <class Impl> 11482292SN/Ainline void 11492292SN/ALSQUnit<Impl>::decrLdIdx(int &load_idx) 11502292SN/A{ 11512292SN/A if (--load_idx < 0) 11522292SN/A load_idx += LQEntries; 11532292SN/A} 11542329SN/A 11552329SN/Atemplate <class Impl> 11562329SN/Avoid 11572329SN/ALSQUnit<Impl>::dumpInsts() 11582329SN/A{ 11592329SN/A cprintf("Load store queue: Dumping instructions.\n"); 11602329SN/A cprintf("Load queue size: %i\n", loads); 11612329SN/A cprintf("Load queue: "); 11622329SN/A 11632329SN/A int load_idx = loadHead; 11642329SN/A 11652329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 11667720Sgblack@eecs.umich.edu cprintf("%s ", loadQueue[load_idx]->pcState()); 11672329SN/A 11682329SN/A incrLdIdx(load_idx); 11692329SN/A } 11702329SN/A 11712329SN/A cprintf("Store queue size: %i\n", stores); 11722329SN/A cprintf("Store queue: "); 11732329SN/A 11742329SN/A int store_idx = storeHead; 11752329SN/A 11762329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 11777720Sgblack@eecs.umich.edu cprintf("%s ", storeQueue[store_idx].inst->pcState()); 11782329SN/A 11792329SN/A incrStIdx(store_idx); 11802329SN/A } 11812329SN/A 11822329SN/A cprintf("\n"); 11832329SN/A} 1184