lsq_unit_impl.hh revision 8199
12292SN/A/* 27597Sminkyu.jeong@arm.com * Copyright (c) 2010 ARM Limited 37597Sminkyu.jeong@arm.com * All rights reserved 47597Sminkyu.jeong@arm.com * 57597Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67597Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77597Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87597Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97597Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107597Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117597Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127597Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137597Sminkyu.jeong@arm.com * 142292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 152292SN/A * All rights reserved. 162292SN/A * 172292SN/A * Redistribution and use in source and binary forms, with or without 182292SN/A * modification, are permitted provided that the following conditions are 192292SN/A * met: redistributions of source code must retain the above copyright 202292SN/A * notice, this list of conditions and the following disclaimer; 212292SN/A * redistributions in binary form must reproduce the above copyright 222292SN/A * notice, this list of conditions and the following disclaimer in the 232292SN/A * documentation and/or other materials provided with the distribution; 242292SN/A * neither the name of the copyright holders nor the names of its 252292SN/A * contributors may be used to endorse or promote products derived from 262292SN/A * this software without specific prior written permission. 272292SN/A * 282292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392689Sktlim@umich.edu * 402689Sktlim@umich.edu * Authors: Kevin Lim 412689Sktlim@umich.edu * Korey Sewell 422292SN/A */ 432292SN/A 443326Sktlim@umich.edu#include "arch/locked_mem.hh" 456658Snate@binkert.org#include "config/the_isa.hh" 462733Sktlim@umich.edu#include "config/use_checker.hh" 472907Sktlim@umich.edu#include "cpu/o3/lsq.hh" 482292SN/A#include "cpu/o3/lsq_unit.hh" 492292SN/A#include "base/str.hh" 502722Sktlim@umich.edu#include "mem/packet.hh" 512669Sktlim@umich.edu#include "mem/request.hh" 522292SN/A 532790Sktlim@umich.edu#if USE_CHECKER 542790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 552790Sktlim@umich.edu#endif 562790Sktlim@umich.edu 572669Sktlim@umich.edutemplate<class Impl> 582678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 592678Sktlim@umich.edu LSQUnit *lsq_ptr) 605606Snate@binkert.org : inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 612292SN/A{ 622678Sktlim@umich.edu this->setFlags(Event::AutoDelete); 632292SN/A} 642292SN/A 652669Sktlim@umich.edutemplate<class Impl> 662292SN/Avoid 672678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 682292SN/A{ 692678Sktlim@umich.edu if (!lsqPtr->isSwitchedOut()) { 702678Sktlim@umich.edu lsqPtr->writeback(inst, pkt); 712678Sktlim@umich.edu } 724319Sktlim@umich.edu 734319Sktlim@umich.edu if (pkt->senderState) 744319Sktlim@umich.edu delete pkt->senderState; 754319Sktlim@umich.edu 764319Sktlim@umich.edu delete pkt->req; 772678Sktlim@umich.edu delete pkt; 782678Sktlim@umich.edu} 792292SN/A 802678Sktlim@umich.edutemplate<class Impl> 812678Sktlim@umich.educonst char * 825336Shines@cs.fsu.eduLSQUnit<Impl>::WritebackEvent::description() const 832678Sktlim@umich.edu{ 844873Sstever@eecs.umich.edu return "Store writeback"; 852678Sktlim@umich.edu} 862292SN/A 872678Sktlim@umich.edutemplate<class Impl> 882678Sktlim@umich.eduvoid 892678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 902678Sktlim@umich.edu{ 912678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 922678Sktlim@umich.edu DynInstPtr inst = state->inst; 937852SMatt.Horsnell@arm.com DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum); 947852SMatt.Horsnell@arm.com DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum); 952344SN/A 962678Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 972678Sktlim@umich.edu 984986Ssaidi@eecs.umich.edu assert(!pkt->wasNacked()); 994986Ssaidi@eecs.umich.edu 1006974Stjones1@inf.ed.ac.uk // If this is a split access, wait until all packets are received. 1016974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && !state->complete()) { 1026974Stjones1@inf.ed.ac.uk delete pkt->req; 1036974Stjones1@inf.ed.ac.uk delete pkt; 1046974Stjones1@inf.ed.ac.uk return; 1056974Stjones1@inf.ed.ac.uk } 1066974Stjones1@inf.ed.ac.uk 1072678Sktlim@umich.edu if (isSwitchedOut() || inst->isSquashed()) { 1082820Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 1092678Sktlim@umich.edu } else { 1102678Sktlim@umich.edu if (!state->noWB) { 1116974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 1126974Stjones1@inf.ed.ac.uk !state->isLoad) { 1136974Stjones1@inf.ed.ac.uk writeback(inst, pkt); 1146974Stjones1@inf.ed.ac.uk } else { 1156974Stjones1@inf.ed.ac.uk writeback(inst, state->mainPkt); 1166974Stjones1@inf.ed.ac.uk } 1172678Sktlim@umich.edu } 1182678Sktlim@umich.edu 1192678Sktlim@umich.edu if (inst->isStore()) { 1202678Sktlim@umich.edu completeStore(state->idx); 1212678Sktlim@umich.edu } 1222344SN/A } 1232307SN/A 1246974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 1256974Stjones1@inf.ed.ac.uk delete state->mainPkt->req; 1266974Stjones1@inf.ed.ac.uk delete state->mainPkt; 1276974Stjones1@inf.ed.ac.uk } 1282678Sktlim@umich.edu delete state; 1294032Sktlim@umich.edu delete pkt->req; 1302678Sktlim@umich.edu delete pkt; 1312292SN/A} 1322292SN/A 1332292SN/Atemplate <class Impl> 1342292SN/ALSQUnit<Impl>::LSQUnit() 1352678Sktlim@umich.edu : loads(0), stores(0), storesToWB(0), stalled(false), 1362678Sktlim@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1376974Stjones1@inf.ed.ac.uk loadBlockedHandled(false), hasPendingPkt(false) 1382292SN/A{ 1392292SN/A} 1402292SN/A 1412292SN/Atemplate<class Impl> 1422292SN/Avoid 1435529Snate@binkert.orgLSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 1445529Snate@binkert.org LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 1455529Snate@binkert.org unsigned id) 1462292SN/A{ 1474329Sktlim@umich.edu cpu = cpu_ptr; 1484329Sktlim@umich.edu iewStage = iew_ptr; 1494329Sktlim@umich.edu 1504329Sktlim@umich.edu DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1512292SN/A 1522307SN/A switchedOut = false; 1532307SN/A 1542907Sktlim@umich.edu lsq = lsq_ptr; 1552907Sktlim@umich.edu 1562292SN/A lsqID = id; 1572292SN/A 1582329SN/A // Add 1 for the sentinel entry (they are circular queues). 1592329SN/A LQEntries = maxLQEntries + 1; 1602329SN/A SQEntries = maxSQEntries + 1; 1612292SN/A 1622292SN/A loadQueue.resize(LQEntries); 1632292SN/A storeQueue.resize(SQEntries); 1642292SN/A 1658199SAli.Saidi@ARM.com depCheckShift = params->LSQDepCheckShift; 1668199SAli.Saidi@ARM.com checkLoads = params->LSQCheckLoads; 1678199SAli.Saidi@ARM.com 1682292SN/A loadHead = loadTail = 0; 1692292SN/A 1702292SN/A storeHead = storeWBIdx = storeTail = 0; 1712292SN/A 1722292SN/A usedPorts = 0; 1732292SN/A cachePorts = params->cachePorts; 1742292SN/A 1753492Sktlim@umich.edu retryPkt = NULL; 1762329SN/A memDepViolator = NULL; 1772292SN/A 1782292SN/A blockedLoadSeqNum = 0; 1792292SN/A} 1802292SN/A 1812292SN/Atemplate<class Impl> 1822292SN/Astd::string 1832292SN/ALSQUnit<Impl>::name() const 1842292SN/A{ 1852292SN/A if (Impl::MaxThreads == 1) { 1862292SN/A return iewStage->name() + ".lsq"; 1872292SN/A } else { 1882292SN/A return iewStage->name() + ".lsq.thread." + to_string(lsqID); 1892292SN/A } 1902292SN/A} 1912292SN/A 1922292SN/Atemplate<class Impl> 1932292SN/Avoid 1942727Sktlim@umich.eduLSQUnit<Impl>::regStats() 1952727Sktlim@umich.edu{ 1962727Sktlim@umich.edu lsqForwLoads 1972727Sktlim@umich.edu .name(name() + ".forwLoads") 1982727Sktlim@umich.edu .desc("Number of loads that had data forwarded from stores"); 1992727Sktlim@umich.edu 2002727Sktlim@umich.edu invAddrLoads 2012727Sktlim@umich.edu .name(name() + ".invAddrLoads") 2022727Sktlim@umich.edu .desc("Number of loads ignored due to an invalid address"); 2032727Sktlim@umich.edu 2042727Sktlim@umich.edu lsqSquashedLoads 2052727Sktlim@umich.edu .name(name() + ".squashedLoads") 2062727Sktlim@umich.edu .desc("Number of loads squashed"); 2072727Sktlim@umich.edu 2082727Sktlim@umich.edu lsqIgnoredResponses 2092727Sktlim@umich.edu .name(name() + ".ignoredResponses") 2102727Sktlim@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 2112727Sktlim@umich.edu 2122361SN/A lsqMemOrderViolation 2132361SN/A .name(name() + ".memOrderViolation") 2142361SN/A .desc("Number of memory ordering violations"); 2152361SN/A 2162727Sktlim@umich.edu lsqSquashedStores 2172727Sktlim@umich.edu .name(name() + ".squashedStores") 2182727Sktlim@umich.edu .desc("Number of stores squashed"); 2192727Sktlim@umich.edu 2202727Sktlim@umich.edu invAddrSwpfs 2212727Sktlim@umich.edu .name(name() + ".invAddrSwpfs") 2222727Sktlim@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 2232727Sktlim@umich.edu 2242727Sktlim@umich.edu lsqBlockedLoads 2252727Sktlim@umich.edu .name(name() + ".blockedLoads") 2262727Sktlim@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 2272727Sktlim@umich.edu 2282727Sktlim@umich.edu lsqRescheduledLoads 2292727Sktlim@umich.edu .name(name() + ".rescheduledLoads") 2302727Sktlim@umich.edu .desc("Number of loads that were rescheduled"); 2312727Sktlim@umich.edu 2322727Sktlim@umich.edu lsqCacheBlocked 2332727Sktlim@umich.edu .name(name() + ".cacheBlocked") 2342727Sktlim@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2352727Sktlim@umich.edu} 2362727Sktlim@umich.edu 2372727Sktlim@umich.edutemplate<class Impl> 2382727Sktlim@umich.eduvoid 2394329Sktlim@umich.eduLSQUnit<Impl>::setDcachePort(Port *dcache_port) 2404329Sktlim@umich.edu{ 2414329Sktlim@umich.edu dcachePort = dcache_port; 2424329Sktlim@umich.edu 2434329Sktlim@umich.edu#if USE_CHECKER 2444329Sktlim@umich.edu if (cpu->checker) { 2454329Sktlim@umich.edu cpu->checker->setDcachePort(dcachePort); 2464329Sktlim@umich.edu } 2474329Sktlim@umich.edu#endif 2484329Sktlim@umich.edu} 2494329Sktlim@umich.edu 2504329Sktlim@umich.edutemplate<class Impl> 2514329Sktlim@umich.eduvoid 2522292SN/ALSQUnit<Impl>::clearLQ() 2532292SN/A{ 2542292SN/A loadQueue.clear(); 2552292SN/A} 2562292SN/A 2572292SN/Atemplate<class Impl> 2582292SN/Avoid 2592292SN/ALSQUnit<Impl>::clearSQ() 2602292SN/A{ 2612292SN/A storeQueue.clear(); 2622292SN/A} 2632292SN/A 2642292SN/Atemplate<class Impl> 2652292SN/Avoid 2662307SN/ALSQUnit<Impl>::switchOut() 2672307SN/A{ 2682307SN/A switchedOut = true; 2692367SN/A for (int i = 0; i < loadQueue.size(); ++i) { 2702367SN/A assert(!loadQueue[i]); 2712307SN/A loadQueue[i] = NULL; 2722367SN/A } 2732307SN/A 2742329SN/A assert(storesToWB == 0); 2752307SN/A} 2762307SN/A 2772307SN/Atemplate<class Impl> 2782307SN/Avoid 2792307SN/ALSQUnit<Impl>::takeOverFrom() 2802307SN/A{ 2812307SN/A switchedOut = false; 2822307SN/A loads = stores = storesToWB = 0; 2832307SN/A 2842307SN/A loadHead = loadTail = 0; 2852307SN/A 2862307SN/A storeHead = storeWBIdx = storeTail = 0; 2872307SN/A 2882307SN/A usedPorts = 0; 2892307SN/A 2902329SN/A memDepViolator = NULL; 2912307SN/A 2922307SN/A blockedLoadSeqNum = 0; 2932307SN/A 2942307SN/A stalled = false; 2952307SN/A isLoadBlocked = false; 2962307SN/A loadBlockedHandled = false; 2972307SN/A} 2982307SN/A 2992307SN/Atemplate<class Impl> 3002307SN/Avoid 3012292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 3022292SN/A{ 3032329SN/A unsigned size_plus_sentinel = size + 1; 3042329SN/A assert(size_plus_sentinel >= LQEntries); 3052292SN/A 3062329SN/A if (size_plus_sentinel > LQEntries) { 3072329SN/A while (size_plus_sentinel > loadQueue.size()) { 3082292SN/A DynInstPtr dummy; 3092292SN/A loadQueue.push_back(dummy); 3102292SN/A LQEntries++; 3112292SN/A } 3122292SN/A } else { 3132329SN/A LQEntries = size_plus_sentinel; 3142292SN/A } 3152292SN/A 3162292SN/A} 3172292SN/A 3182292SN/Atemplate<class Impl> 3192292SN/Avoid 3202292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 3212292SN/A{ 3222329SN/A unsigned size_plus_sentinel = size + 1; 3232329SN/A if (size_plus_sentinel > SQEntries) { 3242329SN/A while (size_plus_sentinel > storeQueue.size()) { 3252292SN/A SQEntry dummy; 3262292SN/A storeQueue.push_back(dummy); 3272292SN/A SQEntries++; 3282292SN/A } 3292292SN/A } else { 3302329SN/A SQEntries = size_plus_sentinel; 3312292SN/A } 3322292SN/A} 3332292SN/A 3342292SN/Atemplate <class Impl> 3352292SN/Avoid 3362292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 3372292SN/A{ 3382292SN/A assert(inst->isMemRef()); 3392292SN/A 3402292SN/A assert(inst->isLoad() || inst->isStore()); 3412292SN/A 3422292SN/A if (inst->isLoad()) { 3432292SN/A insertLoad(inst); 3442292SN/A } else { 3452292SN/A insertStore(inst); 3462292SN/A } 3472292SN/A 3482292SN/A inst->setInLSQ(); 3492292SN/A} 3502292SN/A 3512292SN/Atemplate <class Impl> 3522292SN/Avoid 3532292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3542292SN/A{ 3552329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3562329SN/A assert(loads < LQEntries); 3572292SN/A 3587720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 3597720Sgblack@eecs.umich.edu load_inst->pcState(), loadTail, load_inst->seqNum); 3602292SN/A 3612292SN/A load_inst->lqIdx = loadTail; 3622292SN/A 3632292SN/A if (stores == 0) { 3642292SN/A load_inst->sqIdx = -1; 3652292SN/A } else { 3662292SN/A load_inst->sqIdx = storeTail; 3672292SN/A } 3682292SN/A 3692292SN/A loadQueue[loadTail] = load_inst; 3702292SN/A 3712292SN/A incrLdIdx(loadTail); 3722292SN/A 3732292SN/A ++loads; 3742292SN/A} 3752292SN/A 3762292SN/Atemplate <class Impl> 3772292SN/Avoid 3782292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3792292SN/A{ 3802292SN/A // Make sure it is not full before inserting an instruction. 3812292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3822292SN/A assert(stores < SQEntries); 3832292SN/A 3847720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 3857720Sgblack@eecs.umich.edu store_inst->pcState(), storeTail, store_inst->seqNum); 3862292SN/A 3872292SN/A store_inst->sqIdx = storeTail; 3882292SN/A store_inst->lqIdx = loadTail; 3892292SN/A 3902292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3912292SN/A 3922292SN/A incrStIdx(storeTail); 3932292SN/A 3942292SN/A ++stores; 3952292SN/A} 3962292SN/A 3972292SN/Atemplate <class Impl> 3982292SN/Atypename Impl::DynInstPtr 3992292SN/ALSQUnit<Impl>::getMemDepViolator() 4002292SN/A{ 4012292SN/A DynInstPtr temp = memDepViolator; 4022292SN/A 4032292SN/A memDepViolator = NULL; 4042292SN/A 4052292SN/A return temp; 4062292SN/A} 4072292SN/A 4082292SN/Atemplate <class Impl> 4092292SN/Aunsigned 4102292SN/ALSQUnit<Impl>::numFreeEntries() 4112292SN/A{ 4122292SN/A unsigned free_lq_entries = LQEntries - loads; 4132292SN/A unsigned free_sq_entries = SQEntries - stores; 4142292SN/A 4152292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 4162292SN/A // empty/full conditions. Subtract 1 from the free entries. 4172292SN/A if (free_lq_entries < free_sq_entries) { 4182292SN/A return free_lq_entries - 1; 4192292SN/A } else { 4202292SN/A return free_sq_entries - 1; 4212292SN/A } 4222292SN/A} 4232292SN/A 4242292SN/Atemplate <class Impl> 4252292SN/Aint 4262292SN/ALSQUnit<Impl>::numLoadsReady() 4272292SN/A{ 4282292SN/A int load_idx = loadHead; 4292292SN/A int retval = 0; 4302292SN/A 4312292SN/A while (load_idx != loadTail) { 4322292SN/A assert(loadQueue[load_idx]); 4332292SN/A 4342292SN/A if (loadQueue[load_idx]->readyToIssue()) { 4352292SN/A ++retval; 4362292SN/A } 4372292SN/A } 4382292SN/A 4392292SN/A return retval; 4402292SN/A} 4412292SN/A 4422292SN/Atemplate <class Impl> 4432292SN/AFault 4448199SAli.Saidi@ARM.comLSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) 4458199SAli.Saidi@ARM.com{ 4468199SAli.Saidi@ARM.com Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 4478199SAli.Saidi@ARM.com Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 4488199SAli.Saidi@ARM.com 4498199SAli.Saidi@ARM.com /** @todo in theory you only need to check an instruction that has executed 4508199SAli.Saidi@ARM.com * however, there isn't a good way in the pipeline at the moment to check 4518199SAli.Saidi@ARM.com * all instructions that will execute before the store writes back. Thus, 4528199SAli.Saidi@ARM.com * like the implementation that came before it, we're overly conservative. 4538199SAli.Saidi@ARM.com */ 4548199SAli.Saidi@ARM.com while (load_idx != loadTail) { 4558199SAli.Saidi@ARM.com DynInstPtr ld_inst = loadQueue[load_idx]; 4568199SAli.Saidi@ARM.com if (!ld_inst->effAddrValid || ld_inst->uncacheable()) { 4578199SAli.Saidi@ARM.com incrLdIdx(load_idx); 4588199SAli.Saidi@ARM.com continue; 4598199SAli.Saidi@ARM.com } 4608199SAli.Saidi@ARM.com 4618199SAli.Saidi@ARM.com Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 4628199SAli.Saidi@ARM.com Addr ld_eff_addr2 = 4638199SAli.Saidi@ARM.com (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 4648199SAli.Saidi@ARM.com 4658199SAli.Saidi@ARM.com if ((inst_eff_addr2 > ld_eff_addr1 && inst_eff_addr1 < ld_eff_addr2) || 4668199SAli.Saidi@ARM.com inst_eff_addr1 == ld_eff_addr1) { 4678199SAli.Saidi@ARM.com // A load/store incorrectly passed this load/store. 4688199SAli.Saidi@ARM.com // Check if we already have a violator, or if it's newer 4698199SAli.Saidi@ARM.com // squash and refetch. 4708199SAli.Saidi@ARM.com if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 4718199SAli.Saidi@ARM.com break; 4728199SAli.Saidi@ARM.com 4738199SAli.Saidi@ARM.com DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and [sn:%lli]" 4748199SAli.Saidi@ARM.com " at address %#x\n", inst->seqNum, ld_inst->seqNum, 4758199SAli.Saidi@ARM.com ld_eff_addr1); 4768199SAli.Saidi@ARM.com memDepViolator = ld_inst; 4778199SAli.Saidi@ARM.com 4788199SAli.Saidi@ARM.com ++lsqMemOrderViolation; 4798199SAli.Saidi@ARM.com 4808199SAli.Saidi@ARM.com return TheISA::genMachineCheckFault(); 4818199SAli.Saidi@ARM.com } 4828199SAli.Saidi@ARM.com 4838199SAli.Saidi@ARM.com incrLdIdx(load_idx); 4848199SAli.Saidi@ARM.com } 4858199SAli.Saidi@ARM.com return NoFault; 4868199SAli.Saidi@ARM.com} 4878199SAli.Saidi@ARM.com 4888199SAli.Saidi@ARM.com 4898199SAli.Saidi@ARM.com 4908199SAli.Saidi@ARM.com 4918199SAli.Saidi@ARM.comtemplate <class Impl> 4928199SAli.Saidi@ARM.comFault 4932292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 4942292SN/A{ 4954032Sktlim@umich.edu using namespace TheISA; 4962292SN/A // Execute a specific load. 4972292SN/A Fault load_fault = NoFault; 4982292SN/A 4997720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 5007944SGiacomo.Gabrielli@arm.com inst->pcState(), inst->seqNum); 5012292SN/A 5024032Sktlim@umich.edu assert(!inst->isSquashed()); 5034032Sktlim@umich.edu 5042669Sktlim@umich.edu load_fault = inst->initiateAcc(); 5052292SN/A 5067944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 5077944SGiacomo.Gabrielli@arm.com load_fault == NoFault) 5087944SGiacomo.Gabrielli@arm.com return load_fault; 5097944SGiacomo.Gabrielli@arm.com 5107597Sminkyu.jeong@arm.com // If the instruction faulted or predicated false, then we need to send it 5117597Sminkyu.jeong@arm.com // along to commit without the instruction completing. 5127597Sminkyu.jeong@arm.com if (load_fault != NoFault || inst->readPredicate() == false) { 5132329SN/A // Send this instruction to commit, also make sure iew stage 5142329SN/A // realizes there is activity. 5152367SN/A // Mark it as executed unless it is an uncached load that 5162367SN/A // needs to hit the head of commit. 5177848SAli.Saidi@ARM.com if (inst->readPredicate() == false) 5187848SAli.Saidi@ARM.com inst->forwardOldRegs(); 5197600Sminkyu.jeong@arm.com DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 5207600Sminkyu.jeong@arm.com inst->seqNum, 5217600Sminkyu.jeong@arm.com (load_fault != NoFault ? "fault" : "predication")); 5224032Sktlim@umich.edu if (!(inst->hasRequest() && inst->uncacheable()) || 5233731Sktlim@umich.edu inst->isAtCommit()) { 5242367SN/A inst->setExecuted(); 5252367SN/A } 5262292SN/A iewStage->instToCommit(inst); 5272292SN/A iewStage->activityThisCycle(); 5284032Sktlim@umich.edu } else if (!loadBlocked()) { 5294032Sktlim@umich.edu assert(inst->effAddrValid); 5304032Sktlim@umich.edu int load_idx = inst->lqIdx; 5314032Sktlim@umich.edu incrLdIdx(load_idx); 5324032Sktlim@umich.edu 5338199SAli.Saidi@ARM.com if (checkLoads) 5348199SAli.Saidi@ARM.com return checkViolations(load_idx, inst); 5352292SN/A } 5362292SN/A 5372292SN/A return load_fault; 5382292SN/A} 5392292SN/A 5402292SN/Atemplate <class Impl> 5412292SN/AFault 5422292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 5432292SN/A{ 5442292SN/A using namespace TheISA; 5452292SN/A // Make sure that a store exists. 5462292SN/A assert(stores != 0); 5472292SN/A 5482292SN/A int store_idx = store_inst->sqIdx; 5492292SN/A 5507720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 5517720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 5522292SN/A 5534032Sktlim@umich.edu assert(!store_inst->isSquashed()); 5544032Sktlim@umich.edu 5552292SN/A // Check the recently completed loads to see if any match this store's 5562292SN/A // address. If so, then we have a memory ordering violation. 5572292SN/A int load_idx = store_inst->lqIdx; 5582292SN/A 5592292SN/A Fault store_fault = store_inst->initiateAcc(); 5602292SN/A 5617944SGiacomo.Gabrielli@arm.com if (store_inst->isTranslationDelayed() && 5627944SGiacomo.Gabrielli@arm.com store_fault == NoFault) 5637944SGiacomo.Gabrielli@arm.com return store_fault; 5647944SGiacomo.Gabrielli@arm.com 5657848SAli.Saidi@ARM.com if (store_inst->readPredicate() == false) 5667848SAli.Saidi@ARM.com store_inst->forwardOldRegs(); 5677848SAli.Saidi@ARM.com 5682329SN/A if (storeQueue[store_idx].size == 0) { 5697782Sminkyu.jeong@arm.com DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 5707720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 5712292SN/A 5722292SN/A return store_fault; 5737782Sminkyu.jeong@arm.com } else if (store_inst->readPredicate() == false) { 5747782Sminkyu.jeong@arm.com DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 5757782Sminkyu.jeong@arm.com store_inst->seqNum); 5767782Sminkyu.jeong@arm.com return store_fault; 5772292SN/A } 5782292SN/A 5792292SN/A assert(store_fault == NoFault); 5802292SN/A 5812336SN/A if (store_inst->isStoreConditional()) { 5822336SN/A // Store conditionals need to set themselves as able to 5832336SN/A // writeback if we haven't had a fault by here. 5842329SN/A storeQueue[store_idx].canWB = true; 5852292SN/A 5862329SN/A ++storesToWB; 5872292SN/A } 5882292SN/A 5898199SAli.Saidi@ARM.com return checkViolations(load_idx, store_inst); 5902292SN/A 5912292SN/A} 5922292SN/A 5932292SN/Atemplate <class Impl> 5942292SN/Avoid 5952292SN/ALSQUnit<Impl>::commitLoad() 5962292SN/A{ 5972292SN/A assert(loadQueue[loadHead]); 5982292SN/A 5997720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 6007720Sgblack@eecs.umich.edu loadQueue[loadHead]->pcState()); 6012292SN/A 6022292SN/A loadQueue[loadHead] = NULL; 6032292SN/A 6042292SN/A incrLdIdx(loadHead); 6052292SN/A 6062292SN/A --loads; 6072292SN/A} 6082292SN/A 6092292SN/Atemplate <class Impl> 6102292SN/Avoid 6112292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 6122292SN/A{ 6132292SN/A assert(loads == 0 || loadQueue[loadHead]); 6142292SN/A 6152292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 6162292SN/A commitLoad(); 6172292SN/A } 6182292SN/A} 6192292SN/A 6202292SN/Atemplate <class Impl> 6212292SN/Avoid 6222292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 6232292SN/A{ 6242292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 6252292SN/A 6262292SN/A int store_idx = storeHead; 6272292SN/A 6282292SN/A while (store_idx != storeTail) { 6292292SN/A assert(storeQueue[store_idx].inst); 6302329SN/A // Mark any stores that are now committed and have not yet 6312329SN/A // been marked as able to write back. 6322292SN/A if (!storeQueue[store_idx].canWB) { 6332292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 6342292SN/A break; 6352292SN/A } 6362292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 6377720Sgblack@eecs.umich.edu "%s [sn:%lli]\n", 6387720Sgblack@eecs.umich.edu storeQueue[store_idx].inst->pcState(), 6392292SN/A storeQueue[store_idx].inst->seqNum); 6402292SN/A 6412292SN/A storeQueue[store_idx].canWB = true; 6422292SN/A 6432292SN/A ++storesToWB; 6442292SN/A } 6452292SN/A 6462292SN/A incrStIdx(store_idx); 6472292SN/A } 6482292SN/A} 6492292SN/A 6502292SN/Atemplate <class Impl> 6512292SN/Avoid 6526974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::writebackPendingStore() 6536974Stjones1@inf.ed.ac.uk{ 6546974Stjones1@inf.ed.ac.uk if (hasPendingPkt) { 6556974Stjones1@inf.ed.ac.uk assert(pendingPkt != NULL); 6566974Stjones1@inf.ed.ac.uk 6576974Stjones1@inf.ed.ac.uk // If the cache is blocked, this will store the packet for retry. 6586974Stjones1@inf.ed.ac.uk if (sendStore(pendingPkt)) { 6596974Stjones1@inf.ed.ac.uk storePostSend(pendingPkt); 6606974Stjones1@inf.ed.ac.uk } 6616974Stjones1@inf.ed.ac.uk pendingPkt = NULL; 6626974Stjones1@inf.ed.ac.uk hasPendingPkt = false; 6636974Stjones1@inf.ed.ac.uk } 6646974Stjones1@inf.ed.ac.uk} 6656974Stjones1@inf.ed.ac.uk 6666974Stjones1@inf.ed.ac.uktemplate <class Impl> 6676974Stjones1@inf.ed.ac.ukvoid 6682292SN/ALSQUnit<Impl>::writebackStores() 6692292SN/A{ 6706974Stjones1@inf.ed.ac.uk // First writeback the second packet from any split store that didn't 6716974Stjones1@inf.ed.ac.uk // complete last cycle because there weren't enough cache ports available. 6726974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc) { 6736974Stjones1@inf.ed.ac.uk writebackPendingStore(); 6746974Stjones1@inf.ed.ac.uk } 6756974Stjones1@inf.ed.ac.uk 6762292SN/A while (storesToWB > 0 && 6772292SN/A storeWBIdx != storeTail && 6782292SN/A storeQueue[storeWBIdx].inst && 6792292SN/A storeQueue[storeWBIdx].canWB && 6802292SN/A usedPorts < cachePorts) { 6812292SN/A 6822907Sktlim@umich.edu if (isStoreBlocked || lsq->cacheBlocked()) { 6832678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 6842678Sktlim@umich.edu " is blocked!\n"); 6852678Sktlim@umich.edu break; 6862678Sktlim@umich.edu } 6872678Sktlim@umich.edu 6882329SN/A // Store didn't write any data so no need to write it back to 6892329SN/A // memory. 6902292SN/A if (storeQueue[storeWBIdx].size == 0) { 6912292SN/A completeStore(storeWBIdx); 6922292SN/A 6932292SN/A incrStIdx(storeWBIdx); 6942292SN/A 6952292SN/A continue; 6962292SN/A } 6972678Sktlim@umich.edu 6982292SN/A ++usedPorts; 6992292SN/A 7002292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 7012292SN/A incrStIdx(storeWBIdx); 7022292SN/A 7032292SN/A continue; 7042292SN/A } 7052292SN/A 7062292SN/A assert(storeQueue[storeWBIdx].req); 7072292SN/A assert(!storeQueue[storeWBIdx].committed); 7082292SN/A 7096974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 7106974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqLow); 7116974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqHigh); 7126974Stjones1@inf.ed.ac.uk } 7136974Stjones1@inf.ed.ac.uk 7142669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 7152669Sktlim@umich.edu 7162669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 7172292SN/A storeQueue[storeWBIdx].committed = true; 7182292SN/A 7192669Sktlim@umich.edu assert(!inst->memData); 7202669Sktlim@umich.edu inst->memData = new uint8_t[64]; 7213772Sgblack@eecs.umich.edu 7224326Sgblack@eecs.umich.edu memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 7232669Sktlim@umich.edu 7244878Sstever@eecs.umich.edu MemCmd command = 7254878Sstever@eecs.umich.edu req->isSwap() ? MemCmd::SwapReq : 7266102Sgblack@eecs.umich.edu (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 7276974Stjones1@inf.ed.ac.uk PacketPtr data_pkt; 7286974Stjones1@inf.ed.ac.uk PacketPtr snd_data_pkt = NULL; 7292292SN/A 7302678Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 7312678Sktlim@umich.edu state->isLoad = false; 7322678Sktlim@umich.edu state->idx = storeWBIdx; 7332678Sktlim@umich.edu state->inst = inst; 7346974Stjones1@inf.ed.ac.uk 7356974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 7366974Stjones1@inf.ed.ac.uk 7376974Stjones1@inf.ed.ac.uk // Build a single data packet if the store isn't split. 7386974Stjones1@inf.ed.ac.uk data_pkt = new Packet(req, command, Packet::Broadcast); 7396974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 7406974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 7416974Stjones1@inf.ed.ac.uk } else { 7426974Stjones1@inf.ed.ac.uk RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 7436974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 7446974Stjones1@inf.ed.ac.uk 7456974Stjones1@inf.ed.ac.uk // Create two packets if the store is split in two. 7466974Stjones1@inf.ed.ac.uk data_pkt = new Packet(sreqLow, command, Packet::Broadcast); 7476974Stjones1@inf.ed.ac.uk snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast); 7486974Stjones1@inf.ed.ac.uk 7496974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 7506974Stjones1@inf.ed.ac.uk snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 7516974Stjones1@inf.ed.ac.uk 7526974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 7536974Stjones1@inf.ed.ac.uk snd_data_pkt->senderState = state; 7546974Stjones1@inf.ed.ac.uk 7556974Stjones1@inf.ed.ac.uk state->isSplit = true; 7566974Stjones1@inf.ed.ac.uk state->outstanding = 2; 7576974Stjones1@inf.ed.ac.uk 7586974Stjones1@inf.ed.ac.uk // Can delete the main request now. 7596974Stjones1@inf.ed.ac.uk delete req; 7606974Stjones1@inf.ed.ac.uk req = sreqLow; 7616974Stjones1@inf.ed.ac.uk } 7622678Sktlim@umich.edu 7637720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 7642292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 7657720Sgblack@eecs.umich.edu storeWBIdx, inst->pcState(), 7663797Sgblack@eecs.umich.edu req->getPaddr(), (int)*(inst->memData), 7673221Sktlim@umich.edu inst->seqNum); 7682292SN/A 7692693Sktlim@umich.edu // @todo: Remove this SC hack once the memory system handles it. 7704350Sgblack@eecs.umich.edu if (inst->isStoreConditional()) { 7716974Stjones1@inf.ed.ac.uk assert(!storeQueue[storeWBIdx].isSplit); 7723326Sktlim@umich.edu // Disable recording the result temporarily. Writing to 7733326Sktlim@umich.edu // misc regs normally updates the result, but this is not 7743326Sktlim@umich.edu // the desired behavior when handling store conditionals. 7753326Sktlim@umich.edu inst->recordResult = false; 7763326Sktlim@umich.edu bool success = TheISA::handleLockedWrite(inst.get(), req); 7773326Sktlim@umich.edu inst->recordResult = true; 7783326Sktlim@umich.edu 7793326Sktlim@umich.edu if (!success) { 7803326Sktlim@umich.edu // Instantly complete this store. 7813326Sktlim@umich.edu DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 7823326Sktlim@umich.edu "Instantly completing it.\n", 7833326Sktlim@umich.edu inst->seqNum); 7843326Sktlim@umich.edu WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 7857823Ssteve.reinhardt@amd.com cpu->schedule(wb, curTick() + 1); 7863326Sktlim@umich.edu completeStore(storeWBIdx); 7873326Sktlim@umich.edu incrStIdx(storeWBIdx); 7883326Sktlim@umich.edu continue; 7892693Sktlim@umich.edu } 7902693Sktlim@umich.edu } else { 7912693Sktlim@umich.edu // Non-store conditionals do not need a writeback. 7922693Sktlim@umich.edu state->noWB = true; 7932693Sktlim@umich.edu } 7942693Sktlim@umich.edu 7956974Stjones1@inf.ed.ac.uk if (!sendStore(data_pkt)) { 7964032Sktlim@umich.edu DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 7973221Sktlim@umich.edu "retry later\n", 7983221Sktlim@umich.edu inst->seqNum); 7996974Stjones1@inf.ed.ac.uk 8006974Stjones1@inf.ed.ac.uk // Need to store the second packet, if split. 8016974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 8026974Stjones1@inf.ed.ac.uk state->pktToSend = true; 8036974Stjones1@inf.ed.ac.uk state->pendingPacket = snd_data_pkt; 8046974Stjones1@inf.ed.ac.uk } 8052669Sktlim@umich.edu } else { 8066974Stjones1@inf.ed.ac.uk 8076974Stjones1@inf.ed.ac.uk // If split, try to send the second packet too 8086974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 8096974Stjones1@inf.ed.ac.uk assert(snd_data_pkt); 8106974Stjones1@inf.ed.ac.uk 8116974Stjones1@inf.ed.ac.uk // Ensure there are enough ports to use. 8126974Stjones1@inf.ed.ac.uk if (usedPorts < cachePorts) { 8136974Stjones1@inf.ed.ac.uk ++usedPorts; 8146974Stjones1@inf.ed.ac.uk if (sendStore(snd_data_pkt)) { 8156974Stjones1@inf.ed.ac.uk storePostSend(snd_data_pkt); 8166974Stjones1@inf.ed.ac.uk } else { 8176974Stjones1@inf.ed.ac.uk DPRINTF(IEW, "D-Cache became blocked when writing" 8186974Stjones1@inf.ed.ac.uk " [sn:%lli] second packet, will retry later\n", 8196974Stjones1@inf.ed.ac.uk inst->seqNum); 8206974Stjones1@inf.ed.ac.uk } 8216974Stjones1@inf.ed.ac.uk } else { 8226974Stjones1@inf.ed.ac.uk 8236974Stjones1@inf.ed.ac.uk // Store the packet for when there's free ports. 8246974Stjones1@inf.ed.ac.uk assert(pendingPkt == NULL); 8256974Stjones1@inf.ed.ac.uk pendingPkt = snd_data_pkt; 8266974Stjones1@inf.ed.ac.uk hasPendingPkt = true; 8276974Stjones1@inf.ed.ac.uk } 8286974Stjones1@inf.ed.ac.uk } else { 8296974Stjones1@inf.ed.ac.uk 8306974Stjones1@inf.ed.ac.uk // Not a split store. 8316974Stjones1@inf.ed.ac.uk storePostSend(data_pkt); 8326974Stjones1@inf.ed.ac.uk } 8332292SN/A } 8342292SN/A } 8352292SN/A 8362292SN/A // Not sure this should set it to 0. 8372292SN/A usedPorts = 0; 8382292SN/A 8392292SN/A assert(stores >= 0 && storesToWB >= 0); 8402292SN/A} 8412292SN/A 8422292SN/A/*template <class Impl> 8432292SN/Avoid 8442292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 8452292SN/A{ 8462292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 8472292SN/A mshrSeqNums.end(), 8482292SN/A seqNum); 8492292SN/A 8502292SN/A if (mshr_it != mshrSeqNums.end()) { 8512292SN/A mshrSeqNums.erase(mshr_it); 8522292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 8532292SN/A } 8542292SN/A}*/ 8552292SN/A 8562292SN/Atemplate <class Impl> 8572292SN/Avoid 8582292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 8592292SN/A{ 8602292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 8612329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 8622292SN/A 8632292SN/A int load_idx = loadTail; 8642292SN/A decrLdIdx(load_idx); 8652292SN/A 8662292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 8677720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 8682292SN/A "[sn:%lli]\n", 8697720Sgblack@eecs.umich.edu loadQueue[load_idx]->pcState(), 8702292SN/A loadQueue[load_idx]->seqNum); 8712292SN/A 8722292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 8732292SN/A stalled = false; 8742292SN/A stallingStoreIsn = 0; 8752292SN/A stallingLoadIdx = 0; 8762292SN/A } 8772292SN/A 8782329SN/A // Clear the smart pointer to make sure it is decremented. 8792731Sktlim@umich.edu loadQueue[load_idx]->setSquashed(); 8802292SN/A loadQueue[load_idx] = NULL; 8812292SN/A --loads; 8822292SN/A 8832292SN/A // Inefficient! 8842292SN/A loadTail = load_idx; 8852292SN/A 8862292SN/A decrLdIdx(load_idx); 8872727Sktlim@umich.edu ++lsqSquashedLoads; 8882292SN/A } 8892292SN/A 8902292SN/A if (isLoadBlocked) { 8912292SN/A if (squashed_num < blockedLoadSeqNum) { 8922292SN/A isLoadBlocked = false; 8932292SN/A loadBlockedHandled = false; 8942292SN/A blockedLoadSeqNum = 0; 8952292SN/A } 8962292SN/A } 8972292SN/A 8984032Sktlim@umich.edu if (memDepViolator && squashed_num < memDepViolator->seqNum) { 8994032Sktlim@umich.edu memDepViolator = NULL; 9004032Sktlim@umich.edu } 9014032Sktlim@umich.edu 9022292SN/A int store_idx = storeTail; 9032292SN/A decrStIdx(store_idx); 9042292SN/A 9052292SN/A while (stores != 0 && 9062292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 9072329SN/A // Instructions marked as can WB are already committed. 9082292SN/A if (storeQueue[store_idx].canWB) { 9092292SN/A break; 9102292SN/A } 9112292SN/A 9127720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 9132292SN/A "idx:%i [sn:%lli]\n", 9147720Sgblack@eecs.umich.edu storeQueue[store_idx].inst->pcState(), 9152292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 9162292SN/A 9172329SN/A // I don't think this can happen. It should have been cleared 9182329SN/A // by the stalling load. 9192292SN/A if (isStalled() && 9202292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 9212292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 9222292SN/A stalled = false; 9232292SN/A stallingStoreIsn = 0; 9242292SN/A } 9252292SN/A 9262329SN/A // Clear the smart pointer to make sure it is decremented. 9272731Sktlim@umich.edu storeQueue[store_idx].inst->setSquashed(); 9282292SN/A storeQueue[store_idx].inst = NULL; 9292292SN/A storeQueue[store_idx].canWB = 0; 9302292SN/A 9314032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 9324032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the proper 9334032Sktlim@umich.edu // place to really handle request deletes. 9344032Sktlim@umich.edu delete storeQueue[store_idx].req; 9356974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 9366974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqLow; 9376974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqHigh; 9386974Stjones1@inf.ed.ac.uk 9396974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqLow = NULL; 9406974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqHigh = NULL; 9416974Stjones1@inf.ed.ac.uk } 9424032Sktlim@umich.edu 9432292SN/A storeQueue[store_idx].req = NULL; 9442292SN/A --stores; 9452292SN/A 9462292SN/A // Inefficient! 9472292SN/A storeTail = store_idx; 9482292SN/A 9492292SN/A decrStIdx(store_idx); 9502727Sktlim@umich.edu ++lsqSquashedStores; 9512292SN/A } 9522292SN/A} 9532292SN/A 9542292SN/Atemplate <class Impl> 9552292SN/Avoid 9563349Sbinkertn@umich.eduLSQUnit<Impl>::storePostSend(PacketPtr pkt) 9572693Sktlim@umich.edu{ 9582693Sktlim@umich.edu if (isStalled() && 9592693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 9602693Sktlim@umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 9612693Sktlim@umich.edu "load idx:%i\n", 9622693Sktlim@umich.edu stallingStoreIsn, stallingLoadIdx); 9632693Sktlim@umich.edu stalled = false; 9642693Sktlim@umich.edu stallingStoreIsn = 0; 9652693Sktlim@umich.edu iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 9662693Sktlim@umich.edu } 9672693Sktlim@umich.edu 9682693Sktlim@umich.edu if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 9692693Sktlim@umich.edu // The store is basically completed at this time. This 9702693Sktlim@umich.edu // only works so long as the checker doesn't try to 9712693Sktlim@umich.edu // verify the value in memory for stores. 9722693Sktlim@umich.edu storeQueue[storeWBIdx].inst->setCompleted(); 9732733Sktlim@umich.edu#if USE_CHECKER 9742693Sktlim@umich.edu if (cpu->checker) { 9752732Sktlim@umich.edu cpu->checker->verify(storeQueue[storeWBIdx].inst); 9762693Sktlim@umich.edu } 9772733Sktlim@umich.edu#endif 9782693Sktlim@umich.edu } 9792693Sktlim@umich.edu 9802693Sktlim@umich.edu incrStIdx(storeWBIdx); 9812693Sktlim@umich.edu} 9822693Sktlim@umich.edu 9832693Sktlim@umich.edutemplate <class Impl> 9842693Sktlim@umich.eduvoid 9852678Sktlim@umich.eduLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 9862678Sktlim@umich.edu{ 9872678Sktlim@umich.edu iewStage->wakeCPU(); 9882678Sktlim@umich.edu 9892678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 9902678Sktlim@umich.edu if (inst->isSquashed()) { 9912927Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 9922678Sktlim@umich.edu assert(!inst->isStore()); 9932727Sktlim@umich.edu ++lsqIgnoredResponses; 9942678Sktlim@umich.edu return; 9952678Sktlim@umich.edu } 9962678Sktlim@umich.edu 9972678Sktlim@umich.edu if (!inst->isExecuted()) { 9982678Sktlim@umich.edu inst->setExecuted(); 9992678Sktlim@umich.edu 10002678Sktlim@umich.edu // Complete access to copy data to proper place. 10012678Sktlim@umich.edu inst->completeAcc(pkt); 10022678Sktlim@umich.edu } 10032678Sktlim@umich.edu 10042678Sktlim@umich.edu // Need to insert instruction into queue to commit 10052678Sktlim@umich.edu iewStage->instToCommit(inst); 10062678Sktlim@umich.edu 10072678Sktlim@umich.edu iewStage->activityThisCycle(); 10087598Sminkyu.jeong@arm.com 10097598Sminkyu.jeong@arm.com // see if this load changed the PC 10107598Sminkyu.jeong@arm.com iewStage->checkMisprediction(inst); 10112678Sktlim@umich.edu} 10122678Sktlim@umich.edu 10132678Sktlim@umich.edutemplate <class Impl> 10142678Sktlim@umich.eduvoid 10152292SN/ALSQUnit<Impl>::completeStore(int store_idx) 10162292SN/A{ 10172292SN/A assert(storeQueue[store_idx].inst); 10182292SN/A storeQueue[store_idx].completed = true; 10192292SN/A --storesToWB; 10202292SN/A // A bit conservative because a store completion may not free up entries, 10212292SN/A // but hopefully avoids two store completions in one cycle from making 10222292SN/A // the CPU tick twice. 10233126Sktlim@umich.edu cpu->wakeCPU(); 10242292SN/A cpu->activityThisCycle(); 10252292SN/A 10262292SN/A if (store_idx == storeHead) { 10272292SN/A do { 10282292SN/A incrStIdx(storeHead); 10292292SN/A 10302292SN/A --stores; 10312292SN/A } while (storeQueue[storeHead].completed && 10322292SN/A storeHead != storeTail); 10332292SN/A 10342292SN/A iewStage->updateLSQNextCycle = true; 10352292SN/A } 10362292SN/A 10372329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 10382329SN/A "idx:%i\n", 10392329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 10402292SN/A 10412292SN/A if (isStalled() && 10422292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 10432292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 10442292SN/A "load idx:%i\n", 10452292SN/A stallingStoreIsn, stallingLoadIdx); 10462292SN/A stalled = false; 10472292SN/A stallingStoreIsn = 0; 10482292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 10492292SN/A } 10502316SN/A 10512316SN/A storeQueue[store_idx].inst->setCompleted(); 10522329SN/A 10532329SN/A // Tell the checker we've completed this instruction. Some stores 10542329SN/A // may get reported twice to the checker, but the checker can 10552329SN/A // handle that case. 10562733Sktlim@umich.edu#if USE_CHECKER 10572316SN/A if (cpu->checker) { 10582732Sktlim@umich.edu cpu->checker->verify(storeQueue[store_idx].inst); 10592316SN/A } 10602733Sktlim@umich.edu#endif 10612292SN/A} 10622292SN/A 10632292SN/Atemplate <class Impl> 10646974Stjones1@inf.ed.ac.ukbool 10656974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::sendStore(PacketPtr data_pkt) 10666974Stjones1@inf.ed.ac.uk{ 10676974Stjones1@inf.ed.ac.uk if (!dcachePort->sendTiming(data_pkt)) { 10686974Stjones1@inf.ed.ac.uk // Need to handle becoming blocked on a store. 10696974Stjones1@inf.ed.ac.uk isStoreBlocked = true; 10706974Stjones1@inf.ed.ac.uk ++lsqCacheBlocked; 10716974Stjones1@inf.ed.ac.uk assert(retryPkt == NULL); 10726974Stjones1@inf.ed.ac.uk retryPkt = data_pkt; 10736974Stjones1@inf.ed.ac.uk lsq->setRetryTid(lsqID); 10746974Stjones1@inf.ed.ac.uk return false; 10756974Stjones1@inf.ed.ac.uk } 10766974Stjones1@inf.ed.ac.uk return true; 10776974Stjones1@inf.ed.ac.uk} 10786974Stjones1@inf.ed.ac.uk 10796974Stjones1@inf.ed.ac.uktemplate <class Impl> 10802693Sktlim@umich.eduvoid 10812693Sktlim@umich.eduLSQUnit<Impl>::recvRetry() 10822693Sktlim@umich.edu{ 10832698Sktlim@umich.edu if (isStoreBlocked) { 10844985Sktlim@umich.edu DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 10852698Sktlim@umich.edu assert(retryPkt != NULL); 10862693Sktlim@umich.edu 10872698Sktlim@umich.edu if (dcachePort->sendTiming(retryPkt)) { 10886974Stjones1@inf.ed.ac.uk LSQSenderState *state = 10896974Stjones1@inf.ed.ac.uk dynamic_cast<LSQSenderState *>(retryPkt->senderState); 10906974Stjones1@inf.ed.ac.uk 10916974Stjones1@inf.ed.ac.uk // Don't finish the store unless this is the last packet. 10928133SAli.Saidi@ARM.com if (!TheISA::HasUnalignedMemAcc || !state->pktToSend || 10938133SAli.Saidi@ARM.com state->pendingPacket == retryPkt) { 10948133SAli.Saidi@ARM.com state->pktToSend = false; 10956974Stjones1@inf.ed.ac.uk storePostSend(retryPkt); 10966974Stjones1@inf.ed.ac.uk } 10972699Sktlim@umich.edu retryPkt = NULL; 10982693Sktlim@umich.edu isStoreBlocked = false; 10996221Snate@binkert.org lsq->setRetryTid(InvalidThreadID); 11006974Stjones1@inf.ed.ac.uk 11016974Stjones1@inf.ed.ac.uk // Send any outstanding packet. 11026974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 11036974Stjones1@inf.ed.ac.uk assert(state->pendingPacket); 11046974Stjones1@inf.ed.ac.uk if (sendStore(state->pendingPacket)) { 11056974Stjones1@inf.ed.ac.uk storePostSend(state->pendingPacket); 11066974Stjones1@inf.ed.ac.uk } 11076974Stjones1@inf.ed.ac.uk } 11082693Sktlim@umich.edu } else { 11092693Sktlim@umich.edu // Still blocked! 11102727Sktlim@umich.edu ++lsqCacheBlocked; 11112907Sktlim@umich.edu lsq->setRetryTid(lsqID); 11122693Sktlim@umich.edu } 11132693Sktlim@umich.edu } else if (isLoadBlocked) { 11142693Sktlim@umich.edu DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 11152693Sktlim@umich.edu "no need to resend packet.\n"); 11162693Sktlim@umich.edu } else { 11172693Sktlim@umich.edu DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 11182693Sktlim@umich.edu } 11192693Sktlim@umich.edu} 11202693Sktlim@umich.edu 11212693Sktlim@umich.edutemplate <class Impl> 11222292SN/Ainline void 11232292SN/ALSQUnit<Impl>::incrStIdx(int &store_idx) 11242292SN/A{ 11252292SN/A if (++store_idx >= SQEntries) 11262292SN/A store_idx = 0; 11272292SN/A} 11282292SN/A 11292292SN/Atemplate <class Impl> 11302292SN/Ainline void 11312292SN/ALSQUnit<Impl>::decrStIdx(int &store_idx) 11322292SN/A{ 11332292SN/A if (--store_idx < 0) 11342292SN/A store_idx += SQEntries; 11352292SN/A} 11362292SN/A 11372292SN/Atemplate <class Impl> 11382292SN/Ainline void 11392292SN/ALSQUnit<Impl>::incrLdIdx(int &load_idx) 11402292SN/A{ 11412292SN/A if (++load_idx >= LQEntries) 11422292SN/A load_idx = 0; 11432292SN/A} 11442292SN/A 11452292SN/Atemplate <class Impl> 11462292SN/Ainline void 11472292SN/ALSQUnit<Impl>::decrLdIdx(int &load_idx) 11482292SN/A{ 11492292SN/A if (--load_idx < 0) 11502292SN/A load_idx += LQEntries; 11512292SN/A} 11522329SN/A 11532329SN/Atemplate <class Impl> 11542329SN/Avoid 11552329SN/ALSQUnit<Impl>::dumpInsts() 11562329SN/A{ 11572329SN/A cprintf("Load store queue: Dumping instructions.\n"); 11582329SN/A cprintf("Load queue size: %i\n", loads); 11592329SN/A cprintf("Load queue: "); 11602329SN/A 11612329SN/A int load_idx = loadHead; 11622329SN/A 11632329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 11647720Sgblack@eecs.umich.edu cprintf("%s ", loadQueue[load_idx]->pcState()); 11652329SN/A 11662329SN/A incrLdIdx(load_idx); 11672329SN/A } 11682329SN/A 11692329SN/A cprintf("Store queue size: %i\n", stores); 11702329SN/A cprintf("Store queue: "); 11712329SN/A 11722329SN/A int store_idx = storeHead; 11732329SN/A 11742329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 11757720Sgblack@eecs.umich.edu cprintf("%s ", storeQueue[store_idx].inst->pcState()); 11762329SN/A 11772329SN/A incrStIdx(store_idx); 11782329SN/A } 11792329SN/A 11802329SN/A cprintf("\n"); 11812329SN/A} 1182