lsq_unit_impl.hh revision 7598
12292SN/A/* 27597Sminkyu.jeong@arm.com * Copyright (c) 2010 ARM Limited 37597Sminkyu.jeong@arm.com * All rights reserved 47597Sminkyu.jeong@arm.com * 57597Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67597Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77597Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87597Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97597Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107597Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117597Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127597Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137597Sminkyu.jeong@arm.com * 142292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 152292SN/A * All rights reserved. 162292SN/A * 172292SN/A * Redistribution and use in source and binary forms, with or without 182292SN/A * modification, are permitted provided that the following conditions are 192292SN/A * met: redistributions of source code must retain the above copyright 202292SN/A * notice, this list of conditions and the following disclaimer; 212292SN/A * redistributions in binary form must reproduce the above copyright 222292SN/A * notice, this list of conditions and the following disclaimer in the 232292SN/A * documentation and/or other materials provided with the distribution; 242292SN/A * neither the name of the copyright holders nor the names of its 252292SN/A * contributors may be used to endorse or promote products derived from 262292SN/A * this software without specific prior written permission. 272292SN/A * 282292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392689Sktlim@umich.edu * 402689Sktlim@umich.edu * Authors: Kevin Lim 412689Sktlim@umich.edu * Korey Sewell 422292SN/A */ 432292SN/A 443326Sktlim@umich.edu#include "arch/locked_mem.hh" 456658Snate@binkert.org#include "config/the_isa.hh" 462733Sktlim@umich.edu#include "config/use_checker.hh" 472907Sktlim@umich.edu#include "cpu/o3/lsq.hh" 482292SN/A#include "cpu/o3/lsq_unit.hh" 492292SN/A#include "base/str.hh" 502722Sktlim@umich.edu#include "mem/packet.hh" 512669Sktlim@umich.edu#include "mem/request.hh" 522292SN/A 532790Sktlim@umich.edu#if USE_CHECKER 542790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 552790Sktlim@umich.edu#endif 562790Sktlim@umich.edu 572669Sktlim@umich.edutemplate<class Impl> 582678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 592678Sktlim@umich.edu LSQUnit *lsq_ptr) 605606Snate@binkert.org : inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 612292SN/A{ 622678Sktlim@umich.edu this->setFlags(Event::AutoDelete); 632292SN/A} 642292SN/A 652669Sktlim@umich.edutemplate<class Impl> 662292SN/Avoid 672678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 682292SN/A{ 692678Sktlim@umich.edu if (!lsqPtr->isSwitchedOut()) { 702678Sktlim@umich.edu lsqPtr->writeback(inst, pkt); 712678Sktlim@umich.edu } 724319Sktlim@umich.edu 734319Sktlim@umich.edu if (pkt->senderState) 744319Sktlim@umich.edu delete pkt->senderState; 754319Sktlim@umich.edu 764319Sktlim@umich.edu delete pkt->req; 772678Sktlim@umich.edu delete pkt; 782678Sktlim@umich.edu} 792292SN/A 802678Sktlim@umich.edutemplate<class Impl> 812678Sktlim@umich.educonst char * 825336Shines@cs.fsu.eduLSQUnit<Impl>::WritebackEvent::description() const 832678Sktlim@umich.edu{ 844873Sstever@eecs.umich.edu return "Store writeback"; 852678Sktlim@umich.edu} 862292SN/A 872678Sktlim@umich.edutemplate<class Impl> 882678Sktlim@umich.eduvoid 892678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 902678Sktlim@umich.edu{ 912678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 922678Sktlim@umich.edu DynInstPtr inst = state->inst; 932678Sktlim@umich.edu DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum); 942698Sktlim@umich.edu DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum); 952344SN/A 962678Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 972678Sktlim@umich.edu 984986Ssaidi@eecs.umich.edu assert(!pkt->wasNacked()); 994986Ssaidi@eecs.umich.edu 1006974Stjones1@inf.ed.ac.uk // If this is a split access, wait until all packets are received. 1016974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && !state->complete()) { 1026974Stjones1@inf.ed.ac.uk delete pkt->req; 1036974Stjones1@inf.ed.ac.uk delete pkt; 1046974Stjones1@inf.ed.ac.uk return; 1056974Stjones1@inf.ed.ac.uk } 1066974Stjones1@inf.ed.ac.uk 1072678Sktlim@umich.edu if (isSwitchedOut() || inst->isSquashed()) { 1082820Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 1092678Sktlim@umich.edu } else { 1102678Sktlim@umich.edu if (!state->noWB) { 1116974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 1126974Stjones1@inf.ed.ac.uk !state->isLoad) { 1136974Stjones1@inf.ed.ac.uk writeback(inst, pkt); 1146974Stjones1@inf.ed.ac.uk } else { 1156974Stjones1@inf.ed.ac.uk writeback(inst, state->mainPkt); 1166974Stjones1@inf.ed.ac.uk } 1172678Sktlim@umich.edu } 1182678Sktlim@umich.edu 1192678Sktlim@umich.edu if (inst->isStore()) { 1202678Sktlim@umich.edu completeStore(state->idx); 1212678Sktlim@umich.edu } 1222344SN/A } 1232307SN/A 1246974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 1256974Stjones1@inf.ed.ac.uk delete state->mainPkt->req; 1266974Stjones1@inf.ed.ac.uk delete state->mainPkt; 1276974Stjones1@inf.ed.ac.uk } 1282678Sktlim@umich.edu delete state; 1294032Sktlim@umich.edu delete pkt->req; 1302678Sktlim@umich.edu delete pkt; 1312292SN/A} 1322292SN/A 1332292SN/Atemplate <class Impl> 1342292SN/ALSQUnit<Impl>::LSQUnit() 1352678Sktlim@umich.edu : loads(0), stores(0), storesToWB(0), stalled(false), 1362678Sktlim@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1376974Stjones1@inf.ed.ac.uk loadBlockedHandled(false), hasPendingPkt(false) 1382292SN/A{ 1392292SN/A} 1402292SN/A 1412292SN/Atemplate<class Impl> 1422292SN/Avoid 1435529Snate@binkert.orgLSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 1445529Snate@binkert.org LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 1455529Snate@binkert.org unsigned id) 1462292SN/A{ 1474329Sktlim@umich.edu cpu = cpu_ptr; 1484329Sktlim@umich.edu iewStage = iew_ptr; 1494329Sktlim@umich.edu 1504329Sktlim@umich.edu DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1512292SN/A 1522307SN/A switchedOut = false; 1532307SN/A 1542907Sktlim@umich.edu lsq = lsq_ptr; 1552907Sktlim@umich.edu 1562292SN/A lsqID = id; 1572292SN/A 1582329SN/A // Add 1 for the sentinel entry (they are circular queues). 1592329SN/A LQEntries = maxLQEntries + 1; 1602329SN/A SQEntries = maxSQEntries + 1; 1612292SN/A 1622292SN/A loadQueue.resize(LQEntries); 1632292SN/A storeQueue.resize(SQEntries); 1642292SN/A 1652292SN/A loadHead = loadTail = 0; 1662292SN/A 1672292SN/A storeHead = storeWBIdx = storeTail = 0; 1682292SN/A 1692292SN/A usedPorts = 0; 1702292SN/A cachePorts = params->cachePorts; 1712292SN/A 1723492Sktlim@umich.edu retryPkt = NULL; 1732329SN/A memDepViolator = NULL; 1742292SN/A 1752292SN/A blockedLoadSeqNum = 0; 1762292SN/A} 1772292SN/A 1782292SN/Atemplate<class Impl> 1792292SN/Astd::string 1802292SN/ALSQUnit<Impl>::name() const 1812292SN/A{ 1822292SN/A if (Impl::MaxThreads == 1) { 1832292SN/A return iewStage->name() + ".lsq"; 1842292SN/A } else { 1852292SN/A return iewStage->name() + ".lsq.thread." + to_string(lsqID); 1862292SN/A } 1872292SN/A} 1882292SN/A 1892292SN/Atemplate<class Impl> 1902292SN/Avoid 1912727Sktlim@umich.eduLSQUnit<Impl>::regStats() 1922727Sktlim@umich.edu{ 1932727Sktlim@umich.edu lsqForwLoads 1942727Sktlim@umich.edu .name(name() + ".forwLoads") 1952727Sktlim@umich.edu .desc("Number of loads that had data forwarded from stores"); 1962727Sktlim@umich.edu 1972727Sktlim@umich.edu invAddrLoads 1982727Sktlim@umich.edu .name(name() + ".invAddrLoads") 1992727Sktlim@umich.edu .desc("Number of loads ignored due to an invalid address"); 2002727Sktlim@umich.edu 2012727Sktlim@umich.edu lsqSquashedLoads 2022727Sktlim@umich.edu .name(name() + ".squashedLoads") 2032727Sktlim@umich.edu .desc("Number of loads squashed"); 2042727Sktlim@umich.edu 2052727Sktlim@umich.edu lsqIgnoredResponses 2062727Sktlim@umich.edu .name(name() + ".ignoredResponses") 2072727Sktlim@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 2082727Sktlim@umich.edu 2092361SN/A lsqMemOrderViolation 2102361SN/A .name(name() + ".memOrderViolation") 2112361SN/A .desc("Number of memory ordering violations"); 2122361SN/A 2132727Sktlim@umich.edu lsqSquashedStores 2142727Sktlim@umich.edu .name(name() + ".squashedStores") 2152727Sktlim@umich.edu .desc("Number of stores squashed"); 2162727Sktlim@umich.edu 2172727Sktlim@umich.edu invAddrSwpfs 2182727Sktlim@umich.edu .name(name() + ".invAddrSwpfs") 2192727Sktlim@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 2202727Sktlim@umich.edu 2212727Sktlim@umich.edu lsqBlockedLoads 2222727Sktlim@umich.edu .name(name() + ".blockedLoads") 2232727Sktlim@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 2242727Sktlim@umich.edu 2252727Sktlim@umich.edu lsqRescheduledLoads 2262727Sktlim@umich.edu .name(name() + ".rescheduledLoads") 2272727Sktlim@umich.edu .desc("Number of loads that were rescheduled"); 2282727Sktlim@umich.edu 2292727Sktlim@umich.edu lsqCacheBlocked 2302727Sktlim@umich.edu .name(name() + ".cacheBlocked") 2312727Sktlim@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2322727Sktlim@umich.edu} 2332727Sktlim@umich.edu 2342727Sktlim@umich.edutemplate<class Impl> 2352727Sktlim@umich.eduvoid 2364329Sktlim@umich.eduLSQUnit<Impl>::setDcachePort(Port *dcache_port) 2374329Sktlim@umich.edu{ 2384329Sktlim@umich.edu dcachePort = dcache_port; 2394329Sktlim@umich.edu 2404329Sktlim@umich.edu#if USE_CHECKER 2414329Sktlim@umich.edu if (cpu->checker) { 2424329Sktlim@umich.edu cpu->checker->setDcachePort(dcachePort); 2434329Sktlim@umich.edu } 2444329Sktlim@umich.edu#endif 2454329Sktlim@umich.edu} 2464329Sktlim@umich.edu 2474329Sktlim@umich.edutemplate<class Impl> 2484329Sktlim@umich.eduvoid 2492292SN/ALSQUnit<Impl>::clearLQ() 2502292SN/A{ 2512292SN/A loadQueue.clear(); 2522292SN/A} 2532292SN/A 2542292SN/Atemplate<class Impl> 2552292SN/Avoid 2562292SN/ALSQUnit<Impl>::clearSQ() 2572292SN/A{ 2582292SN/A storeQueue.clear(); 2592292SN/A} 2602292SN/A 2612292SN/Atemplate<class Impl> 2622292SN/Avoid 2632307SN/ALSQUnit<Impl>::switchOut() 2642307SN/A{ 2652307SN/A switchedOut = true; 2662367SN/A for (int i = 0; i < loadQueue.size(); ++i) { 2672367SN/A assert(!loadQueue[i]); 2682307SN/A loadQueue[i] = NULL; 2692367SN/A } 2702307SN/A 2712329SN/A assert(storesToWB == 0); 2722307SN/A} 2732307SN/A 2742307SN/Atemplate<class Impl> 2752307SN/Avoid 2762307SN/ALSQUnit<Impl>::takeOverFrom() 2772307SN/A{ 2782307SN/A switchedOut = false; 2792307SN/A loads = stores = storesToWB = 0; 2802307SN/A 2812307SN/A loadHead = loadTail = 0; 2822307SN/A 2832307SN/A storeHead = storeWBIdx = storeTail = 0; 2842307SN/A 2852307SN/A usedPorts = 0; 2862307SN/A 2872329SN/A memDepViolator = NULL; 2882307SN/A 2892307SN/A blockedLoadSeqNum = 0; 2902307SN/A 2912307SN/A stalled = false; 2922307SN/A isLoadBlocked = false; 2932307SN/A loadBlockedHandled = false; 2942307SN/A} 2952307SN/A 2962307SN/Atemplate<class Impl> 2972307SN/Avoid 2982292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 2992292SN/A{ 3002329SN/A unsigned size_plus_sentinel = size + 1; 3012329SN/A assert(size_plus_sentinel >= LQEntries); 3022292SN/A 3032329SN/A if (size_plus_sentinel > LQEntries) { 3042329SN/A while (size_plus_sentinel > loadQueue.size()) { 3052292SN/A DynInstPtr dummy; 3062292SN/A loadQueue.push_back(dummy); 3072292SN/A LQEntries++; 3082292SN/A } 3092292SN/A } else { 3102329SN/A LQEntries = size_plus_sentinel; 3112292SN/A } 3122292SN/A 3132292SN/A} 3142292SN/A 3152292SN/Atemplate<class Impl> 3162292SN/Avoid 3172292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 3182292SN/A{ 3192329SN/A unsigned size_plus_sentinel = size + 1; 3202329SN/A if (size_plus_sentinel > SQEntries) { 3212329SN/A while (size_plus_sentinel > storeQueue.size()) { 3222292SN/A SQEntry dummy; 3232292SN/A storeQueue.push_back(dummy); 3242292SN/A SQEntries++; 3252292SN/A } 3262292SN/A } else { 3272329SN/A SQEntries = size_plus_sentinel; 3282292SN/A } 3292292SN/A} 3302292SN/A 3312292SN/Atemplate <class Impl> 3322292SN/Avoid 3332292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 3342292SN/A{ 3352292SN/A assert(inst->isMemRef()); 3362292SN/A 3372292SN/A assert(inst->isLoad() || inst->isStore()); 3382292SN/A 3392292SN/A if (inst->isLoad()) { 3402292SN/A insertLoad(inst); 3412292SN/A } else { 3422292SN/A insertStore(inst); 3432292SN/A } 3442292SN/A 3452292SN/A inst->setInLSQ(); 3462292SN/A} 3472292SN/A 3482292SN/Atemplate <class Impl> 3492292SN/Avoid 3502292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3512292SN/A{ 3522329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3532329SN/A assert(loads < LQEntries); 3542292SN/A 3552292SN/A DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n", 3562292SN/A load_inst->readPC(), loadTail, load_inst->seqNum); 3572292SN/A 3582292SN/A load_inst->lqIdx = loadTail; 3592292SN/A 3602292SN/A if (stores == 0) { 3612292SN/A load_inst->sqIdx = -1; 3622292SN/A } else { 3632292SN/A load_inst->sqIdx = storeTail; 3642292SN/A } 3652292SN/A 3662292SN/A loadQueue[loadTail] = load_inst; 3672292SN/A 3682292SN/A incrLdIdx(loadTail); 3692292SN/A 3702292SN/A ++loads; 3712292SN/A} 3722292SN/A 3732292SN/Atemplate <class Impl> 3742292SN/Avoid 3752292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3762292SN/A{ 3772292SN/A // Make sure it is not full before inserting an instruction. 3782292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3792292SN/A assert(stores < SQEntries); 3802292SN/A 3812292SN/A DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n", 3822292SN/A store_inst->readPC(), storeTail, store_inst->seqNum); 3832292SN/A 3842292SN/A store_inst->sqIdx = storeTail; 3852292SN/A store_inst->lqIdx = loadTail; 3862292SN/A 3872292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3882292SN/A 3892292SN/A incrStIdx(storeTail); 3902292SN/A 3912292SN/A ++stores; 3922292SN/A} 3932292SN/A 3942292SN/Atemplate <class Impl> 3952292SN/Atypename Impl::DynInstPtr 3962292SN/ALSQUnit<Impl>::getMemDepViolator() 3972292SN/A{ 3982292SN/A DynInstPtr temp = memDepViolator; 3992292SN/A 4002292SN/A memDepViolator = NULL; 4012292SN/A 4022292SN/A return temp; 4032292SN/A} 4042292SN/A 4052292SN/Atemplate <class Impl> 4062292SN/Aunsigned 4072292SN/ALSQUnit<Impl>::numFreeEntries() 4082292SN/A{ 4092292SN/A unsigned free_lq_entries = LQEntries - loads; 4102292SN/A unsigned free_sq_entries = SQEntries - stores; 4112292SN/A 4122292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 4132292SN/A // empty/full conditions. Subtract 1 from the free entries. 4142292SN/A if (free_lq_entries < free_sq_entries) { 4152292SN/A return free_lq_entries - 1; 4162292SN/A } else { 4172292SN/A return free_sq_entries - 1; 4182292SN/A } 4192292SN/A} 4202292SN/A 4212292SN/Atemplate <class Impl> 4222292SN/Aint 4232292SN/ALSQUnit<Impl>::numLoadsReady() 4242292SN/A{ 4252292SN/A int load_idx = loadHead; 4262292SN/A int retval = 0; 4272292SN/A 4282292SN/A while (load_idx != loadTail) { 4292292SN/A assert(loadQueue[load_idx]); 4302292SN/A 4312292SN/A if (loadQueue[load_idx]->readyToIssue()) { 4322292SN/A ++retval; 4332292SN/A } 4342292SN/A } 4352292SN/A 4362292SN/A return retval; 4372292SN/A} 4382292SN/A 4392292SN/Atemplate <class Impl> 4402292SN/AFault 4412292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 4422292SN/A{ 4434032Sktlim@umich.edu using namespace TheISA; 4442292SN/A // Execute a specific load. 4452292SN/A Fault load_fault = NoFault; 4462292SN/A 4472292SN/A DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n", 4482292SN/A inst->readPC(),inst->seqNum); 4492292SN/A 4504032Sktlim@umich.edu assert(!inst->isSquashed()); 4514032Sktlim@umich.edu 4522669Sktlim@umich.edu load_fault = inst->initiateAcc(); 4532292SN/A 4547597Sminkyu.jeong@arm.com // If the instruction faulted or predicated false, then we need to send it 4557597Sminkyu.jeong@arm.com // along to commit without the instruction completing. 4567597Sminkyu.jeong@arm.com if (load_fault != NoFault || inst->readPredicate() == false) { 4572329SN/A // Send this instruction to commit, also make sure iew stage 4582329SN/A // realizes there is activity. 4592367SN/A // Mark it as executed unless it is an uncached load that 4602367SN/A // needs to hit the head of commit. 4614032Sktlim@umich.edu if (!(inst->hasRequest() && inst->uncacheable()) || 4623731Sktlim@umich.edu inst->isAtCommit()) { 4632367SN/A inst->setExecuted(); 4642367SN/A } 4652292SN/A iewStage->instToCommit(inst); 4662292SN/A iewStage->activityThisCycle(); 4674032Sktlim@umich.edu } else if (!loadBlocked()) { 4684032Sktlim@umich.edu assert(inst->effAddrValid); 4694032Sktlim@umich.edu int load_idx = inst->lqIdx; 4704032Sktlim@umich.edu incrLdIdx(load_idx); 4714032Sktlim@umich.edu while (load_idx != loadTail) { 4724032Sktlim@umich.edu // Really only need to check loads that have actually executed 4734032Sktlim@umich.edu 4744032Sktlim@umich.edu // @todo: For now this is extra conservative, detecting a 4754032Sktlim@umich.edu // violation if the addresses match assuming all accesses 4764032Sktlim@umich.edu // are quad word accesses. 4774032Sktlim@umich.edu 4784032Sktlim@umich.edu // @todo: Fix this, magic number being used here 4794032Sktlim@umich.edu if (loadQueue[load_idx]->effAddrValid && 4804032Sktlim@umich.edu (loadQueue[load_idx]->effAddr >> 8) == 4814032Sktlim@umich.edu (inst->effAddr >> 8)) { 4824032Sktlim@umich.edu // A load incorrectly passed this load. Squash and refetch. 4834032Sktlim@umich.edu // For now return a fault to show that it was unsuccessful. 4844032Sktlim@umich.edu DynInstPtr violator = loadQueue[load_idx]; 4854032Sktlim@umich.edu if (!memDepViolator || 4864032Sktlim@umich.edu (violator->seqNum < memDepViolator->seqNum)) { 4874032Sktlim@umich.edu memDepViolator = violator; 4884032Sktlim@umich.edu } else { 4894032Sktlim@umich.edu break; 4904032Sktlim@umich.edu } 4914032Sktlim@umich.edu 4924032Sktlim@umich.edu ++lsqMemOrderViolation; 4934032Sktlim@umich.edu 4944032Sktlim@umich.edu return genMachineCheckFault(); 4954032Sktlim@umich.edu } 4964032Sktlim@umich.edu 4974032Sktlim@umich.edu incrLdIdx(load_idx); 4984032Sktlim@umich.edu } 4992292SN/A } 5002292SN/A 5012292SN/A return load_fault; 5022292SN/A} 5032292SN/A 5042292SN/Atemplate <class Impl> 5052292SN/AFault 5062292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 5072292SN/A{ 5082292SN/A using namespace TheISA; 5092292SN/A // Make sure that a store exists. 5102292SN/A assert(stores != 0); 5112292SN/A 5122292SN/A int store_idx = store_inst->sqIdx; 5132292SN/A 5142292SN/A DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n", 5152292SN/A store_inst->readPC(), store_inst->seqNum); 5162292SN/A 5174032Sktlim@umich.edu assert(!store_inst->isSquashed()); 5184032Sktlim@umich.edu 5192292SN/A // Check the recently completed loads to see if any match this store's 5202292SN/A // address. If so, then we have a memory ordering violation. 5212292SN/A int load_idx = store_inst->lqIdx; 5222292SN/A 5232292SN/A Fault store_fault = store_inst->initiateAcc(); 5242292SN/A 5252329SN/A if (storeQueue[store_idx].size == 0) { 5262292SN/A DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n", 5272292SN/A store_inst->readPC(),store_inst->seqNum); 5282292SN/A 5292292SN/A return store_fault; 5302292SN/A } 5312292SN/A 5322292SN/A assert(store_fault == NoFault); 5332292SN/A 5342336SN/A if (store_inst->isStoreConditional()) { 5352336SN/A // Store conditionals need to set themselves as able to 5362336SN/A // writeback if we haven't had a fault by here. 5372329SN/A storeQueue[store_idx].canWB = true; 5382292SN/A 5392329SN/A ++storesToWB; 5402292SN/A } 5412292SN/A 5424032Sktlim@umich.edu assert(store_inst->effAddrValid); 5434032Sktlim@umich.edu while (load_idx != loadTail) { 5444032Sktlim@umich.edu // Really only need to check loads that have actually executed 5454032Sktlim@umich.edu // It's safe to check all loads because effAddr is set to 5464032Sktlim@umich.edu // InvalAddr when the dyn inst is created. 5472292SN/A 5484032Sktlim@umich.edu // @todo: For now this is extra conservative, detecting a 5494032Sktlim@umich.edu // violation if the addresses match assuming all accesses 5504032Sktlim@umich.edu // are quad word accesses. 5512329SN/A 5524032Sktlim@umich.edu // @todo: Fix this, magic number being used here 5534032Sktlim@umich.edu if (loadQueue[load_idx]->effAddrValid && 5544032Sktlim@umich.edu (loadQueue[load_idx]->effAddr >> 8) == 5554032Sktlim@umich.edu (store_inst->effAddr >> 8)) { 5564032Sktlim@umich.edu // A load incorrectly passed this store. Squash and refetch. 5574032Sktlim@umich.edu // For now return a fault to show that it was unsuccessful. 5584032Sktlim@umich.edu DynInstPtr violator = loadQueue[load_idx]; 5594032Sktlim@umich.edu if (!memDepViolator || 5604032Sktlim@umich.edu (violator->seqNum < memDepViolator->seqNum)) { 5614032Sktlim@umich.edu memDepViolator = violator; 5624032Sktlim@umich.edu } else { 5634032Sktlim@umich.edu break; 5642292SN/A } 5652292SN/A 5664032Sktlim@umich.edu ++lsqMemOrderViolation; 5674032Sktlim@umich.edu 5684032Sktlim@umich.edu return genMachineCheckFault(); 5692292SN/A } 5702292SN/A 5714032Sktlim@umich.edu incrLdIdx(load_idx); 5722292SN/A } 5732292SN/A 5742292SN/A return store_fault; 5752292SN/A} 5762292SN/A 5772292SN/Atemplate <class Impl> 5782292SN/Avoid 5792292SN/ALSQUnit<Impl>::commitLoad() 5802292SN/A{ 5812292SN/A assert(loadQueue[loadHead]); 5822292SN/A 5832292SN/A DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n", 5842292SN/A loadQueue[loadHead]->readPC()); 5852292SN/A 5862292SN/A loadQueue[loadHead] = NULL; 5872292SN/A 5882292SN/A incrLdIdx(loadHead); 5892292SN/A 5902292SN/A --loads; 5912292SN/A} 5922292SN/A 5932292SN/Atemplate <class Impl> 5942292SN/Avoid 5952292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 5962292SN/A{ 5972292SN/A assert(loads == 0 || loadQueue[loadHead]); 5982292SN/A 5992292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 6002292SN/A commitLoad(); 6012292SN/A } 6022292SN/A} 6032292SN/A 6042292SN/Atemplate <class Impl> 6052292SN/Avoid 6062292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 6072292SN/A{ 6082292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 6092292SN/A 6102292SN/A int store_idx = storeHead; 6112292SN/A 6122292SN/A while (store_idx != storeTail) { 6132292SN/A assert(storeQueue[store_idx].inst); 6142329SN/A // Mark any stores that are now committed and have not yet 6152329SN/A // been marked as able to write back. 6162292SN/A if (!storeQueue[store_idx].canWB) { 6172292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 6182292SN/A break; 6192292SN/A } 6202292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 6212292SN/A "%#x [sn:%lli]\n", 6222292SN/A storeQueue[store_idx].inst->readPC(), 6232292SN/A storeQueue[store_idx].inst->seqNum); 6242292SN/A 6252292SN/A storeQueue[store_idx].canWB = true; 6262292SN/A 6272292SN/A ++storesToWB; 6282292SN/A } 6292292SN/A 6302292SN/A incrStIdx(store_idx); 6312292SN/A } 6322292SN/A} 6332292SN/A 6342292SN/Atemplate <class Impl> 6352292SN/Avoid 6366974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::writebackPendingStore() 6376974Stjones1@inf.ed.ac.uk{ 6386974Stjones1@inf.ed.ac.uk if (hasPendingPkt) { 6396974Stjones1@inf.ed.ac.uk assert(pendingPkt != NULL); 6406974Stjones1@inf.ed.ac.uk 6416974Stjones1@inf.ed.ac.uk // If the cache is blocked, this will store the packet for retry. 6426974Stjones1@inf.ed.ac.uk if (sendStore(pendingPkt)) { 6436974Stjones1@inf.ed.ac.uk storePostSend(pendingPkt); 6446974Stjones1@inf.ed.ac.uk } 6456974Stjones1@inf.ed.ac.uk pendingPkt = NULL; 6466974Stjones1@inf.ed.ac.uk hasPendingPkt = false; 6476974Stjones1@inf.ed.ac.uk } 6486974Stjones1@inf.ed.ac.uk} 6496974Stjones1@inf.ed.ac.uk 6506974Stjones1@inf.ed.ac.uktemplate <class Impl> 6516974Stjones1@inf.ed.ac.ukvoid 6522292SN/ALSQUnit<Impl>::writebackStores() 6532292SN/A{ 6546974Stjones1@inf.ed.ac.uk // First writeback the second packet from any split store that didn't 6556974Stjones1@inf.ed.ac.uk // complete last cycle because there weren't enough cache ports available. 6566974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc) { 6576974Stjones1@inf.ed.ac.uk writebackPendingStore(); 6586974Stjones1@inf.ed.ac.uk } 6596974Stjones1@inf.ed.ac.uk 6602292SN/A while (storesToWB > 0 && 6612292SN/A storeWBIdx != storeTail && 6622292SN/A storeQueue[storeWBIdx].inst && 6632292SN/A storeQueue[storeWBIdx].canWB && 6642292SN/A usedPorts < cachePorts) { 6652292SN/A 6662907Sktlim@umich.edu if (isStoreBlocked || lsq->cacheBlocked()) { 6672678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 6682678Sktlim@umich.edu " is blocked!\n"); 6692678Sktlim@umich.edu break; 6702678Sktlim@umich.edu } 6712678Sktlim@umich.edu 6722329SN/A // Store didn't write any data so no need to write it back to 6732329SN/A // memory. 6742292SN/A if (storeQueue[storeWBIdx].size == 0) { 6752292SN/A completeStore(storeWBIdx); 6762292SN/A 6772292SN/A incrStIdx(storeWBIdx); 6782292SN/A 6792292SN/A continue; 6802292SN/A } 6812678Sktlim@umich.edu 6822292SN/A ++usedPorts; 6832292SN/A 6842292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 6852292SN/A incrStIdx(storeWBIdx); 6862292SN/A 6872292SN/A continue; 6882292SN/A } 6892292SN/A 6902292SN/A assert(storeQueue[storeWBIdx].req); 6912292SN/A assert(!storeQueue[storeWBIdx].committed); 6922292SN/A 6936974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 6946974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqLow); 6956974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqHigh); 6966974Stjones1@inf.ed.ac.uk } 6976974Stjones1@inf.ed.ac.uk 6982669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 6992669Sktlim@umich.edu 7002669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 7012292SN/A storeQueue[storeWBIdx].committed = true; 7022292SN/A 7032669Sktlim@umich.edu assert(!inst->memData); 7042669Sktlim@umich.edu inst->memData = new uint8_t[64]; 7053772Sgblack@eecs.umich.edu 7064326Sgblack@eecs.umich.edu memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 7072669Sktlim@umich.edu 7084878Sstever@eecs.umich.edu MemCmd command = 7094878Sstever@eecs.umich.edu req->isSwap() ? MemCmd::SwapReq : 7106102Sgblack@eecs.umich.edu (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 7116974Stjones1@inf.ed.ac.uk PacketPtr data_pkt; 7126974Stjones1@inf.ed.ac.uk PacketPtr snd_data_pkt = NULL; 7132292SN/A 7142678Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 7152678Sktlim@umich.edu state->isLoad = false; 7162678Sktlim@umich.edu state->idx = storeWBIdx; 7172678Sktlim@umich.edu state->inst = inst; 7186974Stjones1@inf.ed.ac.uk 7196974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 7206974Stjones1@inf.ed.ac.uk 7216974Stjones1@inf.ed.ac.uk // Build a single data packet if the store isn't split. 7226974Stjones1@inf.ed.ac.uk data_pkt = new Packet(req, command, Packet::Broadcast); 7236974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 7246974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 7256974Stjones1@inf.ed.ac.uk } else { 7266974Stjones1@inf.ed.ac.uk RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 7276974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 7286974Stjones1@inf.ed.ac.uk 7296974Stjones1@inf.ed.ac.uk // Create two packets if the store is split in two. 7306974Stjones1@inf.ed.ac.uk data_pkt = new Packet(sreqLow, command, Packet::Broadcast); 7316974Stjones1@inf.ed.ac.uk snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast); 7326974Stjones1@inf.ed.ac.uk 7336974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 7346974Stjones1@inf.ed.ac.uk snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 7356974Stjones1@inf.ed.ac.uk 7366974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 7376974Stjones1@inf.ed.ac.uk snd_data_pkt->senderState = state; 7386974Stjones1@inf.ed.ac.uk 7396974Stjones1@inf.ed.ac.uk state->isSplit = true; 7406974Stjones1@inf.ed.ac.uk state->outstanding = 2; 7416974Stjones1@inf.ed.ac.uk 7426974Stjones1@inf.ed.ac.uk // Can delete the main request now. 7436974Stjones1@inf.ed.ac.uk delete req; 7446974Stjones1@inf.ed.ac.uk req = sreqLow; 7456974Stjones1@inf.ed.ac.uk } 7462678Sktlim@umich.edu 7472292SN/A DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " 7482292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 7493221Sktlim@umich.edu storeWBIdx, inst->readPC(), 7503797Sgblack@eecs.umich.edu req->getPaddr(), (int)*(inst->memData), 7513221Sktlim@umich.edu inst->seqNum); 7522292SN/A 7532693Sktlim@umich.edu // @todo: Remove this SC hack once the memory system handles it. 7544350Sgblack@eecs.umich.edu if (inst->isStoreConditional()) { 7556974Stjones1@inf.ed.ac.uk assert(!storeQueue[storeWBIdx].isSplit); 7563326Sktlim@umich.edu // Disable recording the result temporarily. Writing to 7573326Sktlim@umich.edu // misc regs normally updates the result, but this is not 7583326Sktlim@umich.edu // the desired behavior when handling store conditionals. 7593326Sktlim@umich.edu inst->recordResult = false; 7603326Sktlim@umich.edu bool success = TheISA::handleLockedWrite(inst.get(), req); 7613326Sktlim@umich.edu inst->recordResult = true; 7623326Sktlim@umich.edu 7633326Sktlim@umich.edu if (!success) { 7643326Sktlim@umich.edu // Instantly complete this store. 7653326Sktlim@umich.edu DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 7663326Sktlim@umich.edu "Instantly completing it.\n", 7673326Sktlim@umich.edu inst->seqNum); 7683326Sktlim@umich.edu WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 7695606Snate@binkert.org cpu->schedule(wb, curTick + 1); 7703326Sktlim@umich.edu completeStore(storeWBIdx); 7713326Sktlim@umich.edu incrStIdx(storeWBIdx); 7723326Sktlim@umich.edu continue; 7732693Sktlim@umich.edu } 7742693Sktlim@umich.edu } else { 7752693Sktlim@umich.edu // Non-store conditionals do not need a writeback. 7762693Sktlim@umich.edu state->noWB = true; 7772693Sktlim@umich.edu } 7782693Sktlim@umich.edu 7796974Stjones1@inf.ed.ac.uk if (!sendStore(data_pkt)) { 7804032Sktlim@umich.edu DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 7813221Sktlim@umich.edu "retry later\n", 7823221Sktlim@umich.edu inst->seqNum); 7836974Stjones1@inf.ed.ac.uk 7846974Stjones1@inf.ed.ac.uk // Need to store the second packet, if split. 7856974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 7866974Stjones1@inf.ed.ac.uk state->pktToSend = true; 7876974Stjones1@inf.ed.ac.uk state->pendingPacket = snd_data_pkt; 7886974Stjones1@inf.ed.ac.uk } 7892669Sktlim@umich.edu } else { 7906974Stjones1@inf.ed.ac.uk 7916974Stjones1@inf.ed.ac.uk // If split, try to send the second packet too 7926974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 7936974Stjones1@inf.ed.ac.uk assert(snd_data_pkt); 7946974Stjones1@inf.ed.ac.uk 7956974Stjones1@inf.ed.ac.uk // Ensure there are enough ports to use. 7966974Stjones1@inf.ed.ac.uk if (usedPorts < cachePorts) { 7976974Stjones1@inf.ed.ac.uk ++usedPorts; 7986974Stjones1@inf.ed.ac.uk if (sendStore(snd_data_pkt)) { 7996974Stjones1@inf.ed.ac.uk storePostSend(snd_data_pkt); 8006974Stjones1@inf.ed.ac.uk } else { 8016974Stjones1@inf.ed.ac.uk DPRINTF(IEW, "D-Cache became blocked when writing" 8026974Stjones1@inf.ed.ac.uk " [sn:%lli] second packet, will retry later\n", 8036974Stjones1@inf.ed.ac.uk inst->seqNum); 8046974Stjones1@inf.ed.ac.uk } 8056974Stjones1@inf.ed.ac.uk } else { 8066974Stjones1@inf.ed.ac.uk 8076974Stjones1@inf.ed.ac.uk // Store the packet for when there's free ports. 8086974Stjones1@inf.ed.ac.uk assert(pendingPkt == NULL); 8096974Stjones1@inf.ed.ac.uk pendingPkt = snd_data_pkt; 8106974Stjones1@inf.ed.ac.uk hasPendingPkt = true; 8116974Stjones1@inf.ed.ac.uk } 8126974Stjones1@inf.ed.ac.uk } else { 8136974Stjones1@inf.ed.ac.uk 8146974Stjones1@inf.ed.ac.uk // Not a split store. 8156974Stjones1@inf.ed.ac.uk storePostSend(data_pkt); 8166974Stjones1@inf.ed.ac.uk } 8172292SN/A } 8182292SN/A } 8192292SN/A 8202292SN/A // Not sure this should set it to 0. 8212292SN/A usedPorts = 0; 8222292SN/A 8232292SN/A assert(stores >= 0 && storesToWB >= 0); 8242292SN/A} 8252292SN/A 8262292SN/A/*template <class Impl> 8272292SN/Avoid 8282292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 8292292SN/A{ 8302292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 8312292SN/A mshrSeqNums.end(), 8322292SN/A seqNum); 8332292SN/A 8342292SN/A if (mshr_it != mshrSeqNums.end()) { 8352292SN/A mshrSeqNums.erase(mshr_it); 8362292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 8372292SN/A } 8382292SN/A}*/ 8392292SN/A 8402292SN/Atemplate <class Impl> 8412292SN/Avoid 8422292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 8432292SN/A{ 8442292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 8452329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 8462292SN/A 8472292SN/A int load_idx = loadTail; 8482292SN/A decrLdIdx(load_idx); 8492292SN/A 8502292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 8512292SN/A DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, " 8522292SN/A "[sn:%lli]\n", 8532292SN/A loadQueue[load_idx]->readPC(), 8542292SN/A loadQueue[load_idx]->seqNum); 8552292SN/A 8562292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 8572292SN/A stalled = false; 8582292SN/A stallingStoreIsn = 0; 8592292SN/A stallingLoadIdx = 0; 8602292SN/A } 8612292SN/A 8622329SN/A // Clear the smart pointer to make sure it is decremented. 8632731Sktlim@umich.edu loadQueue[load_idx]->setSquashed(); 8642292SN/A loadQueue[load_idx] = NULL; 8652292SN/A --loads; 8662292SN/A 8672292SN/A // Inefficient! 8682292SN/A loadTail = load_idx; 8692292SN/A 8702292SN/A decrLdIdx(load_idx); 8712727Sktlim@umich.edu ++lsqSquashedLoads; 8722292SN/A } 8732292SN/A 8742292SN/A if (isLoadBlocked) { 8752292SN/A if (squashed_num < blockedLoadSeqNum) { 8762292SN/A isLoadBlocked = false; 8772292SN/A loadBlockedHandled = false; 8782292SN/A blockedLoadSeqNum = 0; 8792292SN/A } 8802292SN/A } 8812292SN/A 8824032Sktlim@umich.edu if (memDepViolator && squashed_num < memDepViolator->seqNum) { 8834032Sktlim@umich.edu memDepViolator = NULL; 8844032Sktlim@umich.edu } 8854032Sktlim@umich.edu 8862292SN/A int store_idx = storeTail; 8872292SN/A decrStIdx(store_idx); 8882292SN/A 8892292SN/A while (stores != 0 && 8902292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 8912329SN/A // Instructions marked as can WB are already committed. 8922292SN/A if (storeQueue[store_idx].canWB) { 8932292SN/A break; 8942292SN/A } 8952292SN/A 8962292SN/A DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, " 8972292SN/A "idx:%i [sn:%lli]\n", 8982292SN/A storeQueue[store_idx].inst->readPC(), 8992292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 9002292SN/A 9012329SN/A // I don't think this can happen. It should have been cleared 9022329SN/A // by the stalling load. 9032292SN/A if (isStalled() && 9042292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 9052292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 9062292SN/A stalled = false; 9072292SN/A stallingStoreIsn = 0; 9082292SN/A } 9092292SN/A 9102329SN/A // Clear the smart pointer to make sure it is decremented. 9112731Sktlim@umich.edu storeQueue[store_idx].inst->setSquashed(); 9122292SN/A storeQueue[store_idx].inst = NULL; 9132292SN/A storeQueue[store_idx].canWB = 0; 9142292SN/A 9154032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 9164032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the proper 9174032Sktlim@umich.edu // place to really handle request deletes. 9184032Sktlim@umich.edu delete storeQueue[store_idx].req; 9196974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 9206974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqLow; 9216974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqHigh; 9226974Stjones1@inf.ed.ac.uk 9236974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqLow = NULL; 9246974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqHigh = NULL; 9256974Stjones1@inf.ed.ac.uk } 9264032Sktlim@umich.edu 9272292SN/A storeQueue[store_idx].req = NULL; 9282292SN/A --stores; 9292292SN/A 9302292SN/A // Inefficient! 9312292SN/A storeTail = store_idx; 9322292SN/A 9332292SN/A decrStIdx(store_idx); 9342727Sktlim@umich.edu ++lsqSquashedStores; 9352292SN/A } 9362292SN/A} 9372292SN/A 9382292SN/Atemplate <class Impl> 9392292SN/Avoid 9403349Sbinkertn@umich.eduLSQUnit<Impl>::storePostSend(PacketPtr pkt) 9412693Sktlim@umich.edu{ 9422693Sktlim@umich.edu if (isStalled() && 9432693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 9442693Sktlim@umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 9452693Sktlim@umich.edu "load idx:%i\n", 9462693Sktlim@umich.edu stallingStoreIsn, stallingLoadIdx); 9472693Sktlim@umich.edu stalled = false; 9482693Sktlim@umich.edu stallingStoreIsn = 0; 9492693Sktlim@umich.edu iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 9502693Sktlim@umich.edu } 9512693Sktlim@umich.edu 9522693Sktlim@umich.edu if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 9532693Sktlim@umich.edu // The store is basically completed at this time. This 9542693Sktlim@umich.edu // only works so long as the checker doesn't try to 9552693Sktlim@umich.edu // verify the value in memory for stores. 9562693Sktlim@umich.edu storeQueue[storeWBIdx].inst->setCompleted(); 9572733Sktlim@umich.edu#if USE_CHECKER 9582693Sktlim@umich.edu if (cpu->checker) { 9592732Sktlim@umich.edu cpu->checker->verify(storeQueue[storeWBIdx].inst); 9602693Sktlim@umich.edu } 9612733Sktlim@umich.edu#endif 9622693Sktlim@umich.edu } 9632693Sktlim@umich.edu 9642693Sktlim@umich.edu incrStIdx(storeWBIdx); 9652693Sktlim@umich.edu} 9662693Sktlim@umich.edu 9672693Sktlim@umich.edutemplate <class Impl> 9682693Sktlim@umich.eduvoid 9692678Sktlim@umich.eduLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 9702678Sktlim@umich.edu{ 9712678Sktlim@umich.edu iewStage->wakeCPU(); 9722678Sktlim@umich.edu 9732678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 9742678Sktlim@umich.edu if (inst->isSquashed()) { 9752927Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 9762678Sktlim@umich.edu assert(!inst->isStore()); 9772727Sktlim@umich.edu ++lsqIgnoredResponses; 9782678Sktlim@umich.edu return; 9792678Sktlim@umich.edu } 9802678Sktlim@umich.edu 9812678Sktlim@umich.edu if (!inst->isExecuted()) { 9822678Sktlim@umich.edu inst->setExecuted(); 9832678Sktlim@umich.edu 9842678Sktlim@umich.edu // Complete access to copy data to proper place. 9852678Sktlim@umich.edu inst->completeAcc(pkt); 9862678Sktlim@umich.edu } 9872678Sktlim@umich.edu 9882678Sktlim@umich.edu // Need to insert instruction into queue to commit 9892678Sktlim@umich.edu iewStage->instToCommit(inst); 9902678Sktlim@umich.edu 9912678Sktlim@umich.edu iewStage->activityThisCycle(); 9927598Sminkyu.jeong@arm.com 9937598Sminkyu.jeong@arm.com // see if this load changed the PC 9947598Sminkyu.jeong@arm.com iewStage->checkMisprediction(inst); 9952678Sktlim@umich.edu} 9962678Sktlim@umich.edu 9972678Sktlim@umich.edutemplate <class Impl> 9982678Sktlim@umich.eduvoid 9992292SN/ALSQUnit<Impl>::completeStore(int store_idx) 10002292SN/A{ 10012292SN/A assert(storeQueue[store_idx].inst); 10022292SN/A storeQueue[store_idx].completed = true; 10032292SN/A --storesToWB; 10042292SN/A // A bit conservative because a store completion may not free up entries, 10052292SN/A // but hopefully avoids two store completions in one cycle from making 10062292SN/A // the CPU tick twice. 10073126Sktlim@umich.edu cpu->wakeCPU(); 10082292SN/A cpu->activityThisCycle(); 10092292SN/A 10102292SN/A if (store_idx == storeHead) { 10112292SN/A do { 10122292SN/A incrStIdx(storeHead); 10132292SN/A 10142292SN/A --stores; 10152292SN/A } while (storeQueue[storeHead].completed && 10162292SN/A storeHead != storeTail); 10172292SN/A 10182292SN/A iewStage->updateLSQNextCycle = true; 10192292SN/A } 10202292SN/A 10212329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 10222329SN/A "idx:%i\n", 10232329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 10242292SN/A 10252292SN/A if (isStalled() && 10262292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 10272292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 10282292SN/A "load idx:%i\n", 10292292SN/A stallingStoreIsn, stallingLoadIdx); 10302292SN/A stalled = false; 10312292SN/A stallingStoreIsn = 0; 10322292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 10332292SN/A } 10342316SN/A 10352316SN/A storeQueue[store_idx].inst->setCompleted(); 10362329SN/A 10372329SN/A // Tell the checker we've completed this instruction. Some stores 10382329SN/A // may get reported twice to the checker, but the checker can 10392329SN/A // handle that case. 10402733Sktlim@umich.edu#if USE_CHECKER 10412316SN/A if (cpu->checker) { 10422732Sktlim@umich.edu cpu->checker->verify(storeQueue[store_idx].inst); 10432316SN/A } 10442733Sktlim@umich.edu#endif 10452292SN/A} 10462292SN/A 10472292SN/Atemplate <class Impl> 10486974Stjones1@inf.ed.ac.ukbool 10496974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::sendStore(PacketPtr data_pkt) 10506974Stjones1@inf.ed.ac.uk{ 10516974Stjones1@inf.ed.ac.uk if (!dcachePort->sendTiming(data_pkt)) { 10526974Stjones1@inf.ed.ac.uk // Need to handle becoming blocked on a store. 10536974Stjones1@inf.ed.ac.uk isStoreBlocked = true; 10546974Stjones1@inf.ed.ac.uk ++lsqCacheBlocked; 10556974Stjones1@inf.ed.ac.uk assert(retryPkt == NULL); 10566974Stjones1@inf.ed.ac.uk retryPkt = data_pkt; 10576974Stjones1@inf.ed.ac.uk lsq->setRetryTid(lsqID); 10586974Stjones1@inf.ed.ac.uk return false; 10596974Stjones1@inf.ed.ac.uk } 10606974Stjones1@inf.ed.ac.uk return true; 10616974Stjones1@inf.ed.ac.uk} 10626974Stjones1@inf.ed.ac.uk 10636974Stjones1@inf.ed.ac.uktemplate <class Impl> 10642693Sktlim@umich.eduvoid 10652693Sktlim@umich.eduLSQUnit<Impl>::recvRetry() 10662693Sktlim@umich.edu{ 10672698Sktlim@umich.edu if (isStoreBlocked) { 10684985Sktlim@umich.edu DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 10692698Sktlim@umich.edu assert(retryPkt != NULL); 10702693Sktlim@umich.edu 10712698Sktlim@umich.edu if (dcachePort->sendTiming(retryPkt)) { 10726974Stjones1@inf.ed.ac.uk LSQSenderState *state = 10736974Stjones1@inf.ed.ac.uk dynamic_cast<LSQSenderState *>(retryPkt->senderState); 10746974Stjones1@inf.ed.ac.uk 10756974Stjones1@inf.ed.ac.uk // Don't finish the store unless this is the last packet. 10766974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !state->pktToSend) { 10776974Stjones1@inf.ed.ac.uk storePostSend(retryPkt); 10786974Stjones1@inf.ed.ac.uk } 10792699Sktlim@umich.edu retryPkt = NULL; 10802693Sktlim@umich.edu isStoreBlocked = false; 10816221Snate@binkert.org lsq->setRetryTid(InvalidThreadID); 10826974Stjones1@inf.ed.ac.uk 10836974Stjones1@inf.ed.ac.uk // Send any outstanding packet. 10846974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 10856974Stjones1@inf.ed.ac.uk assert(state->pendingPacket); 10866974Stjones1@inf.ed.ac.uk if (sendStore(state->pendingPacket)) { 10876974Stjones1@inf.ed.ac.uk storePostSend(state->pendingPacket); 10886974Stjones1@inf.ed.ac.uk } 10896974Stjones1@inf.ed.ac.uk } 10902693Sktlim@umich.edu } else { 10912693Sktlim@umich.edu // Still blocked! 10922727Sktlim@umich.edu ++lsqCacheBlocked; 10932907Sktlim@umich.edu lsq->setRetryTid(lsqID); 10942693Sktlim@umich.edu } 10952693Sktlim@umich.edu } else if (isLoadBlocked) { 10962693Sktlim@umich.edu DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 10972693Sktlim@umich.edu "no need to resend packet.\n"); 10982693Sktlim@umich.edu } else { 10992693Sktlim@umich.edu DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 11002693Sktlim@umich.edu } 11012693Sktlim@umich.edu} 11022693Sktlim@umich.edu 11032693Sktlim@umich.edutemplate <class Impl> 11042292SN/Ainline void 11052292SN/ALSQUnit<Impl>::incrStIdx(int &store_idx) 11062292SN/A{ 11072292SN/A if (++store_idx >= SQEntries) 11082292SN/A store_idx = 0; 11092292SN/A} 11102292SN/A 11112292SN/Atemplate <class Impl> 11122292SN/Ainline void 11132292SN/ALSQUnit<Impl>::decrStIdx(int &store_idx) 11142292SN/A{ 11152292SN/A if (--store_idx < 0) 11162292SN/A store_idx += SQEntries; 11172292SN/A} 11182292SN/A 11192292SN/Atemplate <class Impl> 11202292SN/Ainline void 11212292SN/ALSQUnit<Impl>::incrLdIdx(int &load_idx) 11222292SN/A{ 11232292SN/A if (++load_idx >= LQEntries) 11242292SN/A load_idx = 0; 11252292SN/A} 11262292SN/A 11272292SN/Atemplate <class Impl> 11282292SN/Ainline void 11292292SN/ALSQUnit<Impl>::decrLdIdx(int &load_idx) 11302292SN/A{ 11312292SN/A if (--load_idx < 0) 11322292SN/A load_idx += LQEntries; 11332292SN/A} 11342329SN/A 11352329SN/Atemplate <class Impl> 11362329SN/Avoid 11372329SN/ALSQUnit<Impl>::dumpInsts() 11382329SN/A{ 11392329SN/A cprintf("Load store queue: Dumping instructions.\n"); 11402329SN/A cprintf("Load queue size: %i\n", loads); 11412329SN/A cprintf("Load queue: "); 11422329SN/A 11432329SN/A int load_idx = loadHead; 11442329SN/A 11452329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 11462329SN/A cprintf("%#x ", loadQueue[load_idx]->readPC()); 11472329SN/A 11482329SN/A incrLdIdx(load_idx); 11492329SN/A } 11502329SN/A 11512329SN/A cprintf("Store queue size: %i\n", stores); 11522329SN/A cprintf("Store queue: "); 11532329SN/A 11542329SN/A int store_idx = storeHead; 11552329SN/A 11562329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 11572329SN/A cprintf("%#x ", storeQueue[store_idx].inst->readPC()); 11582329SN/A 11592329SN/A incrStIdx(store_idx); 11602329SN/A } 11612329SN/A 11622329SN/A cprintf("\n"); 11632329SN/A} 1164