lsq_unit_impl.hh revision 6974
12292SN/A/* 22292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32292SN/A * All rights reserved. 42292SN/A * 52292SN/A * Redistribution and use in source and binary forms, with or without 62292SN/A * modification, are permitted provided that the following conditions are 72292SN/A * met: redistributions of source code must retain the above copyright 82292SN/A * notice, this list of conditions and the following disclaimer; 92292SN/A * redistributions in binary form must reproduce the above copyright 102292SN/A * notice, this list of conditions and the following disclaimer in the 112292SN/A * documentation and/or other materials provided with the distribution; 122292SN/A * neither the name of the copyright holders nor the names of its 132292SN/A * contributors may be used to endorse or promote products derived from 142292SN/A * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292689Sktlim@umich.edu * Korey Sewell 302292SN/A */ 312292SN/A 323326Sktlim@umich.edu#include "arch/locked_mem.hh" 336658Snate@binkert.org#include "config/the_isa.hh" 342733Sktlim@umich.edu#include "config/use_checker.hh" 352907Sktlim@umich.edu#include "cpu/o3/lsq.hh" 362292SN/A#include "cpu/o3/lsq_unit.hh" 372292SN/A#include "base/str.hh" 382722Sktlim@umich.edu#include "mem/packet.hh" 392669Sktlim@umich.edu#include "mem/request.hh" 402292SN/A 412790Sktlim@umich.edu#if USE_CHECKER 422790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 432790Sktlim@umich.edu#endif 442790Sktlim@umich.edu 452669Sktlim@umich.edutemplate<class Impl> 462678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 472678Sktlim@umich.edu LSQUnit *lsq_ptr) 485606Snate@binkert.org : inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 492292SN/A{ 502678Sktlim@umich.edu this->setFlags(Event::AutoDelete); 512292SN/A} 522292SN/A 532669Sktlim@umich.edutemplate<class Impl> 542292SN/Avoid 552678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 562292SN/A{ 572678Sktlim@umich.edu if (!lsqPtr->isSwitchedOut()) { 582678Sktlim@umich.edu lsqPtr->writeback(inst, pkt); 592678Sktlim@umich.edu } 604319Sktlim@umich.edu 614319Sktlim@umich.edu if (pkt->senderState) 624319Sktlim@umich.edu delete pkt->senderState; 634319Sktlim@umich.edu 644319Sktlim@umich.edu delete pkt->req; 652678Sktlim@umich.edu delete pkt; 662678Sktlim@umich.edu} 672292SN/A 682678Sktlim@umich.edutemplate<class Impl> 692678Sktlim@umich.educonst char * 705336Shines@cs.fsu.eduLSQUnit<Impl>::WritebackEvent::description() const 712678Sktlim@umich.edu{ 724873Sstever@eecs.umich.edu return "Store writeback"; 732678Sktlim@umich.edu} 742292SN/A 752678Sktlim@umich.edutemplate<class Impl> 762678Sktlim@umich.eduvoid 772678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 782678Sktlim@umich.edu{ 792678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 802678Sktlim@umich.edu DynInstPtr inst = state->inst; 812678Sktlim@umich.edu DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum); 822698Sktlim@umich.edu DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum); 832344SN/A 842678Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 852678Sktlim@umich.edu 864986Ssaidi@eecs.umich.edu assert(!pkt->wasNacked()); 874986Ssaidi@eecs.umich.edu 886974Stjones1@inf.ed.ac.uk // If this is a split access, wait until all packets are received. 896974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && !state->complete()) { 906974Stjones1@inf.ed.ac.uk delete pkt->req; 916974Stjones1@inf.ed.ac.uk delete pkt; 926974Stjones1@inf.ed.ac.uk return; 936974Stjones1@inf.ed.ac.uk } 946974Stjones1@inf.ed.ac.uk 952678Sktlim@umich.edu if (isSwitchedOut() || inst->isSquashed()) { 962820Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 972678Sktlim@umich.edu } else { 982678Sktlim@umich.edu if (!state->noWB) { 996974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 1006974Stjones1@inf.ed.ac.uk !state->isLoad) { 1016974Stjones1@inf.ed.ac.uk writeback(inst, pkt); 1026974Stjones1@inf.ed.ac.uk } else { 1036974Stjones1@inf.ed.ac.uk writeback(inst, state->mainPkt); 1046974Stjones1@inf.ed.ac.uk } 1052678Sktlim@umich.edu } 1062678Sktlim@umich.edu 1072678Sktlim@umich.edu if (inst->isStore()) { 1082678Sktlim@umich.edu completeStore(state->idx); 1092678Sktlim@umich.edu } 1102344SN/A } 1112307SN/A 1126974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 1136974Stjones1@inf.ed.ac.uk delete state->mainPkt->req; 1146974Stjones1@inf.ed.ac.uk delete state->mainPkt; 1156974Stjones1@inf.ed.ac.uk } 1162678Sktlim@umich.edu delete state; 1174032Sktlim@umich.edu delete pkt->req; 1182678Sktlim@umich.edu delete pkt; 1192292SN/A} 1202292SN/A 1212292SN/Atemplate <class Impl> 1222292SN/ALSQUnit<Impl>::LSQUnit() 1232678Sktlim@umich.edu : loads(0), stores(0), storesToWB(0), stalled(false), 1242678Sktlim@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1256974Stjones1@inf.ed.ac.uk loadBlockedHandled(false), hasPendingPkt(false) 1262292SN/A{ 1272292SN/A} 1282292SN/A 1292292SN/Atemplate<class Impl> 1302292SN/Avoid 1315529Snate@binkert.orgLSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 1325529Snate@binkert.org LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 1335529Snate@binkert.org unsigned id) 1342292SN/A{ 1354329Sktlim@umich.edu cpu = cpu_ptr; 1364329Sktlim@umich.edu iewStage = iew_ptr; 1374329Sktlim@umich.edu 1384329Sktlim@umich.edu DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1392292SN/A 1402307SN/A switchedOut = false; 1412307SN/A 1422907Sktlim@umich.edu lsq = lsq_ptr; 1432907Sktlim@umich.edu 1442292SN/A lsqID = id; 1452292SN/A 1462329SN/A // Add 1 for the sentinel entry (they are circular queues). 1472329SN/A LQEntries = maxLQEntries + 1; 1482329SN/A SQEntries = maxSQEntries + 1; 1492292SN/A 1502292SN/A loadQueue.resize(LQEntries); 1512292SN/A storeQueue.resize(SQEntries); 1522292SN/A 1532292SN/A loadHead = loadTail = 0; 1542292SN/A 1552292SN/A storeHead = storeWBIdx = storeTail = 0; 1562292SN/A 1572292SN/A usedPorts = 0; 1582292SN/A cachePorts = params->cachePorts; 1592292SN/A 1603492Sktlim@umich.edu retryPkt = NULL; 1612329SN/A memDepViolator = NULL; 1622292SN/A 1632292SN/A blockedLoadSeqNum = 0; 1642292SN/A} 1652292SN/A 1662292SN/Atemplate<class Impl> 1672292SN/Astd::string 1682292SN/ALSQUnit<Impl>::name() const 1692292SN/A{ 1702292SN/A if (Impl::MaxThreads == 1) { 1712292SN/A return iewStage->name() + ".lsq"; 1722292SN/A } else { 1732292SN/A return iewStage->name() + ".lsq.thread." + to_string(lsqID); 1742292SN/A } 1752292SN/A} 1762292SN/A 1772292SN/Atemplate<class Impl> 1782292SN/Avoid 1792727Sktlim@umich.eduLSQUnit<Impl>::regStats() 1802727Sktlim@umich.edu{ 1812727Sktlim@umich.edu lsqForwLoads 1822727Sktlim@umich.edu .name(name() + ".forwLoads") 1832727Sktlim@umich.edu .desc("Number of loads that had data forwarded from stores"); 1842727Sktlim@umich.edu 1852727Sktlim@umich.edu invAddrLoads 1862727Sktlim@umich.edu .name(name() + ".invAddrLoads") 1872727Sktlim@umich.edu .desc("Number of loads ignored due to an invalid address"); 1882727Sktlim@umich.edu 1892727Sktlim@umich.edu lsqSquashedLoads 1902727Sktlim@umich.edu .name(name() + ".squashedLoads") 1912727Sktlim@umich.edu .desc("Number of loads squashed"); 1922727Sktlim@umich.edu 1932727Sktlim@umich.edu lsqIgnoredResponses 1942727Sktlim@umich.edu .name(name() + ".ignoredResponses") 1952727Sktlim@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 1962727Sktlim@umich.edu 1972361SN/A lsqMemOrderViolation 1982361SN/A .name(name() + ".memOrderViolation") 1992361SN/A .desc("Number of memory ordering violations"); 2002361SN/A 2012727Sktlim@umich.edu lsqSquashedStores 2022727Sktlim@umich.edu .name(name() + ".squashedStores") 2032727Sktlim@umich.edu .desc("Number of stores squashed"); 2042727Sktlim@umich.edu 2052727Sktlim@umich.edu invAddrSwpfs 2062727Sktlim@umich.edu .name(name() + ".invAddrSwpfs") 2072727Sktlim@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 2082727Sktlim@umich.edu 2092727Sktlim@umich.edu lsqBlockedLoads 2102727Sktlim@umich.edu .name(name() + ".blockedLoads") 2112727Sktlim@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 2122727Sktlim@umich.edu 2132727Sktlim@umich.edu lsqRescheduledLoads 2142727Sktlim@umich.edu .name(name() + ".rescheduledLoads") 2152727Sktlim@umich.edu .desc("Number of loads that were rescheduled"); 2162727Sktlim@umich.edu 2172727Sktlim@umich.edu lsqCacheBlocked 2182727Sktlim@umich.edu .name(name() + ".cacheBlocked") 2192727Sktlim@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2202727Sktlim@umich.edu} 2212727Sktlim@umich.edu 2222727Sktlim@umich.edutemplate<class Impl> 2232727Sktlim@umich.eduvoid 2244329Sktlim@umich.eduLSQUnit<Impl>::setDcachePort(Port *dcache_port) 2254329Sktlim@umich.edu{ 2264329Sktlim@umich.edu dcachePort = dcache_port; 2274329Sktlim@umich.edu 2284329Sktlim@umich.edu#if USE_CHECKER 2294329Sktlim@umich.edu if (cpu->checker) { 2304329Sktlim@umich.edu cpu->checker->setDcachePort(dcachePort); 2314329Sktlim@umich.edu } 2324329Sktlim@umich.edu#endif 2334329Sktlim@umich.edu} 2344329Sktlim@umich.edu 2354329Sktlim@umich.edutemplate<class Impl> 2364329Sktlim@umich.eduvoid 2372292SN/ALSQUnit<Impl>::clearLQ() 2382292SN/A{ 2392292SN/A loadQueue.clear(); 2402292SN/A} 2412292SN/A 2422292SN/Atemplate<class Impl> 2432292SN/Avoid 2442292SN/ALSQUnit<Impl>::clearSQ() 2452292SN/A{ 2462292SN/A storeQueue.clear(); 2472292SN/A} 2482292SN/A 2492292SN/Atemplate<class Impl> 2502292SN/Avoid 2512307SN/ALSQUnit<Impl>::switchOut() 2522307SN/A{ 2532307SN/A switchedOut = true; 2542367SN/A for (int i = 0; i < loadQueue.size(); ++i) { 2552367SN/A assert(!loadQueue[i]); 2562307SN/A loadQueue[i] = NULL; 2572367SN/A } 2582307SN/A 2592329SN/A assert(storesToWB == 0); 2602307SN/A} 2612307SN/A 2622307SN/Atemplate<class Impl> 2632307SN/Avoid 2642307SN/ALSQUnit<Impl>::takeOverFrom() 2652307SN/A{ 2662307SN/A switchedOut = false; 2672307SN/A loads = stores = storesToWB = 0; 2682307SN/A 2692307SN/A loadHead = loadTail = 0; 2702307SN/A 2712307SN/A storeHead = storeWBIdx = storeTail = 0; 2722307SN/A 2732307SN/A usedPorts = 0; 2742307SN/A 2752329SN/A memDepViolator = NULL; 2762307SN/A 2772307SN/A blockedLoadSeqNum = 0; 2782307SN/A 2792307SN/A stalled = false; 2802307SN/A isLoadBlocked = false; 2812307SN/A loadBlockedHandled = false; 2822307SN/A} 2832307SN/A 2842307SN/Atemplate<class Impl> 2852307SN/Avoid 2862292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 2872292SN/A{ 2882329SN/A unsigned size_plus_sentinel = size + 1; 2892329SN/A assert(size_plus_sentinel >= LQEntries); 2902292SN/A 2912329SN/A if (size_plus_sentinel > LQEntries) { 2922329SN/A while (size_plus_sentinel > loadQueue.size()) { 2932292SN/A DynInstPtr dummy; 2942292SN/A loadQueue.push_back(dummy); 2952292SN/A LQEntries++; 2962292SN/A } 2972292SN/A } else { 2982329SN/A LQEntries = size_plus_sentinel; 2992292SN/A } 3002292SN/A 3012292SN/A} 3022292SN/A 3032292SN/Atemplate<class Impl> 3042292SN/Avoid 3052292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 3062292SN/A{ 3072329SN/A unsigned size_plus_sentinel = size + 1; 3082329SN/A if (size_plus_sentinel > SQEntries) { 3092329SN/A while (size_plus_sentinel > storeQueue.size()) { 3102292SN/A SQEntry dummy; 3112292SN/A storeQueue.push_back(dummy); 3122292SN/A SQEntries++; 3132292SN/A } 3142292SN/A } else { 3152329SN/A SQEntries = size_plus_sentinel; 3162292SN/A } 3172292SN/A} 3182292SN/A 3192292SN/Atemplate <class Impl> 3202292SN/Avoid 3212292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 3222292SN/A{ 3232292SN/A assert(inst->isMemRef()); 3242292SN/A 3252292SN/A assert(inst->isLoad() || inst->isStore()); 3262292SN/A 3272292SN/A if (inst->isLoad()) { 3282292SN/A insertLoad(inst); 3292292SN/A } else { 3302292SN/A insertStore(inst); 3312292SN/A } 3322292SN/A 3332292SN/A inst->setInLSQ(); 3342292SN/A} 3352292SN/A 3362292SN/Atemplate <class Impl> 3372292SN/Avoid 3382292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3392292SN/A{ 3402329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3412329SN/A assert(loads < LQEntries); 3422292SN/A 3432292SN/A DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n", 3442292SN/A load_inst->readPC(), loadTail, load_inst->seqNum); 3452292SN/A 3462292SN/A load_inst->lqIdx = loadTail; 3472292SN/A 3482292SN/A if (stores == 0) { 3492292SN/A load_inst->sqIdx = -1; 3502292SN/A } else { 3512292SN/A load_inst->sqIdx = storeTail; 3522292SN/A } 3532292SN/A 3542292SN/A loadQueue[loadTail] = load_inst; 3552292SN/A 3562292SN/A incrLdIdx(loadTail); 3572292SN/A 3582292SN/A ++loads; 3592292SN/A} 3602292SN/A 3612292SN/Atemplate <class Impl> 3622292SN/Avoid 3632292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3642292SN/A{ 3652292SN/A // Make sure it is not full before inserting an instruction. 3662292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3672292SN/A assert(stores < SQEntries); 3682292SN/A 3692292SN/A DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n", 3702292SN/A store_inst->readPC(), storeTail, store_inst->seqNum); 3712292SN/A 3722292SN/A store_inst->sqIdx = storeTail; 3732292SN/A store_inst->lqIdx = loadTail; 3742292SN/A 3752292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3762292SN/A 3772292SN/A incrStIdx(storeTail); 3782292SN/A 3792292SN/A ++stores; 3802292SN/A} 3812292SN/A 3822292SN/Atemplate <class Impl> 3832292SN/Atypename Impl::DynInstPtr 3842292SN/ALSQUnit<Impl>::getMemDepViolator() 3852292SN/A{ 3862292SN/A DynInstPtr temp = memDepViolator; 3872292SN/A 3882292SN/A memDepViolator = NULL; 3892292SN/A 3902292SN/A return temp; 3912292SN/A} 3922292SN/A 3932292SN/Atemplate <class Impl> 3942292SN/Aunsigned 3952292SN/ALSQUnit<Impl>::numFreeEntries() 3962292SN/A{ 3972292SN/A unsigned free_lq_entries = LQEntries - loads; 3982292SN/A unsigned free_sq_entries = SQEntries - stores; 3992292SN/A 4002292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 4012292SN/A // empty/full conditions. Subtract 1 from the free entries. 4022292SN/A if (free_lq_entries < free_sq_entries) { 4032292SN/A return free_lq_entries - 1; 4042292SN/A } else { 4052292SN/A return free_sq_entries - 1; 4062292SN/A } 4072292SN/A} 4082292SN/A 4092292SN/Atemplate <class Impl> 4102292SN/Aint 4112292SN/ALSQUnit<Impl>::numLoadsReady() 4122292SN/A{ 4132292SN/A int load_idx = loadHead; 4142292SN/A int retval = 0; 4152292SN/A 4162292SN/A while (load_idx != loadTail) { 4172292SN/A assert(loadQueue[load_idx]); 4182292SN/A 4192292SN/A if (loadQueue[load_idx]->readyToIssue()) { 4202292SN/A ++retval; 4212292SN/A } 4222292SN/A } 4232292SN/A 4242292SN/A return retval; 4252292SN/A} 4262292SN/A 4272292SN/Atemplate <class Impl> 4282292SN/AFault 4292292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 4302292SN/A{ 4314032Sktlim@umich.edu using namespace TheISA; 4322292SN/A // Execute a specific load. 4332292SN/A Fault load_fault = NoFault; 4342292SN/A 4352292SN/A DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n", 4362292SN/A inst->readPC(),inst->seqNum); 4372292SN/A 4384032Sktlim@umich.edu assert(!inst->isSquashed()); 4394032Sktlim@umich.edu 4402669Sktlim@umich.edu load_fault = inst->initiateAcc(); 4412292SN/A 4422292SN/A // If the instruction faulted, then we need to send it along to commit 4432292SN/A // without the instruction completing. 4442292SN/A if (load_fault != NoFault) { 4452329SN/A // Send this instruction to commit, also make sure iew stage 4462329SN/A // realizes there is activity. 4472367SN/A // Mark it as executed unless it is an uncached load that 4482367SN/A // needs to hit the head of commit. 4494032Sktlim@umich.edu if (!(inst->hasRequest() && inst->uncacheable()) || 4503731Sktlim@umich.edu inst->isAtCommit()) { 4512367SN/A inst->setExecuted(); 4522367SN/A } 4532292SN/A iewStage->instToCommit(inst); 4542292SN/A iewStage->activityThisCycle(); 4554032Sktlim@umich.edu } else if (!loadBlocked()) { 4564032Sktlim@umich.edu assert(inst->effAddrValid); 4574032Sktlim@umich.edu int load_idx = inst->lqIdx; 4584032Sktlim@umich.edu incrLdIdx(load_idx); 4594032Sktlim@umich.edu while (load_idx != loadTail) { 4604032Sktlim@umich.edu // Really only need to check loads that have actually executed 4614032Sktlim@umich.edu 4624032Sktlim@umich.edu // @todo: For now this is extra conservative, detecting a 4634032Sktlim@umich.edu // violation if the addresses match assuming all accesses 4644032Sktlim@umich.edu // are quad word accesses. 4654032Sktlim@umich.edu 4664032Sktlim@umich.edu // @todo: Fix this, magic number being used here 4674032Sktlim@umich.edu if (loadQueue[load_idx]->effAddrValid && 4684032Sktlim@umich.edu (loadQueue[load_idx]->effAddr >> 8) == 4694032Sktlim@umich.edu (inst->effAddr >> 8)) { 4704032Sktlim@umich.edu // A load incorrectly passed this load. Squash and refetch. 4714032Sktlim@umich.edu // For now return a fault to show that it was unsuccessful. 4724032Sktlim@umich.edu DynInstPtr violator = loadQueue[load_idx]; 4734032Sktlim@umich.edu if (!memDepViolator || 4744032Sktlim@umich.edu (violator->seqNum < memDepViolator->seqNum)) { 4754032Sktlim@umich.edu memDepViolator = violator; 4764032Sktlim@umich.edu } else { 4774032Sktlim@umich.edu break; 4784032Sktlim@umich.edu } 4794032Sktlim@umich.edu 4804032Sktlim@umich.edu ++lsqMemOrderViolation; 4814032Sktlim@umich.edu 4824032Sktlim@umich.edu return genMachineCheckFault(); 4834032Sktlim@umich.edu } 4844032Sktlim@umich.edu 4854032Sktlim@umich.edu incrLdIdx(load_idx); 4864032Sktlim@umich.edu } 4872292SN/A } 4882292SN/A 4892292SN/A return load_fault; 4902292SN/A} 4912292SN/A 4922292SN/Atemplate <class Impl> 4932292SN/AFault 4942292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 4952292SN/A{ 4962292SN/A using namespace TheISA; 4972292SN/A // Make sure that a store exists. 4982292SN/A assert(stores != 0); 4992292SN/A 5002292SN/A int store_idx = store_inst->sqIdx; 5012292SN/A 5022292SN/A DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n", 5032292SN/A store_inst->readPC(), store_inst->seqNum); 5042292SN/A 5054032Sktlim@umich.edu assert(!store_inst->isSquashed()); 5064032Sktlim@umich.edu 5072292SN/A // Check the recently completed loads to see if any match this store's 5082292SN/A // address. If so, then we have a memory ordering violation. 5092292SN/A int load_idx = store_inst->lqIdx; 5102292SN/A 5112292SN/A Fault store_fault = store_inst->initiateAcc(); 5122292SN/A 5132329SN/A if (storeQueue[store_idx].size == 0) { 5142292SN/A DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n", 5152292SN/A store_inst->readPC(),store_inst->seqNum); 5162292SN/A 5172292SN/A return store_fault; 5182292SN/A } 5192292SN/A 5202292SN/A assert(store_fault == NoFault); 5212292SN/A 5222336SN/A if (store_inst->isStoreConditional()) { 5232336SN/A // Store conditionals need to set themselves as able to 5242336SN/A // writeback if we haven't had a fault by here. 5252329SN/A storeQueue[store_idx].canWB = true; 5262292SN/A 5272329SN/A ++storesToWB; 5282292SN/A } 5292292SN/A 5304032Sktlim@umich.edu assert(store_inst->effAddrValid); 5314032Sktlim@umich.edu while (load_idx != loadTail) { 5324032Sktlim@umich.edu // Really only need to check loads that have actually executed 5334032Sktlim@umich.edu // It's safe to check all loads because effAddr is set to 5344032Sktlim@umich.edu // InvalAddr when the dyn inst is created. 5352292SN/A 5364032Sktlim@umich.edu // @todo: For now this is extra conservative, detecting a 5374032Sktlim@umich.edu // violation if the addresses match assuming all accesses 5384032Sktlim@umich.edu // are quad word accesses. 5392329SN/A 5404032Sktlim@umich.edu // @todo: Fix this, magic number being used here 5414032Sktlim@umich.edu if (loadQueue[load_idx]->effAddrValid && 5424032Sktlim@umich.edu (loadQueue[load_idx]->effAddr >> 8) == 5434032Sktlim@umich.edu (store_inst->effAddr >> 8)) { 5444032Sktlim@umich.edu // A load incorrectly passed this store. Squash and refetch. 5454032Sktlim@umich.edu // For now return a fault to show that it was unsuccessful. 5464032Sktlim@umich.edu DynInstPtr violator = loadQueue[load_idx]; 5474032Sktlim@umich.edu if (!memDepViolator || 5484032Sktlim@umich.edu (violator->seqNum < memDepViolator->seqNum)) { 5494032Sktlim@umich.edu memDepViolator = violator; 5504032Sktlim@umich.edu } else { 5514032Sktlim@umich.edu break; 5522292SN/A } 5532292SN/A 5544032Sktlim@umich.edu ++lsqMemOrderViolation; 5554032Sktlim@umich.edu 5564032Sktlim@umich.edu return genMachineCheckFault(); 5572292SN/A } 5582292SN/A 5594032Sktlim@umich.edu incrLdIdx(load_idx); 5602292SN/A } 5612292SN/A 5622292SN/A return store_fault; 5632292SN/A} 5642292SN/A 5652292SN/Atemplate <class Impl> 5662292SN/Avoid 5672292SN/ALSQUnit<Impl>::commitLoad() 5682292SN/A{ 5692292SN/A assert(loadQueue[loadHead]); 5702292SN/A 5712292SN/A DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n", 5722292SN/A loadQueue[loadHead]->readPC()); 5732292SN/A 5742292SN/A loadQueue[loadHead] = NULL; 5752292SN/A 5762292SN/A incrLdIdx(loadHead); 5772292SN/A 5782292SN/A --loads; 5792292SN/A} 5802292SN/A 5812292SN/Atemplate <class Impl> 5822292SN/Avoid 5832292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 5842292SN/A{ 5852292SN/A assert(loads == 0 || loadQueue[loadHead]); 5862292SN/A 5872292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 5882292SN/A commitLoad(); 5892292SN/A } 5902292SN/A} 5912292SN/A 5922292SN/Atemplate <class Impl> 5932292SN/Avoid 5942292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 5952292SN/A{ 5962292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 5972292SN/A 5982292SN/A int store_idx = storeHead; 5992292SN/A 6002292SN/A while (store_idx != storeTail) { 6012292SN/A assert(storeQueue[store_idx].inst); 6022329SN/A // Mark any stores that are now committed and have not yet 6032329SN/A // been marked as able to write back. 6042292SN/A if (!storeQueue[store_idx].canWB) { 6052292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 6062292SN/A break; 6072292SN/A } 6082292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 6092292SN/A "%#x [sn:%lli]\n", 6102292SN/A storeQueue[store_idx].inst->readPC(), 6112292SN/A storeQueue[store_idx].inst->seqNum); 6122292SN/A 6132292SN/A storeQueue[store_idx].canWB = true; 6142292SN/A 6152292SN/A ++storesToWB; 6162292SN/A } 6172292SN/A 6182292SN/A incrStIdx(store_idx); 6192292SN/A } 6202292SN/A} 6212292SN/A 6222292SN/Atemplate <class Impl> 6232292SN/Avoid 6246974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::writebackPendingStore() 6256974Stjones1@inf.ed.ac.uk{ 6266974Stjones1@inf.ed.ac.uk if (hasPendingPkt) { 6276974Stjones1@inf.ed.ac.uk assert(pendingPkt != NULL); 6286974Stjones1@inf.ed.ac.uk 6296974Stjones1@inf.ed.ac.uk // If the cache is blocked, this will store the packet for retry. 6306974Stjones1@inf.ed.ac.uk if (sendStore(pendingPkt)) { 6316974Stjones1@inf.ed.ac.uk storePostSend(pendingPkt); 6326974Stjones1@inf.ed.ac.uk } 6336974Stjones1@inf.ed.ac.uk pendingPkt = NULL; 6346974Stjones1@inf.ed.ac.uk hasPendingPkt = false; 6356974Stjones1@inf.ed.ac.uk } 6366974Stjones1@inf.ed.ac.uk} 6376974Stjones1@inf.ed.ac.uk 6386974Stjones1@inf.ed.ac.uktemplate <class Impl> 6396974Stjones1@inf.ed.ac.ukvoid 6402292SN/ALSQUnit<Impl>::writebackStores() 6412292SN/A{ 6426974Stjones1@inf.ed.ac.uk // First writeback the second packet from any split store that didn't 6436974Stjones1@inf.ed.ac.uk // complete last cycle because there weren't enough cache ports available. 6446974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc) { 6456974Stjones1@inf.ed.ac.uk writebackPendingStore(); 6466974Stjones1@inf.ed.ac.uk } 6476974Stjones1@inf.ed.ac.uk 6482292SN/A while (storesToWB > 0 && 6492292SN/A storeWBIdx != storeTail && 6502292SN/A storeQueue[storeWBIdx].inst && 6512292SN/A storeQueue[storeWBIdx].canWB && 6522292SN/A usedPorts < cachePorts) { 6532292SN/A 6542907Sktlim@umich.edu if (isStoreBlocked || lsq->cacheBlocked()) { 6552678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 6562678Sktlim@umich.edu " is blocked!\n"); 6572678Sktlim@umich.edu break; 6582678Sktlim@umich.edu } 6592678Sktlim@umich.edu 6602329SN/A // Store didn't write any data so no need to write it back to 6612329SN/A // memory. 6622292SN/A if (storeQueue[storeWBIdx].size == 0) { 6632292SN/A completeStore(storeWBIdx); 6642292SN/A 6652292SN/A incrStIdx(storeWBIdx); 6662292SN/A 6672292SN/A continue; 6682292SN/A } 6692678Sktlim@umich.edu 6702292SN/A ++usedPorts; 6712292SN/A 6722292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 6732292SN/A incrStIdx(storeWBIdx); 6742292SN/A 6752292SN/A continue; 6762292SN/A } 6772292SN/A 6782292SN/A assert(storeQueue[storeWBIdx].req); 6792292SN/A assert(!storeQueue[storeWBIdx].committed); 6802292SN/A 6816974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 6826974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqLow); 6836974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqHigh); 6846974Stjones1@inf.ed.ac.uk } 6856974Stjones1@inf.ed.ac.uk 6862669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 6872669Sktlim@umich.edu 6882669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 6892292SN/A storeQueue[storeWBIdx].committed = true; 6902292SN/A 6912669Sktlim@umich.edu assert(!inst->memData); 6922669Sktlim@umich.edu inst->memData = new uint8_t[64]; 6933772Sgblack@eecs.umich.edu 6944326Sgblack@eecs.umich.edu memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 6952669Sktlim@umich.edu 6964878Sstever@eecs.umich.edu MemCmd command = 6974878Sstever@eecs.umich.edu req->isSwap() ? MemCmd::SwapReq : 6986102Sgblack@eecs.umich.edu (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 6996974Stjones1@inf.ed.ac.uk PacketPtr data_pkt; 7006974Stjones1@inf.ed.ac.uk PacketPtr snd_data_pkt = NULL; 7012292SN/A 7022678Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 7032678Sktlim@umich.edu state->isLoad = false; 7042678Sktlim@umich.edu state->idx = storeWBIdx; 7052678Sktlim@umich.edu state->inst = inst; 7066974Stjones1@inf.ed.ac.uk 7076974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 7086974Stjones1@inf.ed.ac.uk 7096974Stjones1@inf.ed.ac.uk // Build a single data packet if the store isn't split. 7106974Stjones1@inf.ed.ac.uk data_pkt = new Packet(req, command, Packet::Broadcast); 7116974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 7126974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 7136974Stjones1@inf.ed.ac.uk } else { 7146974Stjones1@inf.ed.ac.uk RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 7156974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 7166974Stjones1@inf.ed.ac.uk 7176974Stjones1@inf.ed.ac.uk // Create two packets if the store is split in two. 7186974Stjones1@inf.ed.ac.uk data_pkt = new Packet(sreqLow, command, Packet::Broadcast); 7196974Stjones1@inf.ed.ac.uk snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast); 7206974Stjones1@inf.ed.ac.uk 7216974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 7226974Stjones1@inf.ed.ac.uk snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 7236974Stjones1@inf.ed.ac.uk 7246974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 7256974Stjones1@inf.ed.ac.uk snd_data_pkt->senderState = state; 7266974Stjones1@inf.ed.ac.uk 7276974Stjones1@inf.ed.ac.uk state->isSplit = true; 7286974Stjones1@inf.ed.ac.uk state->outstanding = 2; 7296974Stjones1@inf.ed.ac.uk 7306974Stjones1@inf.ed.ac.uk // Can delete the main request now. 7316974Stjones1@inf.ed.ac.uk delete req; 7326974Stjones1@inf.ed.ac.uk req = sreqLow; 7336974Stjones1@inf.ed.ac.uk } 7342678Sktlim@umich.edu 7352292SN/A DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " 7362292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 7373221Sktlim@umich.edu storeWBIdx, inst->readPC(), 7383797Sgblack@eecs.umich.edu req->getPaddr(), (int)*(inst->memData), 7393221Sktlim@umich.edu inst->seqNum); 7402292SN/A 7412693Sktlim@umich.edu // @todo: Remove this SC hack once the memory system handles it. 7424350Sgblack@eecs.umich.edu if (inst->isStoreConditional()) { 7436974Stjones1@inf.ed.ac.uk assert(!storeQueue[storeWBIdx].isSplit); 7443326Sktlim@umich.edu // Disable recording the result temporarily. Writing to 7453326Sktlim@umich.edu // misc regs normally updates the result, but this is not 7463326Sktlim@umich.edu // the desired behavior when handling store conditionals. 7473326Sktlim@umich.edu inst->recordResult = false; 7483326Sktlim@umich.edu bool success = TheISA::handleLockedWrite(inst.get(), req); 7493326Sktlim@umich.edu inst->recordResult = true; 7503326Sktlim@umich.edu 7513326Sktlim@umich.edu if (!success) { 7523326Sktlim@umich.edu // Instantly complete this store. 7533326Sktlim@umich.edu DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 7543326Sktlim@umich.edu "Instantly completing it.\n", 7553326Sktlim@umich.edu inst->seqNum); 7563326Sktlim@umich.edu WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 7575606Snate@binkert.org cpu->schedule(wb, curTick + 1); 7583326Sktlim@umich.edu completeStore(storeWBIdx); 7593326Sktlim@umich.edu incrStIdx(storeWBIdx); 7603326Sktlim@umich.edu continue; 7612693Sktlim@umich.edu } 7622693Sktlim@umich.edu } else { 7632693Sktlim@umich.edu // Non-store conditionals do not need a writeback. 7642693Sktlim@umich.edu state->noWB = true; 7652693Sktlim@umich.edu } 7662693Sktlim@umich.edu 7676974Stjones1@inf.ed.ac.uk if (!sendStore(data_pkt)) { 7684032Sktlim@umich.edu DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 7693221Sktlim@umich.edu "retry later\n", 7703221Sktlim@umich.edu inst->seqNum); 7716974Stjones1@inf.ed.ac.uk 7726974Stjones1@inf.ed.ac.uk // Need to store the second packet, if split. 7736974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 7746974Stjones1@inf.ed.ac.uk state->pktToSend = true; 7756974Stjones1@inf.ed.ac.uk state->pendingPacket = snd_data_pkt; 7766974Stjones1@inf.ed.ac.uk } 7772669Sktlim@umich.edu } else { 7786974Stjones1@inf.ed.ac.uk 7796974Stjones1@inf.ed.ac.uk // If split, try to send the second packet too 7806974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 7816974Stjones1@inf.ed.ac.uk assert(snd_data_pkt); 7826974Stjones1@inf.ed.ac.uk 7836974Stjones1@inf.ed.ac.uk // Ensure there are enough ports to use. 7846974Stjones1@inf.ed.ac.uk if (usedPorts < cachePorts) { 7856974Stjones1@inf.ed.ac.uk ++usedPorts; 7866974Stjones1@inf.ed.ac.uk if (sendStore(snd_data_pkt)) { 7876974Stjones1@inf.ed.ac.uk storePostSend(snd_data_pkt); 7886974Stjones1@inf.ed.ac.uk } else { 7896974Stjones1@inf.ed.ac.uk DPRINTF(IEW, "D-Cache became blocked when writing" 7906974Stjones1@inf.ed.ac.uk " [sn:%lli] second packet, will retry later\n", 7916974Stjones1@inf.ed.ac.uk inst->seqNum); 7926974Stjones1@inf.ed.ac.uk } 7936974Stjones1@inf.ed.ac.uk } else { 7946974Stjones1@inf.ed.ac.uk 7956974Stjones1@inf.ed.ac.uk // Store the packet for when there's free ports. 7966974Stjones1@inf.ed.ac.uk assert(pendingPkt == NULL); 7976974Stjones1@inf.ed.ac.uk pendingPkt = snd_data_pkt; 7986974Stjones1@inf.ed.ac.uk hasPendingPkt = true; 7996974Stjones1@inf.ed.ac.uk } 8006974Stjones1@inf.ed.ac.uk } else { 8016974Stjones1@inf.ed.ac.uk 8026974Stjones1@inf.ed.ac.uk // Not a split store. 8036974Stjones1@inf.ed.ac.uk storePostSend(data_pkt); 8046974Stjones1@inf.ed.ac.uk } 8052292SN/A } 8062292SN/A } 8072292SN/A 8082292SN/A // Not sure this should set it to 0. 8092292SN/A usedPorts = 0; 8102292SN/A 8112292SN/A assert(stores >= 0 && storesToWB >= 0); 8122292SN/A} 8132292SN/A 8142292SN/A/*template <class Impl> 8152292SN/Avoid 8162292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 8172292SN/A{ 8182292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 8192292SN/A mshrSeqNums.end(), 8202292SN/A seqNum); 8212292SN/A 8222292SN/A if (mshr_it != mshrSeqNums.end()) { 8232292SN/A mshrSeqNums.erase(mshr_it); 8242292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 8252292SN/A } 8262292SN/A}*/ 8272292SN/A 8282292SN/Atemplate <class Impl> 8292292SN/Avoid 8302292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 8312292SN/A{ 8322292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 8332329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 8342292SN/A 8352292SN/A int load_idx = loadTail; 8362292SN/A decrLdIdx(load_idx); 8372292SN/A 8382292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 8392292SN/A DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, " 8402292SN/A "[sn:%lli]\n", 8412292SN/A loadQueue[load_idx]->readPC(), 8422292SN/A loadQueue[load_idx]->seqNum); 8432292SN/A 8442292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 8452292SN/A stalled = false; 8462292SN/A stallingStoreIsn = 0; 8472292SN/A stallingLoadIdx = 0; 8482292SN/A } 8492292SN/A 8502329SN/A // Clear the smart pointer to make sure it is decremented. 8512731Sktlim@umich.edu loadQueue[load_idx]->setSquashed(); 8522292SN/A loadQueue[load_idx] = NULL; 8532292SN/A --loads; 8542292SN/A 8552292SN/A // Inefficient! 8562292SN/A loadTail = load_idx; 8572292SN/A 8582292SN/A decrLdIdx(load_idx); 8592727Sktlim@umich.edu ++lsqSquashedLoads; 8602292SN/A } 8612292SN/A 8622292SN/A if (isLoadBlocked) { 8632292SN/A if (squashed_num < blockedLoadSeqNum) { 8642292SN/A isLoadBlocked = false; 8652292SN/A loadBlockedHandled = false; 8662292SN/A blockedLoadSeqNum = 0; 8672292SN/A } 8682292SN/A } 8692292SN/A 8704032Sktlim@umich.edu if (memDepViolator && squashed_num < memDepViolator->seqNum) { 8714032Sktlim@umich.edu memDepViolator = NULL; 8724032Sktlim@umich.edu } 8734032Sktlim@umich.edu 8742292SN/A int store_idx = storeTail; 8752292SN/A decrStIdx(store_idx); 8762292SN/A 8772292SN/A while (stores != 0 && 8782292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 8792329SN/A // Instructions marked as can WB are already committed. 8802292SN/A if (storeQueue[store_idx].canWB) { 8812292SN/A break; 8822292SN/A } 8832292SN/A 8842292SN/A DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, " 8852292SN/A "idx:%i [sn:%lli]\n", 8862292SN/A storeQueue[store_idx].inst->readPC(), 8872292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 8882292SN/A 8892329SN/A // I don't think this can happen. It should have been cleared 8902329SN/A // by the stalling load. 8912292SN/A if (isStalled() && 8922292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 8932292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 8942292SN/A stalled = false; 8952292SN/A stallingStoreIsn = 0; 8962292SN/A } 8972292SN/A 8982329SN/A // Clear the smart pointer to make sure it is decremented. 8992731Sktlim@umich.edu storeQueue[store_idx].inst->setSquashed(); 9002292SN/A storeQueue[store_idx].inst = NULL; 9012292SN/A storeQueue[store_idx].canWB = 0; 9022292SN/A 9034032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 9044032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the proper 9054032Sktlim@umich.edu // place to really handle request deletes. 9064032Sktlim@umich.edu delete storeQueue[store_idx].req; 9076974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 9086974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqLow; 9096974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqHigh; 9106974Stjones1@inf.ed.ac.uk 9116974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqLow = NULL; 9126974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqHigh = NULL; 9136974Stjones1@inf.ed.ac.uk } 9144032Sktlim@umich.edu 9152292SN/A storeQueue[store_idx].req = NULL; 9162292SN/A --stores; 9172292SN/A 9182292SN/A // Inefficient! 9192292SN/A storeTail = store_idx; 9202292SN/A 9212292SN/A decrStIdx(store_idx); 9222727Sktlim@umich.edu ++lsqSquashedStores; 9232292SN/A } 9242292SN/A} 9252292SN/A 9262292SN/Atemplate <class Impl> 9272292SN/Avoid 9283349Sbinkertn@umich.eduLSQUnit<Impl>::storePostSend(PacketPtr pkt) 9292693Sktlim@umich.edu{ 9302693Sktlim@umich.edu if (isStalled() && 9312693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 9322693Sktlim@umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 9332693Sktlim@umich.edu "load idx:%i\n", 9342693Sktlim@umich.edu stallingStoreIsn, stallingLoadIdx); 9352693Sktlim@umich.edu stalled = false; 9362693Sktlim@umich.edu stallingStoreIsn = 0; 9372693Sktlim@umich.edu iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 9382693Sktlim@umich.edu } 9392693Sktlim@umich.edu 9402693Sktlim@umich.edu if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 9412693Sktlim@umich.edu // The store is basically completed at this time. This 9422693Sktlim@umich.edu // only works so long as the checker doesn't try to 9432693Sktlim@umich.edu // verify the value in memory for stores. 9442693Sktlim@umich.edu storeQueue[storeWBIdx].inst->setCompleted(); 9452733Sktlim@umich.edu#if USE_CHECKER 9462693Sktlim@umich.edu if (cpu->checker) { 9472732Sktlim@umich.edu cpu->checker->verify(storeQueue[storeWBIdx].inst); 9482693Sktlim@umich.edu } 9492733Sktlim@umich.edu#endif 9502693Sktlim@umich.edu } 9512693Sktlim@umich.edu 9522693Sktlim@umich.edu incrStIdx(storeWBIdx); 9532693Sktlim@umich.edu} 9542693Sktlim@umich.edu 9552693Sktlim@umich.edutemplate <class Impl> 9562693Sktlim@umich.eduvoid 9572678Sktlim@umich.eduLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 9582678Sktlim@umich.edu{ 9592678Sktlim@umich.edu iewStage->wakeCPU(); 9602678Sktlim@umich.edu 9612678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 9622678Sktlim@umich.edu if (inst->isSquashed()) { 9632927Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 9642678Sktlim@umich.edu assert(!inst->isStore()); 9652727Sktlim@umich.edu ++lsqIgnoredResponses; 9662678Sktlim@umich.edu return; 9672678Sktlim@umich.edu } 9682678Sktlim@umich.edu 9692678Sktlim@umich.edu if (!inst->isExecuted()) { 9702678Sktlim@umich.edu inst->setExecuted(); 9712678Sktlim@umich.edu 9722678Sktlim@umich.edu // Complete access to copy data to proper place. 9732678Sktlim@umich.edu inst->completeAcc(pkt); 9742678Sktlim@umich.edu } 9752678Sktlim@umich.edu 9762678Sktlim@umich.edu // Need to insert instruction into queue to commit 9772678Sktlim@umich.edu iewStage->instToCommit(inst); 9782678Sktlim@umich.edu 9792678Sktlim@umich.edu iewStage->activityThisCycle(); 9802678Sktlim@umich.edu} 9812678Sktlim@umich.edu 9822678Sktlim@umich.edutemplate <class Impl> 9832678Sktlim@umich.eduvoid 9842292SN/ALSQUnit<Impl>::completeStore(int store_idx) 9852292SN/A{ 9862292SN/A assert(storeQueue[store_idx].inst); 9872292SN/A storeQueue[store_idx].completed = true; 9882292SN/A --storesToWB; 9892292SN/A // A bit conservative because a store completion may not free up entries, 9902292SN/A // but hopefully avoids two store completions in one cycle from making 9912292SN/A // the CPU tick twice. 9923126Sktlim@umich.edu cpu->wakeCPU(); 9932292SN/A cpu->activityThisCycle(); 9942292SN/A 9952292SN/A if (store_idx == storeHead) { 9962292SN/A do { 9972292SN/A incrStIdx(storeHead); 9982292SN/A 9992292SN/A --stores; 10002292SN/A } while (storeQueue[storeHead].completed && 10012292SN/A storeHead != storeTail); 10022292SN/A 10032292SN/A iewStage->updateLSQNextCycle = true; 10042292SN/A } 10052292SN/A 10062329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 10072329SN/A "idx:%i\n", 10082329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 10092292SN/A 10102292SN/A if (isStalled() && 10112292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 10122292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 10132292SN/A "load idx:%i\n", 10142292SN/A stallingStoreIsn, stallingLoadIdx); 10152292SN/A stalled = false; 10162292SN/A stallingStoreIsn = 0; 10172292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 10182292SN/A } 10192316SN/A 10202316SN/A storeQueue[store_idx].inst->setCompleted(); 10212329SN/A 10222329SN/A // Tell the checker we've completed this instruction. Some stores 10232329SN/A // may get reported twice to the checker, but the checker can 10242329SN/A // handle that case. 10252733Sktlim@umich.edu#if USE_CHECKER 10262316SN/A if (cpu->checker) { 10272732Sktlim@umich.edu cpu->checker->verify(storeQueue[store_idx].inst); 10282316SN/A } 10292733Sktlim@umich.edu#endif 10302292SN/A} 10312292SN/A 10322292SN/Atemplate <class Impl> 10336974Stjones1@inf.ed.ac.ukbool 10346974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::sendStore(PacketPtr data_pkt) 10356974Stjones1@inf.ed.ac.uk{ 10366974Stjones1@inf.ed.ac.uk if (!dcachePort->sendTiming(data_pkt)) { 10376974Stjones1@inf.ed.ac.uk // Need to handle becoming blocked on a store. 10386974Stjones1@inf.ed.ac.uk isStoreBlocked = true; 10396974Stjones1@inf.ed.ac.uk ++lsqCacheBlocked; 10406974Stjones1@inf.ed.ac.uk assert(retryPkt == NULL); 10416974Stjones1@inf.ed.ac.uk retryPkt = data_pkt; 10426974Stjones1@inf.ed.ac.uk lsq->setRetryTid(lsqID); 10436974Stjones1@inf.ed.ac.uk return false; 10446974Stjones1@inf.ed.ac.uk } 10456974Stjones1@inf.ed.ac.uk return true; 10466974Stjones1@inf.ed.ac.uk} 10476974Stjones1@inf.ed.ac.uk 10486974Stjones1@inf.ed.ac.uktemplate <class Impl> 10492693Sktlim@umich.eduvoid 10502693Sktlim@umich.eduLSQUnit<Impl>::recvRetry() 10512693Sktlim@umich.edu{ 10522698Sktlim@umich.edu if (isStoreBlocked) { 10534985Sktlim@umich.edu DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 10542698Sktlim@umich.edu assert(retryPkt != NULL); 10552693Sktlim@umich.edu 10562698Sktlim@umich.edu if (dcachePort->sendTiming(retryPkt)) { 10576974Stjones1@inf.ed.ac.uk LSQSenderState *state = 10586974Stjones1@inf.ed.ac.uk dynamic_cast<LSQSenderState *>(retryPkt->senderState); 10596974Stjones1@inf.ed.ac.uk 10606974Stjones1@inf.ed.ac.uk // Don't finish the store unless this is the last packet. 10616974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !state->pktToSend) { 10626974Stjones1@inf.ed.ac.uk storePostSend(retryPkt); 10636974Stjones1@inf.ed.ac.uk } 10642699Sktlim@umich.edu retryPkt = NULL; 10652693Sktlim@umich.edu isStoreBlocked = false; 10666221Snate@binkert.org lsq->setRetryTid(InvalidThreadID); 10676974Stjones1@inf.ed.ac.uk 10686974Stjones1@inf.ed.ac.uk // Send any outstanding packet. 10696974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 10706974Stjones1@inf.ed.ac.uk assert(state->pendingPacket); 10716974Stjones1@inf.ed.ac.uk if (sendStore(state->pendingPacket)) { 10726974Stjones1@inf.ed.ac.uk storePostSend(state->pendingPacket); 10736974Stjones1@inf.ed.ac.uk } 10746974Stjones1@inf.ed.ac.uk } 10752693Sktlim@umich.edu } else { 10762693Sktlim@umich.edu // Still blocked! 10772727Sktlim@umich.edu ++lsqCacheBlocked; 10782907Sktlim@umich.edu lsq->setRetryTid(lsqID); 10792693Sktlim@umich.edu } 10802693Sktlim@umich.edu } else if (isLoadBlocked) { 10812693Sktlim@umich.edu DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 10822693Sktlim@umich.edu "no need to resend packet.\n"); 10832693Sktlim@umich.edu } else { 10842693Sktlim@umich.edu DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 10852693Sktlim@umich.edu } 10862693Sktlim@umich.edu} 10872693Sktlim@umich.edu 10882693Sktlim@umich.edutemplate <class Impl> 10892292SN/Ainline void 10902292SN/ALSQUnit<Impl>::incrStIdx(int &store_idx) 10912292SN/A{ 10922292SN/A if (++store_idx >= SQEntries) 10932292SN/A store_idx = 0; 10942292SN/A} 10952292SN/A 10962292SN/Atemplate <class Impl> 10972292SN/Ainline void 10982292SN/ALSQUnit<Impl>::decrStIdx(int &store_idx) 10992292SN/A{ 11002292SN/A if (--store_idx < 0) 11012292SN/A store_idx += SQEntries; 11022292SN/A} 11032292SN/A 11042292SN/Atemplate <class Impl> 11052292SN/Ainline void 11062292SN/ALSQUnit<Impl>::incrLdIdx(int &load_idx) 11072292SN/A{ 11082292SN/A if (++load_idx >= LQEntries) 11092292SN/A load_idx = 0; 11102292SN/A} 11112292SN/A 11122292SN/Atemplate <class Impl> 11132292SN/Ainline void 11142292SN/ALSQUnit<Impl>::decrLdIdx(int &load_idx) 11152292SN/A{ 11162292SN/A if (--load_idx < 0) 11172292SN/A load_idx += LQEntries; 11182292SN/A} 11192329SN/A 11202329SN/Atemplate <class Impl> 11212329SN/Avoid 11222329SN/ALSQUnit<Impl>::dumpInsts() 11232329SN/A{ 11242329SN/A cprintf("Load store queue: Dumping instructions.\n"); 11252329SN/A cprintf("Load queue size: %i\n", loads); 11262329SN/A cprintf("Load queue: "); 11272329SN/A 11282329SN/A int load_idx = loadHead; 11292329SN/A 11302329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 11312329SN/A cprintf("%#x ", loadQueue[load_idx]->readPC()); 11322329SN/A 11332329SN/A incrLdIdx(load_idx); 11342329SN/A } 11352329SN/A 11362329SN/A cprintf("Store queue size: %i\n", stores); 11372329SN/A cprintf("Store queue: "); 11382329SN/A 11392329SN/A int store_idx = storeHead; 11402329SN/A 11412329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 11422329SN/A cprintf("%#x ", storeQueue[store_idx].inst->readPC()); 11432329SN/A 11442329SN/A incrStIdx(store_idx); 11452329SN/A } 11462329SN/A 11472329SN/A cprintf("\n"); 11482329SN/A} 1149