lsq_unit_impl.hh revision 6658
12292SN/A/* 22292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32292SN/A * All rights reserved. 42292SN/A * 52292SN/A * Redistribution and use in source and binary forms, with or without 62292SN/A * modification, are permitted provided that the following conditions are 72292SN/A * met: redistributions of source code must retain the above copyright 82292SN/A * notice, this list of conditions and the following disclaimer; 92292SN/A * redistributions in binary form must reproduce the above copyright 102292SN/A * notice, this list of conditions and the following disclaimer in the 112292SN/A * documentation and/or other materials provided with the distribution; 122292SN/A * neither the name of the copyright holders nor the names of its 132292SN/A * contributors may be used to endorse or promote products derived from 142292SN/A * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292689Sktlim@umich.edu * Korey Sewell 302292SN/A */ 312292SN/A 323326Sktlim@umich.edu#include "arch/locked_mem.hh" 336658Snate@binkert.org#include "config/the_isa.hh" 342733Sktlim@umich.edu#include "config/use_checker.hh" 352907Sktlim@umich.edu#include "cpu/o3/lsq.hh" 362292SN/A#include "cpu/o3/lsq_unit.hh" 372292SN/A#include "base/str.hh" 382722Sktlim@umich.edu#include "mem/packet.hh" 392669Sktlim@umich.edu#include "mem/request.hh" 402292SN/A 412790Sktlim@umich.edu#if USE_CHECKER 422790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 432790Sktlim@umich.edu#endif 442790Sktlim@umich.edu 452669Sktlim@umich.edutemplate<class Impl> 462678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 472678Sktlim@umich.edu LSQUnit *lsq_ptr) 485606Snate@binkert.org : inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 492292SN/A{ 502678Sktlim@umich.edu this->setFlags(Event::AutoDelete); 512292SN/A} 522292SN/A 532669Sktlim@umich.edutemplate<class Impl> 542292SN/Avoid 552678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 562292SN/A{ 572678Sktlim@umich.edu if (!lsqPtr->isSwitchedOut()) { 582678Sktlim@umich.edu lsqPtr->writeback(inst, pkt); 592678Sktlim@umich.edu } 604319Sktlim@umich.edu 614319Sktlim@umich.edu if (pkt->senderState) 624319Sktlim@umich.edu delete pkt->senderState; 634319Sktlim@umich.edu 644319Sktlim@umich.edu delete pkt->req; 652678Sktlim@umich.edu delete pkt; 662678Sktlim@umich.edu} 672292SN/A 682678Sktlim@umich.edutemplate<class Impl> 692678Sktlim@umich.educonst char * 705336Shines@cs.fsu.eduLSQUnit<Impl>::WritebackEvent::description() const 712678Sktlim@umich.edu{ 724873Sstever@eecs.umich.edu return "Store writeback"; 732678Sktlim@umich.edu} 742292SN/A 752678Sktlim@umich.edutemplate<class Impl> 762678Sktlim@umich.eduvoid 772678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 782678Sktlim@umich.edu{ 792678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 802678Sktlim@umich.edu DynInstPtr inst = state->inst; 812678Sktlim@umich.edu DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum); 822698Sktlim@umich.edu DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum); 832344SN/A 842678Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 852678Sktlim@umich.edu 864986Ssaidi@eecs.umich.edu assert(!pkt->wasNacked()); 874986Ssaidi@eecs.umich.edu 882678Sktlim@umich.edu if (isSwitchedOut() || inst->isSquashed()) { 892820Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 902678Sktlim@umich.edu } else { 912678Sktlim@umich.edu if (!state->noWB) { 922678Sktlim@umich.edu writeback(inst, pkt); 932678Sktlim@umich.edu } 942678Sktlim@umich.edu 952678Sktlim@umich.edu if (inst->isStore()) { 962678Sktlim@umich.edu completeStore(state->idx); 972678Sktlim@umich.edu } 982344SN/A } 992307SN/A 1002678Sktlim@umich.edu delete state; 1014032Sktlim@umich.edu delete pkt->req; 1022678Sktlim@umich.edu delete pkt; 1032292SN/A} 1042292SN/A 1052292SN/Atemplate <class Impl> 1062292SN/ALSQUnit<Impl>::LSQUnit() 1072678Sktlim@umich.edu : loads(0), stores(0), storesToWB(0), stalled(false), 1082678Sktlim@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1092292SN/A loadBlockedHandled(false) 1102292SN/A{ 1112292SN/A} 1122292SN/A 1132292SN/Atemplate<class Impl> 1142292SN/Avoid 1155529Snate@binkert.orgLSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 1165529Snate@binkert.org LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 1175529Snate@binkert.org unsigned id) 1182292SN/A{ 1194329Sktlim@umich.edu cpu = cpu_ptr; 1204329Sktlim@umich.edu iewStage = iew_ptr; 1214329Sktlim@umich.edu 1224329Sktlim@umich.edu DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1232292SN/A 1242307SN/A switchedOut = false; 1252307SN/A 1262907Sktlim@umich.edu lsq = lsq_ptr; 1272907Sktlim@umich.edu 1282292SN/A lsqID = id; 1292292SN/A 1302329SN/A // Add 1 for the sentinel entry (they are circular queues). 1312329SN/A LQEntries = maxLQEntries + 1; 1322329SN/A SQEntries = maxSQEntries + 1; 1332292SN/A 1342292SN/A loadQueue.resize(LQEntries); 1352292SN/A storeQueue.resize(SQEntries); 1362292SN/A 1372292SN/A loadHead = loadTail = 0; 1382292SN/A 1392292SN/A storeHead = storeWBIdx = storeTail = 0; 1402292SN/A 1412292SN/A usedPorts = 0; 1422292SN/A cachePorts = params->cachePorts; 1432292SN/A 1443492Sktlim@umich.edu retryPkt = NULL; 1452329SN/A memDepViolator = NULL; 1462292SN/A 1472292SN/A blockedLoadSeqNum = 0; 1482292SN/A} 1492292SN/A 1502292SN/Atemplate<class Impl> 1512292SN/Astd::string 1522292SN/ALSQUnit<Impl>::name() const 1532292SN/A{ 1542292SN/A if (Impl::MaxThreads == 1) { 1552292SN/A return iewStage->name() + ".lsq"; 1562292SN/A } else { 1572292SN/A return iewStage->name() + ".lsq.thread." + to_string(lsqID); 1582292SN/A } 1592292SN/A} 1602292SN/A 1612292SN/Atemplate<class Impl> 1622292SN/Avoid 1632727Sktlim@umich.eduLSQUnit<Impl>::regStats() 1642727Sktlim@umich.edu{ 1652727Sktlim@umich.edu lsqForwLoads 1662727Sktlim@umich.edu .name(name() + ".forwLoads") 1672727Sktlim@umich.edu .desc("Number of loads that had data forwarded from stores"); 1682727Sktlim@umich.edu 1692727Sktlim@umich.edu invAddrLoads 1702727Sktlim@umich.edu .name(name() + ".invAddrLoads") 1712727Sktlim@umich.edu .desc("Number of loads ignored due to an invalid address"); 1722727Sktlim@umich.edu 1732727Sktlim@umich.edu lsqSquashedLoads 1742727Sktlim@umich.edu .name(name() + ".squashedLoads") 1752727Sktlim@umich.edu .desc("Number of loads squashed"); 1762727Sktlim@umich.edu 1772727Sktlim@umich.edu lsqIgnoredResponses 1782727Sktlim@umich.edu .name(name() + ".ignoredResponses") 1792727Sktlim@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 1802727Sktlim@umich.edu 1812361SN/A lsqMemOrderViolation 1822361SN/A .name(name() + ".memOrderViolation") 1832361SN/A .desc("Number of memory ordering violations"); 1842361SN/A 1852727Sktlim@umich.edu lsqSquashedStores 1862727Sktlim@umich.edu .name(name() + ".squashedStores") 1872727Sktlim@umich.edu .desc("Number of stores squashed"); 1882727Sktlim@umich.edu 1892727Sktlim@umich.edu invAddrSwpfs 1902727Sktlim@umich.edu .name(name() + ".invAddrSwpfs") 1912727Sktlim@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 1922727Sktlim@umich.edu 1932727Sktlim@umich.edu lsqBlockedLoads 1942727Sktlim@umich.edu .name(name() + ".blockedLoads") 1952727Sktlim@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 1962727Sktlim@umich.edu 1972727Sktlim@umich.edu lsqRescheduledLoads 1982727Sktlim@umich.edu .name(name() + ".rescheduledLoads") 1992727Sktlim@umich.edu .desc("Number of loads that were rescheduled"); 2002727Sktlim@umich.edu 2012727Sktlim@umich.edu lsqCacheBlocked 2022727Sktlim@umich.edu .name(name() + ".cacheBlocked") 2032727Sktlim@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2042727Sktlim@umich.edu} 2052727Sktlim@umich.edu 2062727Sktlim@umich.edutemplate<class Impl> 2072727Sktlim@umich.eduvoid 2084329Sktlim@umich.eduLSQUnit<Impl>::setDcachePort(Port *dcache_port) 2094329Sktlim@umich.edu{ 2104329Sktlim@umich.edu dcachePort = dcache_port; 2114329Sktlim@umich.edu 2124329Sktlim@umich.edu#if USE_CHECKER 2134329Sktlim@umich.edu if (cpu->checker) { 2144329Sktlim@umich.edu cpu->checker->setDcachePort(dcachePort); 2154329Sktlim@umich.edu } 2164329Sktlim@umich.edu#endif 2174329Sktlim@umich.edu} 2184329Sktlim@umich.edu 2194329Sktlim@umich.edutemplate<class Impl> 2204329Sktlim@umich.eduvoid 2212292SN/ALSQUnit<Impl>::clearLQ() 2222292SN/A{ 2232292SN/A loadQueue.clear(); 2242292SN/A} 2252292SN/A 2262292SN/Atemplate<class Impl> 2272292SN/Avoid 2282292SN/ALSQUnit<Impl>::clearSQ() 2292292SN/A{ 2302292SN/A storeQueue.clear(); 2312292SN/A} 2322292SN/A 2332292SN/Atemplate<class Impl> 2342292SN/Avoid 2352307SN/ALSQUnit<Impl>::switchOut() 2362307SN/A{ 2372307SN/A switchedOut = true; 2382367SN/A for (int i = 0; i < loadQueue.size(); ++i) { 2392367SN/A assert(!loadQueue[i]); 2402307SN/A loadQueue[i] = NULL; 2412367SN/A } 2422307SN/A 2432329SN/A assert(storesToWB == 0); 2442307SN/A} 2452307SN/A 2462307SN/Atemplate<class Impl> 2472307SN/Avoid 2482307SN/ALSQUnit<Impl>::takeOverFrom() 2492307SN/A{ 2502307SN/A switchedOut = false; 2512307SN/A loads = stores = storesToWB = 0; 2522307SN/A 2532307SN/A loadHead = loadTail = 0; 2542307SN/A 2552307SN/A storeHead = storeWBIdx = storeTail = 0; 2562307SN/A 2572307SN/A usedPorts = 0; 2582307SN/A 2592329SN/A memDepViolator = NULL; 2602307SN/A 2612307SN/A blockedLoadSeqNum = 0; 2622307SN/A 2632307SN/A stalled = false; 2642307SN/A isLoadBlocked = false; 2652307SN/A loadBlockedHandled = false; 2662307SN/A} 2672307SN/A 2682307SN/Atemplate<class Impl> 2692307SN/Avoid 2702292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 2712292SN/A{ 2722329SN/A unsigned size_plus_sentinel = size + 1; 2732329SN/A assert(size_plus_sentinel >= LQEntries); 2742292SN/A 2752329SN/A if (size_plus_sentinel > LQEntries) { 2762329SN/A while (size_plus_sentinel > loadQueue.size()) { 2772292SN/A DynInstPtr dummy; 2782292SN/A loadQueue.push_back(dummy); 2792292SN/A LQEntries++; 2802292SN/A } 2812292SN/A } else { 2822329SN/A LQEntries = size_plus_sentinel; 2832292SN/A } 2842292SN/A 2852292SN/A} 2862292SN/A 2872292SN/Atemplate<class Impl> 2882292SN/Avoid 2892292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 2902292SN/A{ 2912329SN/A unsigned size_plus_sentinel = size + 1; 2922329SN/A if (size_plus_sentinel > SQEntries) { 2932329SN/A while (size_plus_sentinel > storeQueue.size()) { 2942292SN/A SQEntry dummy; 2952292SN/A storeQueue.push_back(dummy); 2962292SN/A SQEntries++; 2972292SN/A } 2982292SN/A } else { 2992329SN/A SQEntries = size_plus_sentinel; 3002292SN/A } 3012292SN/A} 3022292SN/A 3032292SN/Atemplate <class Impl> 3042292SN/Avoid 3052292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 3062292SN/A{ 3072292SN/A assert(inst->isMemRef()); 3082292SN/A 3092292SN/A assert(inst->isLoad() || inst->isStore()); 3102292SN/A 3112292SN/A if (inst->isLoad()) { 3122292SN/A insertLoad(inst); 3132292SN/A } else { 3142292SN/A insertStore(inst); 3152292SN/A } 3162292SN/A 3172292SN/A inst->setInLSQ(); 3182292SN/A} 3192292SN/A 3202292SN/Atemplate <class Impl> 3212292SN/Avoid 3222292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3232292SN/A{ 3242329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3252329SN/A assert(loads < LQEntries); 3262292SN/A 3272292SN/A DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n", 3282292SN/A load_inst->readPC(), loadTail, load_inst->seqNum); 3292292SN/A 3302292SN/A load_inst->lqIdx = loadTail; 3312292SN/A 3322292SN/A if (stores == 0) { 3332292SN/A load_inst->sqIdx = -1; 3342292SN/A } else { 3352292SN/A load_inst->sqIdx = storeTail; 3362292SN/A } 3372292SN/A 3382292SN/A loadQueue[loadTail] = load_inst; 3392292SN/A 3402292SN/A incrLdIdx(loadTail); 3412292SN/A 3422292SN/A ++loads; 3432292SN/A} 3442292SN/A 3452292SN/Atemplate <class Impl> 3462292SN/Avoid 3472292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3482292SN/A{ 3492292SN/A // Make sure it is not full before inserting an instruction. 3502292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3512292SN/A assert(stores < SQEntries); 3522292SN/A 3532292SN/A DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n", 3542292SN/A store_inst->readPC(), storeTail, store_inst->seqNum); 3552292SN/A 3562292SN/A store_inst->sqIdx = storeTail; 3572292SN/A store_inst->lqIdx = loadTail; 3582292SN/A 3592292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3602292SN/A 3612292SN/A incrStIdx(storeTail); 3622292SN/A 3632292SN/A ++stores; 3642292SN/A} 3652292SN/A 3662292SN/Atemplate <class Impl> 3672292SN/Atypename Impl::DynInstPtr 3682292SN/ALSQUnit<Impl>::getMemDepViolator() 3692292SN/A{ 3702292SN/A DynInstPtr temp = memDepViolator; 3712292SN/A 3722292SN/A memDepViolator = NULL; 3732292SN/A 3742292SN/A return temp; 3752292SN/A} 3762292SN/A 3772292SN/Atemplate <class Impl> 3782292SN/Aunsigned 3792292SN/ALSQUnit<Impl>::numFreeEntries() 3802292SN/A{ 3812292SN/A unsigned free_lq_entries = LQEntries - loads; 3822292SN/A unsigned free_sq_entries = SQEntries - stores; 3832292SN/A 3842292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 3852292SN/A // empty/full conditions. Subtract 1 from the free entries. 3862292SN/A if (free_lq_entries < free_sq_entries) { 3872292SN/A return free_lq_entries - 1; 3882292SN/A } else { 3892292SN/A return free_sq_entries - 1; 3902292SN/A } 3912292SN/A} 3922292SN/A 3932292SN/Atemplate <class Impl> 3942292SN/Aint 3952292SN/ALSQUnit<Impl>::numLoadsReady() 3962292SN/A{ 3972292SN/A int load_idx = loadHead; 3982292SN/A int retval = 0; 3992292SN/A 4002292SN/A while (load_idx != loadTail) { 4012292SN/A assert(loadQueue[load_idx]); 4022292SN/A 4032292SN/A if (loadQueue[load_idx]->readyToIssue()) { 4042292SN/A ++retval; 4052292SN/A } 4062292SN/A } 4072292SN/A 4082292SN/A return retval; 4092292SN/A} 4102292SN/A 4112292SN/Atemplate <class Impl> 4122292SN/AFault 4132292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 4142292SN/A{ 4154032Sktlim@umich.edu using namespace TheISA; 4162292SN/A // Execute a specific load. 4172292SN/A Fault load_fault = NoFault; 4182292SN/A 4192292SN/A DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n", 4202292SN/A inst->readPC(),inst->seqNum); 4212292SN/A 4224032Sktlim@umich.edu assert(!inst->isSquashed()); 4234032Sktlim@umich.edu 4242669Sktlim@umich.edu load_fault = inst->initiateAcc(); 4252292SN/A 4262292SN/A // If the instruction faulted, then we need to send it along to commit 4272292SN/A // without the instruction completing. 4282292SN/A if (load_fault != NoFault) { 4292329SN/A // Send this instruction to commit, also make sure iew stage 4302329SN/A // realizes there is activity. 4312367SN/A // Mark it as executed unless it is an uncached load that 4322367SN/A // needs to hit the head of commit. 4334032Sktlim@umich.edu if (!(inst->hasRequest() && inst->uncacheable()) || 4343731Sktlim@umich.edu inst->isAtCommit()) { 4352367SN/A inst->setExecuted(); 4362367SN/A } 4372292SN/A iewStage->instToCommit(inst); 4382292SN/A iewStage->activityThisCycle(); 4394032Sktlim@umich.edu } else if (!loadBlocked()) { 4404032Sktlim@umich.edu assert(inst->effAddrValid); 4414032Sktlim@umich.edu int load_idx = inst->lqIdx; 4424032Sktlim@umich.edu incrLdIdx(load_idx); 4434032Sktlim@umich.edu while (load_idx != loadTail) { 4444032Sktlim@umich.edu // Really only need to check loads that have actually executed 4454032Sktlim@umich.edu 4464032Sktlim@umich.edu // @todo: For now this is extra conservative, detecting a 4474032Sktlim@umich.edu // violation if the addresses match assuming all accesses 4484032Sktlim@umich.edu // are quad word accesses. 4494032Sktlim@umich.edu 4504032Sktlim@umich.edu // @todo: Fix this, magic number being used here 4514032Sktlim@umich.edu if (loadQueue[load_idx]->effAddrValid && 4524032Sktlim@umich.edu (loadQueue[load_idx]->effAddr >> 8) == 4534032Sktlim@umich.edu (inst->effAddr >> 8)) { 4544032Sktlim@umich.edu // A load incorrectly passed this load. Squash and refetch. 4554032Sktlim@umich.edu // For now return a fault to show that it was unsuccessful. 4564032Sktlim@umich.edu DynInstPtr violator = loadQueue[load_idx]; 4574032Sktlim@umich.edu if (!memDepViolator || 4584032Sktlim@umich.edu (violator->seqNum < memDepViolator->seqNum)) { 4594032Sktlim@umich.edu memDepViolator = violator; 4604032Sktlim@umich.edu } else { 4614032Sktlim@umich.edu break; 4624032Sktlim@umich.edu } 4634032Sktlim@umich.edu 4644032Sktlim@umich.edu ++lsqMemOrderViolation; 4654032Sktlim@umich.edu 4664032Sktlim@umich.edu return genMachineCheckFault(); 4674032Sktlim@umich.edu } 4684032Sktlim@umich.edu 4694032Sktlim@umich.edu incrLdIdx(load_idx); 4704032Sktlim@umich.edu } 4712292SN/A } 4722292SN/A 4732292SN/A return load_fault; 4742292SN/A} 4752292SN/A 4762292SN/Atemplate <class Impl> 4772292SN/AFault 4782292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 4792292SN/A{ 4802292SN/A using namespace TheISA; 4812292SN/A // Make sure that a store exists. 4822292SN/A assert(stores != 0); 4832292SN/A 4842292SN/A int store_idx = store_inst->sqIdx; 4852292SN/A 4862292SN/A DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n", 4872292SN/A store_inst->readPC(), store_inst->seqNum); 4882292SN/A 4894032Sktlim@umich.edu assert(!store_inst->isSquashed()); 4904032Sktlim@umich.edu 4912292SN/A // Check the recently completed loads to see if any match this store's 4922292SN/A // address. If so, then we have a memory ordering violation. 4932292SN/A int load_idx = store_inst->lqIdx; 4942292SN/A 4952292SN/A Fault store_fault = store_inst->initiateAcc(); 4962292SN/A 4972329SN/A if (storeQueue[store_idx].size == 0) { 4982292SN/A DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n", 4992292SN/A store_inst->readPC(),store_inst->seqNum); 5002292SN/A 5012292SN/A return store_fault; 5022292SN/A } 5032292SN/A 5042292SN/A assert(store_fault == NoFault); 5052292SN/A 5062336SN/A if (store_inst->isStoreConditional()) { 5072336SN/A // Store conditionals need to set themselves as able to 5082336SN/A // writeback if we haven't had a fault by here. 5092329SN/A storeQueue[store_idx].canWB = true; 5102292SN/A 5112329SN/A ++storesToWB; 5122292SN/A } 5132292SN/A 5144032Sktlim@umich.edu assert(store_inst->effAddrValid); 5154032Sktlim@umich.edu while (load_idx != loadTail) { 5164032Sktlim@umich.edu // Really only need to check loads that have actually executed 5174032Sktlim@umich.edu // It's safe to check all loads because effAddr is set to 5184032Sktlim@umich.edu // InvalAddr when the dyn inst is created. 5192292SN/A 5204032Sktlim@umich.edu // @todo: For now this is extra conservative, detecting a 5214032Sktlim@umich.edu // violation if the addresses match assuming all accesses 5224032Sktlim@umich.edu // are quad word accesses. 5232329SN/A 5244032Sktlim@umich.edu // @todo: Fix this, magic number being used here 5254032Sktlim@umich.edu if (loadQueue[load_idx]->effAddrValid && 5264032Sktlim@umich.edu (loadQueue[load_idx]->effAddr >> 8) == 5274032Sktlim@umich.edu (store_inst->effAddr >> 8)) { 5284032Sktlim@umich.edu // A load incorrectly passed this store. Squash and refetch. 5294032Sktlim@umich.edu // For now return a fault to show that it was unsuccessful. 5304032Sktlim@umich.edu DynInstPtr violator = loadQueue[load_idx]; 5314032Sktlim@umich.edu if (!memDepViolator || 5324032Sktlim@umich.edu (violator->seqNum < memDepViolator->seqNum)) { 5334032Sktlim@umich.edu memDepViolator = violator; 5344032Sktlim@umich.edu } else { 5354032Sktlim@umich.edu break; 5362292SN/A } 5372292SN/A 5384032Sktlim@umich.edu ++lsqMemOrderViolation; 5394032Sktlim@umich.edu 5404032Sktlim@umich.edu return genMachineCheckFault(); 5412292SN/A } 5422292SN/A 5434032Sktlim@umich.edu incrLdIdx(load_idx); 5442292SN/A } 5452292SN/A 5462292SN/A return store_fault; 5472292SN/A} 5482292SN/A 5492292SN/Atemplate <class Impl> 5502292SN/Avoid 5512292SN/ALSQUnit<Impl>::commitLoad() 5522292SN/A{ 5532292SN/A assert(loadQueue[loadHead]); 5542292SN/A 5552292SN/A DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n", 5562292SN/A loadQueue[loadHead]->readPC()); 5572292SN/A 5582292SN/A loadQueue[loadHead] = NULL; 5592292SN/A 5602292SN/A incrLdIdx(loadHead); 5612292SN/A 5622292SN/A --loads; 5632292SN/A} 5642292SN/A 5652292SN/Atemplate <class Impl> 5662292SN/Avoid 5672292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 5682292SN/A{ 5692292SN/A assert(loads == 0 || loadQueue[loadHead]); 5702292SN/A 5712292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 5722292SN/A commitLoad(); 5732292SN/A } 5742292SN/A} 5752292SN/A 5762292SN/Atemplate <class Impl> 5772292SN/Avoid 5782292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 5792292SN/A{ 5802292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 5812292SN/A 5822292SN/A int store_idx = storeHead; 5832292SN/A 5842292SN/A while (store_idx != storeTail) { 5852292SN/A assert(storeQueue[store_idx].inst); 5862329SN/A // Mark any stores that are now committed and have not yet 5872329SN/A // been marked as able to write back. 5882292SN/A if (!storeQueue[store_idx].canWB) { 5892292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 5902292SN/A break; 5912292SN/A } 5922292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 5932292SN/A "%#x [sn:%lli]\n", 5942292SN/A storeQueue[store_idx].inst->readPC(), 5952292SN/A storeQueue[store_idx].inst->seqNum); 5962292SN/A 5972292SN/A storeQueue[store_idx].canWB = true; 5982292SN/A 5992292SN/A ++storesToWB; 6002292SN/A } 6012292SN/A 6022292SN/A incrStIdx(store_idx); 6032292SN/A } 6042292SN/A} 6052292SN/A 6062292SN/Atemplate <class Impl> 6072292SN/Avoid 6082292SN/ALSQUnit<Impl>::writebackStores() 6092292SN/A{ 6102292SN/A while (storesToWB > 0 && 6112292SN/A storeWBIdx != storeTail && 6122292SN/A storeQueue[storeWBIdx].inst && 6132292SN/A storeQueue[storeWBIdx].canWB && 6142292SN/A usedPorts < cachePorts) { 6152292SN/A 6162907Sktlim@umich.edu if (isStoreBlocked || lsq->cacheBlocked()) { 6172678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 6182678Sktlim@umich.edu " is blocked!\n"); 6192678Sktlim@umich.edu break; 6202678Sktlim@umich.edu } 6212678Sktlim@umich.edu 6222329SN/A // Store didn't write any data so no need to write it back to 6232329SN/A // memory. 6242292SN/A if (storeQueue[storeWBIdx].size == 0) { 6252292SN/A completeStore(storeWBIdx); 6262292SN/A 6272292SN/A incrStIdx(storeWBIdx); 6282292SN/A 6292292SN/A continue; 6302292SN/A } 6312678Sktlim@umich.edu 6322292SN/A ++usedPorts; 6332292SN/A 6342292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 6352292SN/A incrStIdx(storeWBIdx); 6362292SN/A 6372292SN/A continue; 6382292SN/A } 6392292SN/A 6402292SN/A assert(storeQueue[storeWBIdx].req); 6412292SN/A assert(!storeQueue[storeWBIdx].committed); 6422292SN/A 6432669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 6442669Sktlim@umich.edu 6452669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 6462292SN/A storeQueue[storeWBIdx].committed = true; 6472292SN/A 6482669Sktlim@umich.edu assert(!inst->memData); 6492669Sktlim@umich.edu inst->memData = new uint8_t[64]; 6503772Sgblack@eecs.umich.edu 6514326Sgblack@eecs.umich.edu memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 6522669Sktlim@umich.edu 6534878Sstever@eecs.umich.edu MemCmd command = 6544878Sstever@eecs.umich.edu req->isSwap() ? MemCmd::SwapReq : 6556102Sgblack@eecs.umich.edu (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 6564350Sgblack@eecs.umich.edu PacketPtr data_pkt = new Packet(req, command, 6574022Sstever@eecs.umich.edu Packet::Broadcast); 6582669Sktlim@umich.edu data_pkt->dataStatic(inst->memData); 6592292SN/A 6602678Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 6612678Sktlim@umich.edu state->isLoad = false; 6622678Sktlim@umich.edu state->idx = storeWBIdx; 6632678Sktlim@umich.edu state->inst = inst; 6642678Sktlim@umich.edu data_pkt->senderState = state; 6652678Sktlim@umich.edu 6662292SN/A DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " 6672292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 6683221Sktlim@umich.edu storeWBIdx, inst->readPC(), 6693797Sgblack@eecs.umich.edu req->getPaddr(), (int)*(inst->memData), 6703221Sktlim@umich.edu inst->seqNum); 6712292SN/A 6722693Sktlim@umich.edu // @todo: Remove this SC hack once the memory system handles it. 6734350Sgblack@eecs.umich.edu if (inst->isStoreConditional()) { 6743326Sktlim@umich.edu // Disable recording the result temporarily. Writing to 6753326Sktlim@umich.edu // misc regs normally updates the result, but this is not 6763326Sktlim@umich.edu // the desired behavior when handling store conditionals. 6773326Sktlim@umich.edu inst->recordResult = false; 6783326Sktlim@umich.edu bool success = TheISA::handleLockedWrite(inst.get(), req); 6793326Sktlim@umich.edu inst->recordResult = true; 6803326Sktlim@umich.edu 6813326Sktlim@umich.edu if (!success) { 6823326Sktlim@umich.edu // Instantly complete this store. 6833326Sktlim@umich.edu DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 6843326Sktlim@umich.edu "Instantly completing it.\n", 6853326Sktlim@umich.edu inst->seqNum); 6863326Sktlim@umich.edu WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 6875606Snate@binkert.org cpu->schedule(wb, curTick + 1); 6883326Sktlim@umich.edu completeStore(storeWBIdx); 6893326Sktlim@umich.edu incrStIdx(storeWBIdx); 6903326Sktlim@umich.edu continue; 6912693Sktlim@umich.edu } 6922693Sktlim@umich.edu } else { 6932693Sktlim@umich.edu // Non-store conditionals do not need a writeback. 6942693Sktlim@umich.edu state->noWB = true; 6952693Sktlim@umich.edu } 6962693Sktlim@umich.edu 6972669Sktlim@umich.edu if (!dcachePort->sendTiming(data_pkt)) { 6982669Sktlim@umich.edu // Need to handle becoming blocked on a store. 6994032Sktlim@umich.edu DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 7003221Sktlim@umich.edu "retry later\n", 7013221Sktlim@umich.edu inst->seqNum); 7022678Sktlim@umich.edu isStoreBlocked = true; 7032727Sktlim@umich.edu ++lsqCacheBlocked; 7042698Sktlim@umich.edu assert(retryPkt == NULL); 7052698Sktlim@umich.edu retryPkt = data_pkt; 7063014Srdreslin@umich.edu lsq->setRetryTid(lsqID); 7072669Sktlim@umich.edu } else { 7082693Sktlim@umich.edu storePostSend(data_pkt); 7092292SN/A } 7102292SN/A } 7112292SN/A 7122292SN/A // Not sure this should set it to 0. 7132292SN/A usedPorts = 0; 7142292SN/A 7152292SN/A assert(stores >= 0 && storesToWB >= 0); 7162292SN/A} 7172292SN/A 7182292SN/A/*template <class Impl> 7192292SN/Avoid 7202292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 7212292SN/A{ 7222292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 7232292SN/A mshrSeqNums.end(), 7242292SN/A seqNum); 7252292SN/A 7262292SN/A if (mshr_it != mshrSeqNums.end()) { 7272292SN/A mshrSeqNums.erase(mshr_it); 7282292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 7292292SN/A } 7302292SN/A}*/ 7312292SN/A 7322292SN/Atemplate <class Impl> 7332292SN/Avoid 7342292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 7352292SN/A{ 7362292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 7372329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 7382292SN/A 7392292SN/A int load_idx = loadTail; 7402292SN/A decrLdIdx(load_idx); 7412292SN/A 7422292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 7432292SN/A DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, " 7442292SN/A "[sn:%lli]\n", 7452292SN/A loadQueue[load_idx]->readPC(), 7462292SN/A loadQueue[load_idx]->seqNum); 7472292SN/A 7482292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 7492292SN/A stalled = false; 7502292SN/A stallingStoreIsn = 0; 7512292SN/A stallingLoadIdx = 0; 7522292SN/A } 7532292SN/A 7542329SN/A // Clear the smart pointer to make sure it is decremented. 7552731Sktlim@umich.edu loadQueue[load_idx]->setSquashed(); 7562292SN/A loadQueue[load_idx] = NULL; 7572292SN/A --loads; 7582292SN/A 7592292SN/A // Inefficient! 7602292SN/A loadTail = load_idx; 7612292SN/A 7622292SN/A decrLdIdx(load_idx); 7632727Sktlim@umich.edu ++lsqSquashedLoads; 7642292SN/A } 7652292SN/A 7662292SN/A if (isLoadBlocked) { 7672292SN/A if (squashed_num < blockedLoadSeqNum) { 7682292SN/A isLoadBlocked = false; 7692292SN/A loadBlockedHandled = false; 7702292SN/A blockedLoadSeqNum = 0; 7712292SN/A } 7722292SN/A } 7732292SN/A 7744032Sktlim@umich.edu if (memDepViolator && squashed_num < memDepViolator->seqNum) { 7754032Sktlim@umich.edu memDepViolator = NULL; 7764032Sktlim@umich.edu } 7774032Sktlim@umich.edu 7782292SN/A int store_idx = storeTail; 7792292SN/A decrStIdx(store_idx); 7802292SN/A 7812292SN/A while (stores != 0 && 7822292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 7832329SN/A // Instructions marked as can WB are already committed. 7842292SN/A if (storeQueue[store_idx].canWB) { 7852292SN/A break; 7862292SN/A } 7872292SN/A 7882292SN/A DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, " 7892292SN/A "idx:%i [sn:%lli]\n", 7902292SN/A storeQueue[store_idx].inst->readPC(), 7912292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 7922292SN/A 7932329SN/A // I don't think this can happen. It should have been cleared 7942329SN/A // by the stalling load. 7952292SN/A if (isStalled() && 7962292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 7972292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 7982292SN/A stalled = false; 7992292SN/A stallingStoreIsn = 0; 8002292SN/A } 8012292SN/A 8022329SN/A // Clear the smart pointer to make sure it is decremented. 8032731Sktlim@umich.edu storeQueue[store_idx].inst->setSquashed(); 8042292SN/A storeQueue[store_idx].inst = NULL; 8052292SN/A storeQueue[store_idx].canWB = 0; 8062292SN/A 8074032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 8084032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the proper 8094032Sktlim@umich.edu // place to really handle request deletes. 8104032Sktlim@umich.edu delete storeQueue[store_idx].req; 8114032Sktlim@umich.edu 8122292SN/A storeQueue[store_idx].req = NULL; 8132292SN/A --stores; 8142292SN/A 8152292SN/A // Inefficient! 8162292SN/A storeTail = store_idx; 8172292SN/A 8182292SN/A decrStIdx(store_idx); 8192727Sktlim@umich.edu ++lsqSquashedStores; 8202292SN/A } 8212292SN/A} 8222292SN/A 8232292SN/Atemplate <class Impl> 8242292SN/Avoid 8253349Sbinkertn@umich.eduLSQUnit<Impl>::storePostSend(PacketPtr pkt) 8262693Sktlim@umich.edu{ 8272693Sktlim@umich.edu if (isStalled() && 8282693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 8292693Sktlim@umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 8302693Sktlim@umich.edu "load idx:%i\n", 8312693Sktlim@umich.edu stallingStoreIsn, stallingLoadIdx); 8322693Sktlim@umich.edu stalled = false; 8332693Sktlim@umich.edu stallingStoreIsn = 0; 8342693Sktlim@umich.edu iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 8352693Sktlim@umich.edu } 8362693Sktlim@umich.edu 8372693Sktlim@umich.edu if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 8382693Sktlim@umich.edu // The store is basically completed at this time. This 8392693Sktlim@umich.edu // only works so long as the checker doesn't try to 8402693Sktlim@umich.edu // verify the value in memory for stores. 8412693Sktlim@umich.edu storeQueue[storeWBIdx].inst->setCompleted(); 8422733Sktlim@umich.edu#if USE_CHECKER 8432693Sktlim@umich.edu if (cpu->checker) { 8442732Sktlim@umich.edu cpu->checker->verify(storeQueue[storeWBIdx].inst); 8452693Sktlim@umich.edu } 8462733Sktlim@umich.edu#endif 8472693Sktlim@umich.edu } 8482693Sktlim@umich.edu 8492693Sktlim@umich.edu incrStIdx(storeWBIdx); 8502693Sktlim@umich.edu} 8512693Sktlim@umich.edu 8522693Sktlim@umich.edutemplate <class Impl> 8532693Sktlim@umich.eduvoid 8542678Sktlim@umich.eduLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 8552678Sktlim@umich.edu{ 8562678Sktlim@umich.edu iewStage->wakeCPU(); 8572678Sktlim@umich.edu 8582678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 8592678Sktlim@umich.edu if (inst->isSquashed()) { 8602927Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 8612678Sktlim@umich.edu assert(!inst->isStore()); 8622727Sktlim@umich.edu ++lsqIgnoredResponses; 8632678Sktlim@umich.edu return; 8642678Sktlim@umich.edu } 8652678Sktlim@umich.edu 8662678Sktlim@umich.edu if (!inst->isExecuted()) { 8672678Sktlim@umich.edu inst->setExecuted(); 8682678Sktlim@umich.edu 8692678Sktlim@umich.edu // Complete access to copy data to proper place. 8702678Sktlim@umich.edu inst->completeAcc(pkt); 8712678Sktlim@umich.edu } 8722678Sktlim@umich.edu 8732678Sktlim@umich.edu // Need to insert instruction into queue to commit 8742678Sktlim@umich.edu iewStage->instToCommit(inst); 8752678Sktlim@umich.edu 8762678Sktlim@umich.edu iewStage->activityThisCycle(); 8772678Sktlim@umich.edu} 8782678Sktlim@umich.edu 8792678Sktlim@umich.edutemplate <class Impl> 8802678Sktlim@umich.eduvoid 8812292SN/ALSQUnit<Impl>::completeStore(int store_idx) 8822292SN/A{ 8832292SN/A assert(storeQueue[store_idx].inst); 8842292SN/A storeQueue[store_idx].completed = true; 8852292SN/A --storesToWB; 8862292SN/A // A bit conservative because a store completion may not free up entries, 8872292SN/A // but hopefully avoids two store completions in one cycle from making 8882292SN/A // the CPU tick twice. 8893126Sktlim@umich.edu cpu->wakeCPU(); 8902292SN/A cpu->activityThisCycle(); 8912292SN/A 8922292SN/A if (store_idx == storeHead) { 8932292SN/A do { 8942292SN/A incrStIdx(storeHead); 8952292SN/A 8962292SN/A --stores; 8972292SN/A } while (storeQueue[storeHead].completed && 8982292SN/A storeHead != storeTail); 8992292SN/A 9002292SN/A iewStage->updateLSQNextCycle = true; 9012292SN/A } 9022292SN/A 9032329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 9042329SN/A "idx:%i\n", 9052329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 9062292SN/A 9072292SN/A if (isStalled() && 9082292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 9092292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 9102292SN/A "load idx:%i\n", 9112292SN/A stallingStoreIsn, stallingLoadIdx); 9122292SN/A stalled = false; 9132292SN/A stallingStoreIsn = 0; 9142292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 9152292SN/A } 9162316SN/A 9172316SN/A storeQueue[store_idx].inst->setCompleted(); 9182329SN/A 9192329SN/A // Tell the checker we've completed this instruction. Some stores 9202329SN/A // may get reported twice to the checker, but the checker can 9212329SN/A // handle that case. 9222733Sktlim@umich.edu#if USE_CHECKER 9232316SN/A if (cpu->checker) { 9242732Sktlim@umich.edu cpu->checker->verify(storeQueue[store_idx].inst); 9252316SN/A } 9262733Sktlim@umich.edu#endif 9272292SN/A} 9282292SN/A 9292292SN/Atemplate <class Impl> 9302693Sktlim@umich.eduvoid 9312693Sktlim@umich.eduLSQUnit<Impl>::recvRetry() 9322693Sktlim@umich.edu{ 9332698Sktlim@umich.edu if (isStoreBlocked) { 9344985Sktlim@umich.edu DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 9352698Sktlim@umich.edu assert(retryPkt != NULL); 9362693Sktlim@umich.edu 9372698Sktlim@umich.edu if (dcachePort->sendTiming(retryPkt)) { 9382698Sktlim@umich.edu storePostSend(retryPkt); 9392699Sktlim@umich.edu retryPkt = NULL; 9402693Sktlim@umich.edu isStoreBlocked = false; 9416221Snate@binkert.org lsq->setRetryTid(InvalidThreadID); 9422693Sktlim@umich.edu } else { 9432693Sktlim@umich.edu // Still blocked! 9442727Sktlim@umich.edu ++lsqCacheBlocked; 9452907Sktlim@umich.edu lsq->setRetryTid(lsqID); 9462693Sktlim@umich.edu } 9472693Sktlim@umich.edu } else if (isLoadBlocked) { 9482693Sktlim@umich.edu DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 9492693Sktlim@umich.edu "no need to resend packet.\n"); 9502693Sktlim@umich.edu } else { 9512693Sktlim@umich.edu DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 9522693Sktlim@umich.edu } 9532693Sktlim@umich.edu} 9542693Sktlim@umich.edu 9552693Sktlim@umich.edutemplate <class Impl> 9562292SN/Ainline void 9572292SN/ALSQUnit<Impl>::incrStIdx(int &store_idx) 9582292SN/A{ 9592292SN/A if (++store_idx >= SQEntries) 9602292SN/A store_idx = 0; 9612292SN/A} 9622292SN/A 9632292SN/Atemplate <class Impl> 9642292SN/Ainline void 9652292SN/ALSQUnit<Impl>::decrStIdx(int &store_idx) 9662292SN/A{ 9672292SN/A if (--store_idx < 0) 9682292SN/A store_idx += SQEntries; 9692292SN/A} 9702292SN/A 9712292SN/Atemplate <class Impl> 9722292SN/Ainline void 9732292SN/ALSQUnit<Impl>::incrLdIdx(int &load_idx) 9742292SN/A{ 9752292SN/A if (++load_idx >= LQEntries) 9762292SN/A load_idx = 0; 9772292SN/A} 9782292SN/A 9792292SN/Atemplate <class Impl> 9802292SN/Ainline void 9812292SN/ALSQUnit<Impl>::decrLdIdx(int &load_idx) 9822292SN/A{ 9832292SN/A if (--load_idx < 0) 9842292SN/A load_idx += LQEntries; 9852292SN/A} 9862329SN/A 9872329SN/Atemplate <class Impl> 9882329SN/Avoid 9892329SN/ALSQUnit<Impl>::dumpInsts() 9902329SN/A{ 9912329SN/A cprintf("Load store queue: Dumping instructions.\n"); 9922329SN/A cprintf("Load queue size: %i\n", loads); 9932329SN/A cprintf("Load queue: "); 9942329SN/A 9952329SN/A int load_idx = loadHead; 9962329SN/A 9972329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 9982329SN/A cprintf("%#x ", loadQueue[load_idx]->readPC()); 9992329SN/A 10002329SN/A incrLdIdx(load_idx); 10012329SN/A } 10022329SN/A 10032329SN/A cprintf("Store queue size: %i\n", stores); 10042329SN/A cprintf("Store queue: "); 10052329SN/A 10062329SN/A int store_idx = storeHead; 10072329SN/A 10082329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 10092329SN/A cprintf("%#x ", storeQueue[store_idx].inst->readPC()); 10102329SN/A 10112329SN/A incrStIdx(store_idx); 10122329SN/A } 10132329SN/A 10142329SN/A cprintf("\n"); 10152329SN/A} 1016