lsq_unit_impl.hh revision 4319
12292SN/A/* 22292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32292SN/A * All rights reserved. 42292SN/A * 52292SN/A * Redistribution and use in source and binary forms, with or without 62292SN/A * modification, are permitted provided that the following conditions are 72292SN/A * met: redistributions of source code must retain the above copyright 82292SN/A * notice, this list of conditions and the following disclaimer; 92292SN/A * redistributions in binary form must reproduce the above copyright 102292SN/A * notice, this list of conditions and the following disclaimer in the 112292SN/A * documentation and/or other materials provided with the distribution; 122292SN/A * neither the name of the copyright holders nor the names of its 132292SN/A * contributors may be used to endorse or promote products derived from 142292SN/A * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292689Sktlim@umich.edu * Korey Sewell 302292SN/A */ 312292SN/A 323326Sktlim@umich.edu#include "arch/locked_mem.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 342733Sktlim@umich.edu 352907Sktlim@umich.edu#include "cpu/o3/lsq.hh" 362292SN/A#include "cpu/o3/lsq_unit.hh" 372292SN/A#include "base/str.hh" 382722Sktlim@umich.edu#include "mem/packet.hh" 392669Sktlim@umich.edu#include "mem/request.hh" 402292SN/A 412790Sktlim@umich.edu#if USE_CHECKER 422790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 432790Sktlim@umich.edu#endif 442790Sktlim@umich.edu 452669Sktlim@umich.edutemplate<class Impl> 462678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 472678Sktlim@umich.edu LSQUnit *lsq_ptr) 482678Sktlim@umich.edu : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 492292SN/A{ 502678Sktlim@umich.edu this->setFlags(Event::AutoDelete); 512292SN/A} 522292SN/A 532669Sktlim@umich.edutemplate<class Impl> 542292SN/Avoid 552678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 562292SN/A{ 572678Sktlim@umich.edu if (!lsqPtr->isSwitchedOut()) { 582678Sktlim@umich.edu lsqPtr->writeback(inst, pkt); 592678Sktlim@umich.edu } 604319Sktlim@umich.edu 614319Sktlim@umich.edu if (pkt->senderState) 624319Sktlim@umich.edu delete pkt->senderState; 634319Sktlim@umich.edu 644319Sktlim@umich.edu delete pkt->req; 652678Sktlim@umich.edu delete pkt; 662678Sktlim@umich.edu} 672292SN/A 682678Sktlim@umich.edutemplate<class Impl> 692678Sktlim@umich.educonst char * 702678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::description() 712678Sktlim@umich.edu{ 722678Sktlim@umich.edu return "Store writeback event"; 732678Sktlim@umich.edu} 742292SN/A 752678Sktlim@umich.edutemplate<class Impl> 762678Sktlim@umich.eduvoid 772678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 782678Sktlim@umich.edu{ 792678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 802678Sktlim@umich.edu DynInstPtr inst = state->inst; 812678Sktlim@umich.edu DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum); 822698Sktlim@umich.edu DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum); 832344SN/A 842678Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 852678Sktlim@umich.edu 862678Sktlim@umich.edu if (isSwitchedOut() || inst->isSquashed()) { 872820Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 882678Sktlim@umich.edu } else { 892678Sktlim@umich.edu if (!state->noWB) { 902678Sktlim@umich.edu writeback(inst, pkt); 912678Sktlim@umich.edu } 922678Sktlim@umich.edu 932678Sktlim@umich.edu if (inst->isStore()) { 942678Sktlim@umich.edu completeStore(state->idx); 952678Sktlim@umich.edu } 962344SN/A } 972307SN/A 982678Sktlim@umich.edu delete state; 994032Sktlim@umich.edu delete pkt->req; 1002678Sktlim@umich.edu delete pkt; 1012292SN/A} 1022292SN/A 1032292SN/Atemplate <class Impl> 1042292SN/ALSQUnit<Impl>::LSQUnit() 1052678Sktlim@umich.edu : loads(0), stores(0), storesToWB(0), stalled(false), 1062678Sktlim@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1072292SN/A loadBlockedHandled(false) 1082292SN/A{ 1092292SN/A} 1102292SN/A 1112292SN/Atemplate<class Impl> 1122292SN/Avoid 1132907Sktlim@umich.eduLSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries, 1142292SN/A unsigned maxSQEntries, unsigned id) 1152292SN/A{ 1164318Sktlim@umich.edu// DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1172292SN/A 1182307SN/A switchedOut = false; 1192307SN/A 1202907Sktlim@umich.edu lsq = lsq_ptr; 1212907Sktlim@umich.edu 1222292SN/A lsqID = id; 1232292SN/A 1242329SN/A // Add 1 for the sentinel entry (they are circular queues). 1252329SN/A LQEntries = maxLQEntries + 1; 1262329SN/A SQEntries = maxSQEntries + 1; 1272292SN/A 1282292SN/A loadQueue.resize(LQEntries); 1292292SN/A storeQueue.resize(SQEntries); 1302292SN/A 1312292SN/A loadHead = loadTail = 0; 1322292SN/A 1332292SN/A storeHead = storeWBIdx = storeTail = 0; 1342292SN/A 1352292SN/A usedPorts = 0; 1362292SN/A cachePorts = params->cachePorts; 1372292SN/A 1383492Sktlim@umich.edu retryPkt = NULL; 1392329SN/A memDepViolator = NULL; 1402292SN/A 1412292SN/A blockedLoadSeqNum = 0; 1422292SN/A} 1432292SN/A 1442292SN/Atemplate<class Impl> 1452669Sktlim@umich.eduvoid 1462733Sktlim@umich.eduLSQUnit<Impl>::setCPU(O3CPU *cpu_ptr) 1472669Sktlim@umich.edu{ 1482669Sktlim@umich.edu cpu = cpu_ptr; 1492678Sktlim@umich.edu 1502733Sktlim@umich.edu#if USE_CHECKER 1512679Sktlim@umich.edu if (cpu->checker) { 1522679Sktlim@umich.edu cpu->checker->setDcachePort(dcachePort); 1532679Sktlim@umich.edu } 1542733Sktlim@umich.edu#endif 1552669Sktlim@umich.edu} 1562669Sktlim@umich.edu 1572669Sktlim@umich.edutemplate<class Impl> 1582292SN/Astd::string 1592292SN/ALSQUnit<Impl>::name() const 1602292SN/A{ 1612292SN/A if (Impl::MaxThreads == 1) { 1622292SN/A return iewStage->name() + ".lsq"; 1632292SN/A } else { 1642292SN/A return iewStage->name() + ".lsq.thread." + to_string(lsqID); 1652292SN/A } 1662292SN/A} 1672292SN/A 1682292SN/Atemplate<class Impl> 1692292SN/Avoid 1702727Sktlim@umich.eduLSQUnit<Impl>::regStats() 1712727Sktlim@umich.edu{ 1722727Sktlim@umich.edu lsqForwLoads 1732727Sktlim@umich.edu .name(name() + ".forwLoads") 1742727Sktlim@umich.edu .desc("Number of loads that had data forwarded from stores"); 1752727Sktlim@umich.edu 1762727Sktlim@umich.edu invAddrLoads 1772727Sktlim@umich.edu .name(name() + ".invAddrLoads") 1782727Sktlim@umich.edu .desc("Number of loads ignored due to an invalid address"); 1792727Sktlim@umich.edu 1802727Sktlim@umich.edu lsqSquashedLoads 1812727Sktlim@umich.edu .name(name() + ".squashedLoads") 1822727Sktlim@umich.edu .desc("Number of loads squashed"); 1832727Sktlim@umich.edu 1842727Sktlim@umich.edu lsqIgnoredResponses 1852727Sktlim@umich.edu .name(name() + ".ignoredResponses") 1862727Sktlim@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 1872727Sktlim@umich.edu 1882361SN/A lsqMemOrderViolation 1892361SN/A .name(name() + ".memOrderViolation") 1902361SN/A .desc("Number of memory ordering violations"); 1912361SN/A 1922727Sktlim@umich.edu lsqSquashedStores 1932727Sktlim@umich.edu .name(name() + ".squashedStores") 1942727Sktlim@umich.edu .desc("Number of stores squashed"); 1952727Sktlim@umich.edu 1962727Sktlim@umich.edu invAddrSwpfs 1972727Sktlim@umich.edu .name(name() + ".invAddrSwpfs") 1982727Sktlim@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 1992727Sktlim@umich.edu 2002727Sktlim@umich.edu lsqBlockedLoads 2012727Sktlim@umich.edu .name(name() + ".blockedLoads") 2022727Sktlim@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 2032727Sktlim@umich.edu 2042727Sktlim@umich.edu lsqRescheduledLoads 2052727Sktlim@umich.edu .name(name() + ".rescheduledLoads") 2062727Sktlim@umich.edu .desc("Number of loads that were rescheduled"); 2072727Sktlim@umich.edu 2082727Sktlim@umich.edu lsqCacheBlocked 2092727Sktlim@umich.edu .name(name() + ".cacheBlocked") 2102727Sktlim@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2112727Sktlim@umich.edu} 2122727Sktlim@umich.edu 2132727Sktlim@umich.edutemplate<class Impl> 2142727Sktlim@umich.eduvoid 2152292SN/ALSQUnit<Impl>::clearLQ() 2162292SN/A{ 2172292SN/A loadQueue.clear(); 2182292SN/A} 2192292SN/A 2202292SN/Atemplate<class Impl> 2212292SN/Avoid 2222292SN/ALSQUnit<Impl>::clearSQ() 2232292SN/A{ 2242292SN/A storeQueue.clear(); 2252292SN/A} 2262292SN/A 2272292SN/Atemplate<class Impl> 2282292SN/Avoid 2292307SN/ALSQUnit<Impl>::switchOut() 2302307SN/A{ 2312307SN/A switchedOut = true; 2322367SN/A for (int i = 0; i < loadQueue.size(); ++i) { 2332367SN/A assert(!loadQueue[i]); 2342307SN/A loadQueue[i] = NULL; 2352367SN/A } 2362307SN/A 2372329SN/A assert(storesToWB == 0); 2382307SN/A} 2392307SN/A 2402307SN/Atemplate<class Impl> 2412307SN/Avoid 2422307SN/ALSQUnit<Impl>::takeOverFrom() 2432307SN/A{ 2442307SN/A switchedOut = false; 2452307SN/A loads = stores = storesToWB = 0; 2462307SN/A 2472307SN/A loadHead = loadTail = 0; 2482307SN/A 2492307SN/A storeHead = storeWBIdx = storeTail = 0; 2502307SN/A 2512307SN/A usedPorts = 0; 2522307SN/A 2532329SN/A memDepViolator = NULL; 2542307SN/A 2552307SN/A blockedLoadSeqNum = 0; 2562307SN/A 2572307SN/A stalled = false; 2582307SN/A isLoadBlocked = false; 2592307SN/A loadBlockedHandled = false; 2602307SN/A} 2612307SN/A 2622307SN/Atemplate<class Impl> 2632307SN/Avoid 2642292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 2652292SN/A{ 2662329SN/A unsigned size_plus_sentinel = size + 1; 2672329SN/A assert(size_plus_sentinel >= LQEntries); 2682292SN/A 2692329SN/A if (size_plus_sentinel > LQEntries) { 2702329SN/A while (size_plus_sentinel > loadQueue.size()) { 2712292SN/A DynInstPtr dummy; 2722292SN/A loadQueue.push_back(dummy); 2732292SN/A LQEntries++; 2742292SN/A } 2752292SN/A } else { 2762329SN/A LQEntries = size_plus_sentinel; 2772292SN/A } 2782292SN/A 2792292SN/A} 2802292SN/A 2812292SN/Atemplate<class Impl> 2822292SN/Avoid 2832292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 2842292SN/A{ 2852329SN/A unsigned size_plus_sentinel = size + 1; 2862329SN/A if (size_plus_sentinel > SQEntries) { 2872329SN/A while (size_plus_sentinel > storeQueue.size()) { 2882292SN/A SQEntry dummy; 2892292SN/A storeQueue.push_back(dummy); 2902292SN/A SQEntries++; 2912292SN/A } 2922292SN/A } else { 2932329SN/A SQEntries = size_plus_sentinel; 2942292SN/A } 2952292SN/A} 2962292SN/A 2972292SN/Atemplate <class Impl> 2982292SN/Avoid 2992292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 3002292SN/A{ 3012292SN/A assert(inst->isMemRef()); 3022292SN/A 3032292SN/A assert(inst->isLoad() || inst->isStore()); 3042292SN/A 3052292SN/A if (inst->isLoad()) { 3062292SN/A insertLoad(inst); 3072292SN/A } else { 3082292SN/A insertStore(inst); 3092292SN/A } 3102292SN/A 3112292SN/A inst->setInLSQ(); 3122292SN/A} 3132292SN/A 3142292SN/Atemplate <class Impl> 3152292SN/Avoid 3162292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3172292SN/A{ 3182329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3192329SN/A assert(loads < LQEntries); 3202292SN/A 3212292SN/A DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n", 3222292SN/A load_inst->readPC(), loadTail, load_inst->seqNum); 3232292SN/A 3242292SN/A load_inst->lqIdx = loadTail; 3252292SN/A 3262292SN/A if (stores == 0) { 3272292SN/A load_inst->sqIdx = -1; 3282292SN/A } else { 3292292SN/A load_inst->sqIdx = storeTail; 3302292SN/A } 3312292SN/A 3322292SN/A loadQueue[loadTail] = load_inst; 3332292SN/A 3342292SN/A incrLdIdx(loadTail); 3352292SN/A 3362292SN/A ++loads; 3372292SN/A} 3382292SN/A 3392292SN/Atemplate <class Impl> 3402292SN/Avoid 3412292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3422292SN/A{ 3432292SN/A // Make sure it is not full before inserting an instruction. 3442292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3452292SN/A assert(stores < SQEntries); 3462292SN/A 3472292SN/A DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n", 3482292SN/A store_inst->readPC(), storeTail, store_inst->seqNum); 3492292SN/A 3502292SN/A store_inst->sqIdx = storeTail; 3512292SN/A store_inst->lqIdx = loadTail; 3522292SN/A 3532292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3542292SN/A 3552292SN/A incrStIdx(storeTail); 3562292SN/A 3572292SN/A ++stores; 3582292SN/A} 3592292SN/A 3602292SN/Atemplate <class Impl> 3612292SN/Atypename Impl::DynInstPtr 3622292SN/ALSQUnit<Impl>::getMemDepViolator() 3632292SN/A{ 3642292SN/A DynInstPtr temp = memDepViolator; 3652292SN/A 3662292SN/A memDepViolator = NULL; 3672292SN/A 3682292SN/A return temp; 3692292SN/A} 3702292SN/A 3712292SN/Atemplate <class Impl> 3722292SN/Aunsigned 3732292SN/ALSQUnit<Impl>::numFreeEntries() 3742292SN/A{ 3752292SN/A unsigned free_lq_entries = LQEntries - loads; 3762292SN/A unsigned free_sq_entries = SQEntries - stores; 3772292SN/A 3782292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 3792292SN/A // empty/full conditions. Subtract 1 from the free entries. 3802292SN/A if (free_lq_entries < free_sq_entries) { 3812292SN/A return free_lq_entries - 1; 3822292SN/A } else { 3832292SN/A return free_sq_entries - 1; 3842292SN/A } 3852292SN/A} 3862292SN/A 3872292SN/Atemplate <class Impl> 3882292SN/Aint 3892292SN/ALSQUnit<Impl>::numLoadsReady() 3902292SN/A{ 3912292SN/A int load_idx = loadHead; 3922292SN/A int retval = 0; 3932292SN/A 3942292SN/A while (load_idx != loadTail) { 3952292SN/A assert(loadQueue[load_idx]); 3962292SN/A 3972292SN/A if (loadQueue[load_idx]->readyToIssue()) { 3982292SN/A ++retval; 3992292SN/A } 4002292SN/A } 4012292SN/A 4022292SN/A return retval; 4032292SN/A} 4042292SN/A 4052292SN/Atemplate <class Impl> 4062292SN/AFault 4072292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 4082292SN/A{ 4094032Sktlim@umich.edu using namespace TheISA; 4102292SN/A // Execute a specific load. 4112292SN/A Fault load_fault = NoFault; 4122292SN/A 4132292SN/A DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n", 4142292SN/A inst->readPC(),inst->seqNum); 4152292SN/A 4164032Sktlim@umich.edu assert(!inst->isSquashed()); 4174032Sktlim@umich.edu 4182669Sktlim@umich.edu load_fault = inst->initiateAcc(); 4192292SN/A 4202292SN/A // If the instruction faulted, then we need to send it along to commit 4212292SN/A // without the instruction completing. 4222292SN/A if (load_fault != NoFault) { 4232329SN/A // Send this instruction to commit, also make sure iew stage 4242329SN/A // realizes there is activity. 4252367SN/A // Mark it as executed unless it is an uncached load that 4262367SN/A // needs to hit the head of commit. 4274032Sktlim@umich.edu if (!(inst->hasRequest() && inst->uncacheable()) || 4283731Sktlim@umich.edu inst->isAtCommit()) { 4292367SN/A inst->setExecuted(); 4302367SN/A } 4312292SN/A iewStage->instToCommit(inst); 4322292SN/A iewStage->activityThisCycle(); 4334032Sktlim@umich.edu } else if (!loadBlocked()) { 4344032Sktlim@umich.edu assert(inst->effAddrValid); 4354032Sktlim@umich.edu int load_idx = inst->lqIdx; 4364032Sktlim@umich.edu incrLdIdx(load_idx); 4374032Sktlim@umich.edu while (load_idx != loadTail) { 4384032Sktlim@umich.edu // Really only need to check loads that have actually executed 4394032Sktlim@umich.edu 4404032Sktlim@umich.edu // @todo: For now this is extra conservative, detecting a 4414032Sktlim@umich.edu // violation if the addresses match assuming all accesses 4424032Sktlim@umich.edu // are quad word accesses. 4434032Sktlim@umich.edu 4444032Sktlim@umich.edu // @todo: Fix this, magic number being used here 4454032Sktlim@umich.edu if (loadQueue[load_idx]->effAddrValid && 4464032Sktlim@umich.edu (loadQueue[load_idx]->effAddr >> 8) == 4474032Sktlim@umich.edu (inst->effAddr >> 8)) { 4484032Sktlim@umich.edu // A load incorrectly passed this load. Squash and refetch. 4494032Sktlim@umich.edu // For now return a fault to show that it was unsuccessful. 4504032Sktlim@umich.edu DynInstPtr violator = loadQueue[load_idx]; 4514032Sktlim@umich.edu if (!memDepViolator || 4524032Sktlim@umich.edu (violator->seqNum < memDepViolator->seqNum)) { 4534032Sktlim@umich.edu memDepViolator = violator; 4544032Sktlim@umich.edu } else { 4554032Sktlim@umich.edu break; 4564032Sktlim@umich.edu } 4574032Sktlim@umich.edu 4584032Sktlim@umich.edu ++lsqMemOrderViolation; 4594032Sktlim@umich.edu 4604032Sktlim@umich.edu return genMachineCheckFault(); 4614032Sktlim@umich.edu } 4624032Sktlim@umich.edu 4634032Sktlim@umich.edu incrLdIdx(load_idx); 4644032Sktlim@umich.edu } 4652292SN/A } 4662292SN/A 4672292SN/A return load_fault; 4682292SN/A} 4692292SN/A 4702292SN/Atemplate <class Impl> 4712292SN/AFault 4722292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 4732292SN/A{ 4742292SN/A using namespace TheISA; 4752292SN/A // Make sure that a store exists. 4762292SN/A assert(stores != 0); 4772292SN/A 4782292SN/A int store_idx = store_inst->sqIdx; 4792292SN/A 4802292SN/A DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n", 4812292SN/A store_inst->readPC(), store_inst->seqNum); 4822292SN/A 4834032Sktlim@umich.edu assert(!store_inst->isSquashed()); 4844032Sktlim@umich.edu 4852292SN/A // Check the recently completed loads to see if any match this store's 4862292SN/A // address. If so, then we have a memory ordering violation. 4872292SN/A int load_idx = store_inst->lqIdx; 4882292SN/A 4892292SN/A Fault store_fault = store_inst->initiateAcc(); 4902292SN/A 4912329SN/A if (storeQueue[store_idx].size == 0) { 4922292SN/A DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n", 4932292SN/A store_inst->readPC(),store_inst->seqNum); 4942292SN/A 4952292SN/A return store_fault; 4962292SN/A } 4972292SN/A 4982292SN/A assert(store_fault == NoFault); 4992292SN/A 5002336SN/A if (store_inst->isStoreConditional()) { 5012336SN/A // Store conditionals need to set themselves as able to 5022336SN/A // writeback if we haven't had a fault by here. 5032329SN/A storeQueue[store_idx].canWB = true; 5042292SN/A 5052329SN/A ++storesToWB; 5062292SN/A } 5072292SN/A 5084032Sktlim@umich.edu assert(store_inst->effAddrValid); 5094032Sktlim@umich.edu while (load_idx != loadTail) { 5104032Sktlim@umich.edu // Really only need to check loads that have actually executed 5114032Sktlim@umich.edu // It's safe to check all loads because effAddr is set to 5124032Sktlim@umich.edu // InvalAddr when the dyn inst is created. 5132292SN/A 5144032Sktlim@umich.edu // @todo: For now this is extra conservative, detecting a 5154032Sktlim@umich.edu // violation if the addresses match assuming all accesses 5164032Sktlim@umich.edu // are quad word accesses. 5172329SN/A 5184032Sktlim@umich.edu // @todo: Fix this, magic number being used here 5194032Sktlim@umich.edu if (loadQueue[load_idx]->effAddrValid && 5204032Sktlim@umich.edu (loadQueue[load_idx]->effAddr >> 8) == 5214032Sktlim@umich.edu (store_inst->effAddr >> 8)) { 5224032Sktlim@umich.edu // A load incorrectly passed this store. Squash and refetch. 5234032Sktlim@umich.edu // For now return a fault to show that it was unsuccessful. 5244032Sktlim@umich.edu DynInstPtr violator = loadQueue[load_idx]; 5254032Sktlim@umich.edu if (!memDepViolator || 5264032Sktlim@umich.edu (violator->seqNum < memDepViolator->seqNum)) { 5274032Sktlim@umich.edu memDepViolator = violator; 5284032Sktlim@umich.edu } else { 5294032Sktlim@umich.edu break; 5302292SN/A } 5312292SN/A 5324032Sktlim@umich.edu ++lsqMemOrderViolation; 5334032Sktlim@umich.edu 5344032Sktlim@umich.edu return genMachineCheckFault(); 5352292SN/A } 5362292SN/A 5374032Sktlim@umich.edu incrLdIdx(load_idx); 5382292SN/A } 5392292SN/A 5402292SN/A return store_fault; 5412292SN/A} 5422292SN/A 5432292SN/Atemplate <class Impl> 5442292SN/Avoid 5452292SN/ALSQUnit<Impl>::commitLoad() 5462292SN/A{ 5472292SN/A assert(loadQueue[loadHead]); 5482292SN/A 5492292SN/A DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n", 5502292SN/A loadQueue[loadHead]->readPC()); 5512292SN/A 5522292SN/A loadQueue[loadHead] = NULL; 5532292SN/A 5542292SN/A incrLdIdx(loadHead); 5552292SN/A 5562292SN/A --loads; 5572292SN/A} 5582292SN/A 5592292SN/Atemplate <class Impl> 5602292SN/Avoid 5612292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 5622292SN/A{ 5632292SN/A assert(loads == 0 || loadQueue[loadHead]); 5642292SN/A 5652292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 5662292SN/A commitLoad(); 5672292SN/A } 5682292SN/A} 5692292SN/A 5702292SN/Atemplate <class Impl> 5712292SN/Avoid 5722292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 5732292SN/A{ 5742292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 5752292SN/A 5762292SN/A int store_idx = storeHead; 5772292SN/A 5782292SN/A while (store_idx != storeTail) { 5792292SN/A assert(storeQueue[store_idx].inst); 5802329SN/A // Mark any stores that are now committed and have not yet 5812329SN/A // been marked as able to write back. 5822292SN/A if (!storeQueue[store_idx].canWB) { 5832292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 5842292SN/A break; 5852292SN/A } 5862292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 5872292SN/A "%#x [sn:%lli]\n", 5882292SN/A storeQueue[store_idx].inst->readPC(), 5892292SN/A storeQueue[store_idx].inst->seqNum); 5902292SN/A 5912292SN/A storeQueue[store_idx].canWB = true; 5922292SN/A 5932292SN/A ++storesToWB; 5942292SN/A } 5952292SN/A 5962292SN/A incrStIdx(store_idx); 5972292SN/A } 5982292SN/A} 5992292SN/A 6002292SN/Atemplate <class Impl> 6012292SN/Avoid 6022292SN/ALSQUnit<Impl>::writebackStores() 6032292SN/A{ 6042292SN/A while (storesToWB > 0 && 6052292SN/A storeWBIdx != storeTail && 6062292SN/A storeQueue[storeWBIdx].inst && 6072292SN/A storeQueue[storeWBIdx].canWB && 6082292SN/A usedPorts < cachePorts) { 6092292SN/A 6102907Sktlim@umich.edu if (isStoreBlocked || lsq->cacheBlocked()) { 6112678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 6122678Sktlim@umich.edu " is blocked!\n"); 6132678Sktlim@umich.edu break; 6142678Sktlim@umich.edu } 6152678Sktlim@umich.edu 6162329SN/A // Store didn't write any data so no need to write it back to 6172329SN/A // memory. 6182292SN/A if (storeQueue[storeWBIdx].size == 0) { 6192292SN/A completeStore(storeWBIdx); 6202292SN/A 6212292SN/A incrStIdx(storeWBIdx); 6222292SN/A 6232292SN/A continue; 6242292SN/A } 6252678Sktlim@umich.edu 6262292SN/A ++usedPorts; 6272292SN/A 6282292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 6292292SN/A incrStIdx(storeWBIdx); 6302292SN/A 6312292SN/A continue; 6322292SN/A } 6332292SN/A 6342292SN/A assert(storeQueue[storeWBIdx].req); 6352292SN/A assert(!storeQueue[storeWBIdx].committed); 6362292SN/A 6372669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 6382669Sktlim@umich.edu 6392669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 6402292SN/A storeQueue[storeWBIdx].committed = true; 6412292SN/A 6422669Sktlim@umich.edu assert(!inst->memData); 6432669Sktlim@umich.edu inst->memData = new uint8_t[64]; 6443772Sgblack@eecs.umich.edu 6453772Sgblack@eecs.umich.edu TheISA::IntReg convertedData = 6463772Sgblack@eecs.umich.edu TheISA::htog(storeQueue[storeWBIdx].data); 6473772Sgblack@eecs.umich.edu 6483797Sgblack@eecs.umich.edu //FIXME This is a hack to get SPARC working. It, along with endianness 6493797Sgblack@eecs.umich.edu //in the memory system in general, need to be straightened out more 6503797Sgblack@eecs.umich.edu //formally. The problem is that the data's endianness is swapped when 6513797Sgblack@eecs.umich.edu //it's in the 64 bit data field in the store queue. The data that you 6523797Sgblack@eecs.umich.edu //want won't start at the beginning of the field anymore unless it was 6533797Sgblack@eecs.umich.edu //a 64 bit access. 6543797Sgblack@eecs.umich.edu memcpy(inst->memData, 6553797Sgblack@eecs.umich.edu (uint8_t *)&convertedData + 6563797Sgblack@eecs.umich.edu (TheISA::ByteOrderDiffers ? 6573797Sgblack@eecs.umich.edu (sizeof(TheISA::IntReg) - req->getSize()) : 0), 6583797Sgblack@eecs.umich.edu req->getSize()); 6592669Sktlim@umich.edu 6604022Sstever@eecs.umich.edu PacketPtr data_pkt = new Packet(req, MemCmd::WriteReq, 6614022Sstever@eecs.umich.edu Packet::Broadcast); 6622669Sktlim@umich.edu data_pkt->dataStatic(inst->memData); 6632292SN/A 6642678Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 6652678Sktlim@umich.edu state->isLoad = false; 6662678Sktlim@umich.edu state->idx = storeWBIdx; 6672678Sktlim@umich.edu state->inst = inst; 6682678Sktlim@umich.edu data_pkt->senderState = state; 6692678Sktlim@umich.edu 6702292SN/A DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " 6712292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 6723221Sktlim@umich.edu storeWBIdx, inst->readPC(), 6733797Sgblack@eecs.umich.edu req->getPaddr(), (int)*(inst->memData), 6743221Sktlim@umich.edu inst->seqNum); 6752292SN/A 6762693Sktlim@umich.edu // @todo: Remove this SC hack once the memory system handles it. 6773172Sstever@eecs.umich.edu if (req->isLocked()) { 6783326Sktlim@umich.edu // Disable recording the result temporarily. Writing to 6793326Sktlim@umich.edu // misc regs normally updates the result, but this is not 6803326Sktlim@umich.edu // the desired behavior when handling store conditionals. 6813326Sktlim@umich.edu inst->recordResult = false; 6823326Sktlim@umich.edu bool success = TheISA::handleLockedWrite(inst.get(), req); 6833326Sktlim@umich.edu inst->recordResult = true; 6843326Sktlim@umich.edu 6853326Sktlim@umich.edu if (!success) { 6863326Sktlim@umich.edu // Instantly complete this store. 6873326Sktlim@umich.edu DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 6883326Sktlim@umich.edu "Instantly completing it.\n", 6893326Sktlim@umich.edu inst->seqNum); 6903326Sktlim@umich.edu WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 6913326Sktlim@umich.edu wb->schedule(curTick + 1); 6923326Sktlim@umich.edu delete state; 6933326Sktlim@umich.edu completeStore(storeWBIdx); 6943326Sktlim@umich.edu incrStIdx(storeWBIdx); 6953326Sktlim@umich.edu continue; 6962693Sktlim@umich.edu } 6972693Sktlim@umich.edu } else { 6982693Sktlim@umich.edu // Non-store conditionals do not need a writeback. 6992693Sktlim@umich.edu state->noWB = true; 7002693Sktlim@umich.edu } 7012693Sktlim@umich.edu 7022669Sktlim@umich.edu if (!dcachePort->sendTiming(data_pkt)) { 7033221Sktlim@umich.edu if (data_pkt->result == Packet::BadAddress) { 7043221Sktlim@umich.edu panic("LSQ sent out a bad address for a completed store!"); 7053221Sktlim@umich.edu } 7062669Sktlim@umich.edu // Need to handle becoming blocked on a store. 7074032Sktlim@umich.edu DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 7083221Sktlim@umich.edu "retry later\n", 7093221Sktlim@umich.edu inst->seqNum); 7102678Sktlim@umich.edu isStoreBlocked = true; 7112727Sktlim@umich.edu ++lsqCacheBlocked; 7122698Sktlim@umich.edu assert(retryPkt == NULL); 7132698Sktlim@umich.edu retryPkt = data_pkt; 7143014Srdreslin@umich.edu lsq->setRetryTid(lsqID); 7152669Sktlim@umich.edu } else { 7162693Sktlim@umich.edu storePostSend(data_pkt); 7172292SN/A } 7182292SN/A } 7192292SN/A 7202292SN/A // Not sure this should set it to 0. 7212292SN/A usedPorts = 0; 7222292SN/A 7232292SN/A assert(stores >= 0 && storesToWB >= 0); 7242292SN/A} 7252292SN/A 7262292SN/A/*template <class Impl> 7272292SN/Avoid 7282292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 7292292SN/A{ 7302292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 7312292SN/A mshrSeqNums.end(), 7322292SN/A seqNum); 7332292SN/A 7342292SN/A if (mshr_it != mshrSeqNums.end()) { 7352292SN/A mshrSeqNums.erase(mshr_it); 7362292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 7372292SN/A } 7382292SN/A}*/ 7392292SN/A 7402292SN/Atemplate <class Impl> 7412292SN/Avoid 7422292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 7432292SN/A{ 7442292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 7452329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 7462292SN/A 7472292SN/A int load_idx = loadTail; 7482292SN/A decrLdIdx(load_idx); 7492292SN/A 7502292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 7512292SN/A DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, " 7522292SN/A "[sn:%lli]\n", 7532292SN/A loadQueue[load_idx]->readPC(), 7542292SN/A loadQueue[load_idx]->seqNum); 7552292SN/A 7562292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 7572292SN/A stalled = false; 7582292SN/A stallingStoreIsn = 0; 7592292SN/A stallingLoadIdx = 0; 7602292SN/A } 7612292SN/A 7622329SN/A // Clear the smart pointer to make sure it is decremented. 7632731Sktlim@umich.edu loadQueue[load_idx]->setSquashed(); 7642292SN/A loadQueue[load_idx] = NULL; 7652292SN/A --loads; 7662292SN/A 7672292SN/A // Inefficient! 7682292SN/A loadTail = load_idx; 7692292SN/A 7702292SN/A decrLdIdx(load_idx); 7712727Sktlim@umich.edu ++lsqSquashedLoads; 7722292SN/A } 7732292SN/A 7742292SN/A if (isLoadBlocked) { 7752292SN/A if (squashed_num < blockedLoadSeqNum) { 7762292SN/A isLoadBlocked = false; 7772292SN/A loadBlockedHandled = false; 7782292SN/A blockedLoadSeqNum = 0; 7792292SN/A } 7802292SN/A } 7812292SN/A 7824032Sktlim@umich.edu if (memDepViolator && squashed_num < memDepViolator->seqNum) { 7834032Sktlim@umich.edu memDepViolator = NULL; 7844032Sktlim@umich.edu } 7854032Sktlim@umich.edu 7862292SN/A int store_idx = storeTail; 7872292SN/A decrStIdx(store_idx); 7882292SN/A 7892292SN/A while (stores != 0 && 7902292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 7912329SN/A // Instructions marked as can WB are already committed. 7922292SN/A if (storeQueue[store_idx].canWB) { 7932292SN/A break; 7942292SN/A } 7952292SN/A 7962292SN/A DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, " 7972292SN/A "idx:%i [sn:%lli]\n", 7982292SN/A storeQueue[store_idx].inst->readPC(), 7992292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 8002292SN/A 8012329SN/A // I don't think this can happen. It should have been cleared 8022329SN/A // by the stalling load. 8032292SN/A if (isStalled() && 8042292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 8052292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 8062292SN/A stalled = false; 8072292SN/A stallingStoreIsn = 0; 8082292SN/A } 8092292SN/A 8102329SN/A // Clear the smart pointer to make sure it is decremented. 8112731Sktlim@umich.edu storeQueue[store_idx].inst->setSquashed(); 8122292SN/A storeQueue[store_idx].inst = NULL; 8132292SN/A storeQueue[store_idx].canWB = 0; 8142292SN/A 8154032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 8164032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the proper 8174032Sktlim@umich.edu // place to really handle request deletes. 8184032Sktlim@umich.edu delete storeQueue[store_idx].req; 8194032Sktlim@umich.edu 8202292SN/A storeQueue[store_idx].req = NULL; 8212292SN/A --stores; 8222292SN/A 8232292SN/A // Inefficient! 8242292SN/A storeTail = store_idx; 8252292SN/A 8262292SN/A decrStIdx(store_idx); 8272727Sktlim@umich.edu ++lsqSquashedStores; 8282292SN/A } 8292292SN/A} 8302292SN/A 8312292SN/Atemplate <class Impl> 8322292SN/Avoid 8333349Sbinkertn@umich.eduLSQUnit<Impl>::storePostSend(PacketPtr pkt) 8342693Sktlim@umich.edu{ 8352693Sktlim@umich.edu if (isStalled() && 8362693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 8372693Sktlim@umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 8382693Sktlim@umich.edu "load idx:%i\n", 8392693Sktlim@umich.edu stallingStoreIsn, stallingLoadIdx); 8402693Sktlim@umich.edu stalled = false; 8412693Sktlim@umich.edu stallingStoreIsn = 0; 8422693Sktlim@umich.edu iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 8432693Sktlim@umich.edu } 8442693Sktlim@umich.edu 8452693Sktlim@umich.edu if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 8462693Sktlim@umich.edu // The store is basically completed at this time. This 8472693Sktlim@umich.edu // only works so long as the checker doesn't try to 8482693Sktlim@umich.edu // verify the value in memory for stores. 8492693Sktlim@umich.edu storeQueue[storeWBIdx].inst->setCompleted(); 8502733Sktlim@umich.edu#if USE_CHECKER 8512693Sktlim@umich.edu if (cpu->checker) { 8522732Sktlim@umich.edu cpu->checker->verify(storeQueue[storeWBIdx].inst); 8532693Sktlim@umich.edu } 8542733Sktlim@umich.edu#endif 8552693Sktlim@umich.edu } 8562693Sktlim@umich.edu 8572693Sktlim@umich.edu if (pkt->result != Packet::Success) { 8582693Sktlim@umich.edu DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n", 8592693Sktlim@umich.edu storeWBIdx); 8602693Sktlim@umich.edu 8612693Sktlim@umich.edu DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n", 8622693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum); 8632693Sktlim@umich.edu 8642693Sktlim@umich.edu //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum); 8652693Sktlim@umich.edu 8662693Sktlim@umich.edu //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size()); 8672693Sktlim@umich.edu 8682693Sktlim@umich.edu // @todo: Increment stat here. 8692693Sktlim@umich.edu } else { 8702693Sktlim@umich.edu DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n", 8712693Sktlim@umich.edu storeWBIdx); 8722693Sktlim@umich.edu 8732693Sktlim@umich.edu DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", 8742693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum); 8752693Sktlim@umich.edu } 8762693Sktlim@umich.edu 8772693Sktlim@umich.edu incrStIdx(storeWBIdx); 8782693Sktlim@umich.edu} 8792693Sktlim@umich.edu 8802693Sktlim@umich.edutemplate <class Impl> 8812693Sktlim@umich.eduvoid 8822678Sktlim@umich.eduLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 8832678Sktlim@umich.edu{ 8842678Sktlim@umich.edu iewStage->wakeCPU(); 8852678Sktlim@umich.edu 8862678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 8872678Sktlim@umich.edu if (inst->isSquashed()) { 8882927Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 8892678Sktlim@umich.edu assert(!inst->isStore()); 8902727Sktlim@umich.edu ++lsqIgnoredResponses; 8912678Sktlim@umich.edu return; 8922678Sktlim@umich.edu } 8932678Sktlim@umich.edu 8942678Sktlim@umich.edu if (!inst->isExecuted()) { 8952678Sktlim@umich.edu inst->setExecuted(); 8962678Sktlim@umich.edu 8972678Sktlim@umich.edu // Complete access to copy data to proper place. 8982678Sktlim@umich.edu inst->completeAcc(pkt); 8992678Sktlim@umich.edu } 9002678Sktlim@umich.edu 9012678Sktlim@umich.edu // Need to insert instruction into queue to commit 9022678Sktlim@umich.edu iewStage->instToCommit(inst); 9032678Sktlim@umich.edu 9042678Sktlim@umich.edu iewStage->activityThisCycle(); 9052678Sktlim@umich.edu} 9062678Sktlim@umich.edu 9072678Sktlim@umich.edutemplate <class Impl> 9082678Sktlim@umich.eduvoid 9092292SN/ALSQUnit<Impl>::completeStore(int store_idx) 9102292SN/A{ 9112292SN/A assert(storeQueue[store_idx].inst); 9122292SN/A storeQueue[store_idx].completed = true; 9132292SN/A --storesToWB; 9142292SN/A // A bit conservative because a store completion may not free up entries, 9152292SN/A // but hopefully avoids two store completions in one cycle from making 9162292SN/A // the CPU tick twice. 9173126Sktlim@umich.edu cpu->wakeCPU(); 9182292SN/A cpu->activityThisCycle(); 9192292SN/A 9202292SN/A if (store_idx == storeHead) { 9212292SN/A do { 9222292SN/A incrStIdx(storeHead); 9232292SN/A 9242292SN/A --stores; 9252292SN/A } while (storeQueue[storeHead].completed && 9262292SN/A storeHead != storeTail); 9272292SN/A 9282292SN/A iewStage->updateLSQNextCycle = true; 9292292SN/A } 9302292SN/A 9312329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 9322329SN/A "idx:%i\n", 9332329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 9342292SN/A 9352292SN/A if (isStalled() && 9362292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 9372292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 9382292SN/A "load idx:%i\n", 9392292SN/A stallingStoreIsn, stallingLoadIdx); 9402292SN/A stalled = false; 9412292SN/A stallingStoreIsn = 0; 9422292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 9432292SN/A } 9442316SN/A 9452316SN/A storeQueue[store_idx].inst->setCompleted(); 9462329SN/A 9472329SN/A // Tell the checker we've completed this instruction. Some stores 9482329SN/A // may get reported twice to the checker, but the checker can 9492329SN/A // handle that case. 9502733Sktlim@umich.edu#if USE_CHECKER 9512316SN/A if (cpu->checker) { 9522732Sktlim@umich.edu cpu->checker->verify(storeQueue[store_idx].inst); 9532316SN/A } 9542733Sktlim@umich.edu#endif 9552292SN/A} 9562292SN/A 9572292SN/Atemplate <class Impl> 9582693Sktlim@umich.eduvoid 9592693Sktlim@umich.eduLSQUnit<Impl>::recvRetry() 9602693Sktlim@umich.edu{ 9612698Sktlim@umich.edu if (isStoreBlocked) { 9622698Sktlim@umich.edu assert(retryPkt != NULL); 9632693Sktlim@umich.edu 9642698Sktlim@umich.edu if (dcachePort->sendTiming(retryPkt)) { 9653221Sktlim@umich.edu if (retryPkt->result == Packet::BadAddress) { 9663221Sktlim@umich.edu panic("LSQ sent out a bad address for a completed store!"); 9673221Sktlim@umich.edu } 9682698Sktlim@umich.edu storePostSend(retryPkt); 9692699Sktlim@umich.edu retryPkt = NULL; 9702693Sktlim@umich.edu isStoreBlocked = false; 9713014Srdreslin@umich.edu lsq->setRetryTid(-1); 9722693Sktlim@umich.edu } else { 9732693Sktlim@umich.edu // Still blocked! 9742727Sktlim@umich.edu ++lsqCacheBlocked; 9752907Sktlim@umich.edu lsq->setRetryTid(lsqID); 9762693Sktlim@umich.edu } 9772693Sktlim@umich.edu } else if (isLoadBlocked) { 9782693Sktlim@umich.edu DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 9792693Sktlim@umich.edu "no need to resend packet.\n"); 9802693Sktlim@umich.edu } else { 9812693Sktlim@umich.edu DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 9822693Sktlim@umich.edu } 9832693Sktlim@umich.edu} 9842693Sktlim@umich.edu 9852693Sktlim@umich.edutemplate <class Impl> 9862292SN/Ainline void 9872292SN/ALSQUnit<Impl>::incrStIdx(int &store_idx) 9882292SN/A{ 9892292SN/A if (++store_idx >= SQEntries) 9902292SN/A store_idx = 0; 9912292SN/A} 9922292SN/A 9932292SN/Atemplate <class Impl> 9942292SN/Ainline void 9952292SN/ALSQUnit<Impl>::decrStIdx(int &store_idx) 9962292SN/A{ 9972292SN/A if (--store_idx < 0) 9982292SN/A store_idx += SQEntries; 9992292SN/A} 10002292SN/A 10012292SN/Atemplate <class Impl> 10022292SN/Ainline void 10032292SN/ALSQUnit<Impl>::incrLdIdx(int &load_idx) 10042292SN/A{ 10052292SN/A if (++load_idx >= LQEntries) 10062292SN/A load_idx = 0; 10072292SN/A} 10082292SN/A 10092292SN/Atemplate <class Impl> 10102292SN/Ainline void 10112292SN/ALSQUnit<Impl>::decrLdIdx(int &load_idx) 10122292SN/A{ 10132292SN/A if (--load_idx < 0) 10142292SN/A load_idx += LQEntries; 10152292SN/A} 10162329SN/A 10172329SN/Atemplate <class Impl> 10182329SN/Avoid 10192329SN/ALSQUnit<Impl>::dumpInsts() 10202329SN/A{ 10212329SN/A cprintf("Load store queue: Dumping instructions.\n"); 10222329SN/A cprintf("Load queue size: %i\n", loads); 10232329SN/A cprintf("Load queue: "); 10242329SN/A 10252329SN/A int load_idx = loadHead; 10262329SN/A 10272329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 10282329SN/A cprintf("%#x ", loadQueue[load_idx]->readPC()); 10292329SN/A 10302329SN/A incrLdIdx(load_idx); 10312329SN/A } 10322329SN/A 10332329SN/A cprintf("Store queue size: %i\n", stores); 10342329SN/A cprintf("Store queue: "); 10352329SN/A 10362329SN/A int store_idx = storeHead; 10372329SN/A 10382329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 10392329SN/A cprintf("%#x ", storeQueue[store_idx].inst->readPC()); 10402329SN/A 10412329SN/A incrStIdx(store_idx); 10422329SN/A } 10432329SN/A 10442329SN/A cprintf("\n"); 10452329SN/A} 1046