lsq_unit_impl.hh revision 3731
12292SN/A/* 22292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32292SN/A * All rights reserved. 42292SN/A * 52292SN/A * Redistribution and use in source and binary forms, with or without 62292SN/A * modification, are permitted provided that the following conditions are 72292SN/A * met: redistributions of source code must retain the above copyright 82292SN/A * notice, this list of conditions and the following disclaimer; 92292SN/A * redistributions in binary form must reproduce the above copyright 102292SN/A * notice, this list of conditions and the following disclaimer in the 112292SN/A * documentation and/or other materials provided with the distribution; 122292SN/A * neither the name of the copyright holders nor the names of its 132292SN/A * contributors may be used to endorse or promote products derived from 142292SN/A * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292689Sktlim@umich.edu * Korey Sewell 302292SN/A */ 312292SN/A 323326Sktlim@umich.edu#include "arch/locked_mem.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 342733Sktlim@umich.edu 352907Sktlim@umich.edu#include "cpu/o3/lsq.hh" 362292SN/A#include "cpu/o3/lsq_unit.hh" 372292SN/A#include "base/str.hh" 382722Sktlim@umich.edu#include "mem/packet.hh" 392669Sktlim@umich.edu#include "mem/request.hh" 402292SN/A 412790Sktlim@umich.edu#if USE_CHECKER 422790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 432790Sktlim@umich.edu#endif 442790Sktlim@umich.edu 452669Sktlim@umich.edutemplate<class Impl> 462678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 472678Sktlim@umich.edu LSQUnit *lsq_ptr) 482678Sktlim@umich.edu : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 492292SN/A{ 502678Sktlim@umich.edu this->setFlags(Event::AutoDelete); 512292SN/A} 522292SN/A 532669Sktlim@umich.edutemplate<class Impl> 542292SN/Avoid 552678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 562292SN/A{ 572678Sktlim@umich.edu if (!lsqPtr->isSwitchedOut()) { 582678Sktlim@umich.edu lsqPtr->writeback(inst, pkt); 592678Sktlim@umich.edu } 602678Sktlim@umich.edu delete pkt; 612678Sktlim@umich.edu} 622292SN/A 632678Sktlim@umich.edutemplate<class Impl> 642678Sktlim@umich.educonst char * 652678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::description() 662678Sktlim@umich.edu{ 672678Sktlim@umich.edu return "Store writeback event"; 682678Sktlim@umich.edu} 692292SN/A 702678Sktlim@umich.edutemplate<class Impl> 712678Sktlim@umich.eduvoid 722678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 732678Sktlim@umich.edu{ 742678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 752678Sktlim@umich.edu DynInstPtr inst = state->inst; 762678Sktlim@umich.edu DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum); 772698Sktlim@umich.edu DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum); 782344SN/A 792678Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 802678Sktlim@umich.edu 812678Sktlim@umich.edu if (isSwitchedOut() || inst->isSquashed()) { 822820Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 832678Sktlim@umich.edu delete state; 842678Sktlim@umich.edu delete pkt; 852307SN/A return; 862678Sktlim@umich.edu } else { 872678Sktlim@umich.edu if (!state->noWB) { 882678Sktlim@umich.edu writeback(inst, pkt); 892678Sktlim@umich.edu } 902678Sktlim@umich.edu 912678Sktlim@umich.edu if (inst->isStore()) { 922678Sktlim@umich.edu completeStore(state->idx); 932678Sktlim@umich.edu } 942344SN/A } 952307SN/A 962678Sktlim@umich.edu delete state; 972678Sktlim@umich.edu delete pkt; 982292SN/A} 992292SN/A 1002292SN/Atemplate <class Impl> 1012292SN/ALSQUnit<Impl>::LSQUnit() 1022678Sktlim@umich.edu : loads(0), stores(0), storesToWB(0), stalled(false), 1032678Sktlim@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1042292SN/A loadBlockedHandled(false) 1052292SN/A{ 1062292SN/A} 1072292SN/A 1082292SN/Atemplate<class Impl> 1092292SN/Avoid 1102907Sktlim@umich.eduLSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries, 1112292SN/A unsigned maxSQEntries, unsigned id) 1122292SN/A{ 1132292SN/A DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1142292SN/A 1152307SN/A switchedOut = false; 1162307SN/A 1172907Sktlim@umich.edu lsq = lsq_ptr; 1182907Sktlim@umich.edu 1192292SN/A lsqID = id; 1202292SN/A 1212329SN/A // Add 1 for the sentinel entry (they are circular queues). 1222329SN/A LQEntries = maxLQEntries + 1; 1232329SN/A SQEntries = maxSQEntries + 1; 1242292SN/A 1252292SN/A loadQueue.resize(LQEntries); 1262292SN/A storeQueue.resize(SQEntries); 1272292SN/A 1282292SN/A loadHead = loadTail = 0; 1292292SN/A 1302292SN/A storeHead = storeWBIdx = storeTail = 0; 1312292SN/A 1322292SN/A usedPorts = 0; 1332292SN/A cachePorts = params->cachePorts; 1342292SN/A 1353492Sktlim@umich.edu retryPkt = NULL; 1362329SN/A memDepViolator = NULL; 1372292SN/A 1382292SN/A blockedLoadSeqNum = 0; 1392292SN/A} 1402292SN/A 1412292SN/Atemplate<class Impl> 1422669Sktlim@umich.eduvoid 1432733Sktlim@umich.eduLSQUnit<Impl>::setCPU(O3CPU *cpu_ptr) 1442669Sktlim@umich.edu{ 1452669Sktlim@umich.edu cpu = cpu_ptr; 1462678Sktlim@umich.edu 1472733Sktlim@umich.edu#if USE_CHECKER 1482679Sktlim@umich.edu if (cpu->checker) { 1492679Sktlim@umich.edu cpu->checker->setDcachePort(dcachePort); 1502679Sktlim@umich.edu } 1512733Sktlim@umich.edu#endif 1522669Sktlim@umich.edu} 1532669Sktlim@umich.edu 1542669Sktlim@umich.edutemplate<class Impl> 1552292SN/Astd::string 1562292SN/ALSQUnit<Impl>::name() const 1572292SN/A{ 1582292SN/A if (Impl::MaxThreads == 1) { 1592292SN/A return iewStage->name() + ".lsq"; 1602292SN/A } else { 1612292SN/A return iewStage->name() + ".lsq.thread." + to_string(lsqID); 1622292SN/A } 1632292SN/A} 1642292SN/A 1652292SN/Atemplate<class Impl> 1662292SN/Avoid 1672727Sktlim@umich.eduLSQUnit<Impl>::regStats() 1682727Sktlim@umich.edu{ 1692727Sktlim@umich.edu lsqForwLoads 1702727Sktlim@umich.edu .name(name() + ".forwLoads") 1712727Sktlim@umich.edu .desc("Number of loads that had data forwarded from stores"); 1722727Sktlim@umich.edu 1732727Sktlim@umich.edu invAddrLoads 1742727Sktlim@umich.edu .name(name() + ".invAddrLoads") 1752727Sktlim@umich.edu .desc("Number of loads ignored due to an invalid address"); 1762727Sktlim@umich.edu 1772727Sktlim@umich.edu lsqSquashedLoads 1782727Sktlim@umich.edu .name(name() + ".squashedLoads") 1792727Sktlim@umich.edu .desc("Number of loads squashed"); 1802727Sktlim@umich.edu 1812727Sktlim@umich.edu lsqIgnoredResponses 1822727Sktlim@umich.edu .name(name() + ".ignoredResponses") 1832727Sktlim@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 1842727Sktlim@umich.edu 1852361SN/A lsqMemOrderViolation 1862361SN/A .name(name() + ".memOrderViolation") 1872361SN/A .desc("Number of memory ordering violations"); 1882361SN/A 1892727Sktlim@umich.edu lsqSquashedStores 1902727Sktlim@umich.edu .name(name() + ".squashedStores") 1912727Sktlim@umich.edu .desc("Number of stores squashed"); 1922727Sktlim@umich.edu 1932727Sktlim@umich.edu invAddrSwpfs 1942727Sktlim@umich.edu .name(name() + ".invAddrSwpfs") 1952727Sktlim@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 1962727Sktlim@umich.edu 1972727Sktlim@umich.edu lsqBlockedLoads 1982727Sktlim@umich.edu .name(name() + ".blockedLoads") 1992727Sktlim@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 2002727Sktlim@umich.edu 2012727Sktlim@umich.edu lsqRescheduledLoads 2022727Sktlim@umich.edu .name(name() + ".rescheduledLoads") 2032727Sktlim@umich.edu .desc("Number of loads that were rescheduled"); 2042727Sktlim@umich.edu 2052727Sktlim@umich.edu lsqCacheBlocked 2062727Sktlim@umich.edu .name(name() + ".cacheBlocked") 2072727Sktlim@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2082727Sktlim@umich.edu} 2092727Sktlim@umich.edu 2102727Sktlim@umich.edutemplate<class Impl> 2112727Sktlim@umich.eduvoid 2122292SN/ALSQUnit<Impl>::clearLQ() 2132292SN/A{ 2142292SN/A loadQueue.clear(); 2152292SN/A} 2162292SN/A 2172292SN/Atemplate<class Impl> 2182292SN/Avoid 2192292SN/ALSQUnit<Impl>::clearSQ() 2202292SN/A{ 2212292SN/A storeQueue.clear(); 2222292SN/A} 2232292SN/A 2242292SN/Atemplate<class Impl> 2252292SN/Avoid 2262307SN/ALSQUnit<Impl>::switchOut() 2272307SN/A{ 2282307SN/A switchedOut = true; 2292367SN/A for (int i = 0; i < loadQueue.size(); ++i) { 2302367SN/A assert(!loadQueue[i]); 2312307SN/A loadQueue[i] = NULL; 2322367SN/A } 2332307SN/A 2342329SN/A assert(storesToWB == 0); 2352307SN/A} 2362307SN/A 2372307SN/Atemplate<class Impl> 2382307SN/Avoid 2392307SN/ALSQUnit<Impl>::takeOverFrom() 2402307SN/A{ 2412307SN/A switchedOut = false; 2422307SN/A loads = stores = storesToWB = 0; 2432307SN/A 2442307SN/A loadHead = loadTail = 0; 2452307SN/A 2462307SN/A storeHead = storeWBIdx = storeTail = 0; 2472307SN/A 2482307SN/A usedPorts = 0; 2492307SN/A 2502329SN/A memDepViolator = NULL; 2512307SN/A 2522307SN/A blockedLoadSeqNum = 0; 2532307SN/A 2542307SN/A stalled = false; 2552307SN/A isLoadBlocked = false; 2562307SN/A loadBlockedHandled = false; 2572307SN/A} 2582307SN/A 2592307SN/Atemplate<class Impl> 2602307SN/Avoid 2612292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 2622292SN/A{ 2632329SN/A unsigned size_plus_sentinel = size + 1; 2642329SN/A assert(size_plus_sentinel >= LQEntries); 2652292SN/A 2662329SN/A if (size_plus_sentinel > LQEntries) { 2672329SN/A while (size_plus_sentinel > loadQueue.size()) { 2682292SN/A DynInstPtr dummy; 2692292SN/A loadQueue.push_back(dummy); 2702292SN/A LQEntries++; 2712292SN/A } 2722292SN/A } else { 2732329SN/A LQEntries = size_plus_sentinel; 2742292SN/A } 2752292SN/A 2762292SN/A} 2772292SN/A 2782292SN/Atemplate<class Impl> 2792292SN/Avoid 2802292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 2812292SN/A{ 2822329SN/A unsigned size_plus_sentinel = size + 1; 2832329SN/A if (size_plus_sentinel > SQEntries) { 2842329SN/A while (size_plus_sentinel > storeQueue.size()) { 2852292SN/A SQEntry dummy; 2862292SN/A storeQueue.push_back(dummy); 2872292SN/A SQEntries++; 2882292SN/A } 2892292SN/A } else { 2902329SN/A SQEntries = size_plus_sentinel; 2912292SN/A } 2922292SN/A} 2932292SN/A 2942292SN/Atemplate <class Impl> 2952292SN/Avoid 2962292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 2972292SN/A{ 2982292SN/A assert(inst->isMemRef()); 2992292SN/A 3002292SN/A assert(inst->isLoad() || inst->isStore()); 3012292SN/A 3022292SN/A if (inst->isLoad()) { 3032292SN/A insertLoad(inst); 3042292SN/A } else { 3052292SN/A insertStore(inst); 3062292SN/A } 3072292SN/A 3082292SN/A inst->setInLSQ(); 3092292SN/A} 3102292SN/A 3112292SN/Atemplate <class Impl> 3122292SN/Avoid 3132292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3142292SN/A{ 3152329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3162329SN/A assert(loads < LQEntries); 3172292SN/A 3182292SN/A DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n", 3192292SN/A load_inst->readPC(), loadTail, load_inst->seqNum); 3202292SN/A 3212292SN/A load_inst->lqIdx = loadTail; 3222292SN/A 3232292SN/A if (stores == 0) { 3242292SN/A load_inst->sqIdx = -1; 3252292SN/A } else { 3262292SN/A load_inst->sqIdx = storeTail; 3272292SN/A } 3282292SN/A 3292292SN/A loadQueue[loadTail] = load_inst; 3302292SN/A 3312292SN/A incrLdIdx(loadTail); 3322292SN/A 3332292SN/A ++loads; 3342292SN/A} 3352292SN/A 3362292SN/Atemplate <class Impl> 3372292SN/Avoid 3382292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3392292SN/A{ 3402292SN/A // Make sure it is not full before inserting an instruction. 3412292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3422292SN/A assert(stores < SQEntries); 3432292SN/A 3442292SN/A DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n", 3452292SN/A store_inst->readPC(), storeTail, store_inst->seqNum); 3462292SN/A 3472292SN/A store_inst->sqIdx = storeTail; 3482292SN/A store_inst->lqIdx = loadTail; 3492292SN/A 3502292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3512292SN/A 3522292SN/A incrStIdx(storeTail); 3532292SN/A 3542292SN/A ++stores; 3552292SN/A} 3562292SN/A 3572292SN/Atemplate <class Impl> 3582292SN/Atypename Impl::DynInstPtr 3592292SN/ALSQUnit<Impl>::getMemDepViolator() 3602292SN/A{ 3612292SN/A DynInstPtr temp = memDepViolator; 3622292SN/A 3632292SN/A memDepViolator = NULL; 3642292SN/A 3652292SN/A return temp; 3662292SN/A} 3672292SN/A 3682292SN/Atemplate <class Impl> 3692292SN/Aunsigned 3702292SN/ALSQUnit<Impl>::numFreeEntries() 3712292SN/A{ 3722292SN/A unsigned free_lq_entries = LQEntries - loads; 3732292SN/A unsigned free_sq_entries = SQEntries - stores; 3742292SN/A 3752292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 3762292SN/A // empty/full conditions. Subtract 1 from the free entries. 3772292SN/A if (free_lq_entries < free_sq_entries) { 3782292SN/A return free_lq_entries - 1; 3792292SN/A } else { 3802292SN/A return free_sq_entries - 1; 3812292SN/A } 3822292SN/A} 3832292SN/A 3842292SN/Atemplate <class Impl> 3852292SN/Aint 3862292SN/ALSQUnit<Impl>::numLoadsReady() 3872292SN/A{ 3882292SN/A int load_idx = loadHead; 3892292SN/A int retval = 0; 3902292SN/A 3912292SN/A while (load_idx != loadTail) { 3922292SN/A assert(loadQueue[load_idx]); 3932292SN/A 3942292SN/A if (loadQueue[load_idx]->readyToIssue()) { 3952292SN/A ++retval; 3962292SN/A } 3972292SN/A } 3982292SN/A 3992292SN/A return retval; 4002292SN/A} 4012292SN/A 4022292SN/Atemplate <class Impl> 4032292SN/AFault 4042292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 4052292SN/A{ 4062292SN/A // Execute a specific load. 4072292SN/A Fault load_fault = NoFault; 4082292SN/A 4092292SN/A DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n", 4102292SN/A inst->readPC(),inst->seqNum); 4112292SN/A 4122669Sktlim@umich.edu load_fault = inst->initiateAcc(); 4132292SN/A 4142292SN/A // If the instruction faulted, then we need to send it along to commit 4152292SN/A // without the instruction completing. 4162292SN/A if (load_fault != NoFault) { 4172329SN/A // Send this instruction to commit, also make sure iew stage 4182329SN/A // realizes there is activity. 4192367SN/A // Mark it as executed unless it is an uncached load that 4202367SN/A // needs to hit the head of commit. 4213731Sktlim@umich.edu if (!(inst->req && inst->req->isUncacheable()) || 4223731Sktlim@umich.edu inst->isAtCommit()) { 4232367SN/A inst->setExecuted(); 4242367SN/A } 4252292SN/A iewStage->instToCommit(inst); 4262292SN/A iewStage->activityThisCycle(); 4272292SN/A } 4282292SN/A 4292292SN/A return load_fault; 4302292SN/A} 4312292SN/A 4322292SN/Atemplate <class Impl> 4332292SN/AFault 4342292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 4352292SN/A{ 4362292SN/A using namespace TheISA; 4372292SN/A // Make sure that a store exists. 4382292SN/A assert(stores != 0); 4392292SN/A 4402292SN/A int store_idx = store_inst->sqIdx; 4412292SN/A 4422292SN/A DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n", 4432292SN/A store_inst->readPC(), store_inst->seqNum); 4442292SN/A 4452292SN/A // Check the recently completed loads to see if any match this store's 4462292SN/A // address. If so, then we have a memory ordering violation. 4472292SN/A int load_idx = store_inst->lqIdx; 4482292SN/A 4492292SN/A Fault store_fault = store_inst->initiateAcc(); 4502292SN/A 4512329SN/A if (storeQueue[store_idx].size == 0) { 4522292SN/A DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n", 4532292SN/A store_inst->readPC(),store_inst->seqNum); 4542292SN/A 4552292SN/A return store_fault; 4562292SN/A } 4572292SN/A 4582292SN/A assert(store_fault == NoFault); 4592292SN/A 4602336SN/A if (store_inst->isStoreConditional()) { 4612336SN/A // Store conditionals need to set themselves as able to 4622336SN/A // writeback if we haven't had a fault by here. 4632329SN/A storeQueue[store_idx].canWB = true; 4642292SN/A 4652329SN/A ++storesToWB; 4662292SN/A } 4672292SN/A 4682292SN/A if (!memDepViolator) { 4692292SN/A while (load_idx != loadTail) { 4702329SN/A // Really only need to check loads that have actually executed 4712329SN/A // It's safe to check all loads because effAddr is set to 4722329SN/A // InvalAddr when the dyn inst is created. 4732292SN/A 4742329SN/A // @todo: For now this is extra conservative, detecting a 4752329SN/A // violation if the addresses match assuming all accesses 4762329SN/A // are quad word accesses. 4772329SN/A 4782292SN/A // @todo: Fix this, magic number being used here 4792292SN/A if ((loadQueue[load_idx]->effAddr >> 8) == 4802292SN/A (store_inst->effAddr >> 8)) { 4812292SN/A // A load incorrectly passed this store. Squash and refetch. 4822292SN/A // For now return a fault to show that it was unsuccessful. 4832292SN/A memDepViolator = loadQueue[load_idx]; 4842361SN/A ++lsqMemOrderViolation; 4852292SN/A 4862292SN/A return genMachineCheckFault(); 4872292SN/A } 4882292SN/A 4892292SN/A incrLdIdx(load_idx); 4902292SN/A } 4912292SN/A 4922292SN/A // If we've reached this point, there was no violation. 4932292SN/A memDepViolator = NULL; 4942292SN/A } 4952292SN/A 4962292SN/A return store_fault; 4972292SN/A} 4982292SN/A 4992292SN/Atemplate <class Impl> 5002292SN/Avoid 5012292SN/ALSQUnit<Impl>::commitLoad() 5022292SN/A{ 5032292SN/A assert(loadQueue[loadHead]); 5042292SN/A 5052292SN/A DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n", 5062292SN/A loadQueue[loadHead]->readPC()); 5072292SN/A 5082292SN/A loadQueue[loadHead] = NULL; 5092292SN/A 5102292SN/A incrLdIdx(loadHead); 5112292SN/A 5122292SN/A --loads; 5132292SN/A} 5142292SN/A 5152292SN/Atemplate <class Impl> 5162292SN/Avoid 5172292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 5182292SN/A{ 5192292SN/A assert(loads == 0 || loadQueue[loadHead]); 5202292SN/A 5212292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 5222292SN/A commitLoad(); 5232292SN/A } 5242292SN/A} 5252292SN/A 5262292SN/Atemplate <class Impl> 5272292SN/Avoid 5282292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 5292292SN/A{ 5302292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 5312292SN/A 5322292SN/A int store_idx = storeHead; 5332292SN/A 5342292SN/A while (store_idx != storeTail) { 5352292SN/A assert(storeQueue[store_idx].inst); 5362329SN/A // Mark any stores that are now committed and have not yet 5372329SN/A // been marked as able to write back. 5382292SN/A if (!storeQueue[store_idx].canWB) { 5392292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 5402292SN/A break; 5412292SN/A } 5422292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 5432292SN/A "%#x [sn:%lli]\n", 5442292SN/A storeQueue[store_idx].inst->readPC(), 5452292SN/A storeQueue[store_idx].inst->seqNum); 5462292SN/A 5472292SN/A storeQueue[store_idx].canWB = true; 5482292SN/A 5492292SN/A ++storesToWB; 5502292SN/A } 5512292SN/A 5522292SN/A incrStIdx(store_idx); 5532292SN/A } 5542292SN/A} 5552292SN/A 5562292SN/Atemplate <class Impl> 5572292SN/Avoid 5582292SN/ALSQUnit<Impl>::writebackStores() 5592292SN/A{ 5602292SN/A while (storesToWB > 0 && 5612292SN/A storeWBIdx != storeTail && 5622292SN/A storeQueue[storeWBIdx].inst && 5632292SN/A storeQueue[storeWBIdx].canWB && 5642292SN/A usedPorts < cachePorts) { 5652292SN/A 5662907Sktlim@umich.edu if (isStoreBlocked || lsq->cacheBlocked()) { 5672678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 5682678Sktlim@umich.edu " is blocked!\n"); 5692678Sktlim@umich.edu break; 5702678Sktlim@umich.edu } 5712678Sktlim@umich.edu 5722329SN/A // Store didn't write any data so no need to write it back to 5732329SN/A // memory. 5742292SN/A if (storeQueue[storeWBIdx].size == 0) { 5752292SN/A completeStore(storeWBIdx); 5762292SN/A 5772292SN/A incrStIdx(storeWBIdx); 5782292SN/A 5792292SN/A continue; 5802292SN/A } 5812678Sktlim@umich.edu 5822292SN/A ++usedPorts; 5832292SN/A 5842292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 5852292SN/A incrStIdx(storeWBIdx); 5862292SN/A 5872292SN/A continue; 5882292SN/A } 5892292SN/A 5902292SN/A assert(storeQueue[storeWBIdx].req); 5912292SN/A assert(!storeQueue[storeWBIdx].committed); 5922292SN/A 5932669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 5942669Sktlim@umich.edu 5952669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 5962292SN/A storeQueue[storeWBIdx].committed = true; 5972292SN/A 5982669Sktlim@umich.edu assert(!inst->memData); 5992669Sktlim@umich.edu inst->memData = new uint8_t[64]; 6002678Sktlim@umich.edu memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data, 6012678Sktlim@umich.edu req->getSize()); 6022669Sktlim@umich.edu 6032669Sktlim@umich.edu PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 6042669Sktlim@umich.edu data_pkt->dataStatic(inst->memData); 6052292SN/A 6062678Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 6072678Sktlim@umich.edu state->isLoad = false; 6082678Sktlim@umich.edu state->idx = storeWBIdx; 6092678Sktlim@umich.edu state->inst = inst; 6102678Sktlim@umich.edu data_pkt->senderState = state; 6112678Sktlim@umich.edu 6122292SN/A DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " 6132292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 6143221Sktlim@umich.edu storeWBIdx, inst->readPC(), 6152669Sktlim@umich.edu req->getPaddr(), *(inst->memData), 6163221Sktlim@umich.edu inst->seqNum); 6172292SN/A 6182693Sktlim@umich.edu // @todo: Remove this SC hack once the memory system handles it. 6193172Sstever@eecs.umich.edu if (req->isLocked()) { 6203326Sktlim@umich.edu // Disable recording the result temporarily. Writing to 6213326Sktlim@umich.edu // misc regs normally updates the result, but this is not 6223326Sktlim@umich.edu // the desired behavior when handling store conditionals. 6233326Sktlim@umich.edu inst->recordResult = false; 6243326Sktlim@umich.edu bool success = TheISA::handleLockedWrite(inst.get(), req); 6253326Sktlim@umich.edu inst->recordResult = true; 6263326Sktlim@umich.edu 6273326Sktlim@umich.edu if (!success) { 6283326Sktlim@umich.edu // Instantly complete this store. 6293326Sktlim@umich.edu DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 6303326Sktlim@umich.edu "Instantly completing it.\n", 6313326Sktlim@umich.edu inst->seqNum); 6323326Sktlim@umich.edu WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 6333326Sktlim@umich.edu wb->schedule(curTick + 1); 6343326Sktlim@umich.edu delete state; 6353326Sktlim@umich.edu completeStore(storeWBIdx); 6363326Sktlim@umich.edu incrStIdx(storeWBIdx); 6373326Sktlim@umich.edu continue; 6382693Sktlim@umich.edu } 6392693Sktlim@umich.edu } else { 6402693Sktlim@umich.edu // Non-store conditionals do not need a writeback. 6412693Sktlim@umich.edu state->noWB = true; 6422693Sktlim@umich.edu } 6432693Sktlim@umich.edu 6442669Sktlim@umich.edu if (!dcachePort->sendTiming(data_pkt)) { 6453221Sktlim@umich.edu if (data_pkt->result == Packet::BadAddress) { 6463221Sktlim@umich.edu panic("LSQ sent out a bad address for a completed store!"); 6473221Sktlim@umich.edu } 6482669Sktlim@umich.edu // Need to handle becoming blocked on a store. 6493221Sktlim@umich.edu DPRINTF(IEW, "D-Cache became blcoked when writing [sn:%lli], will" 6503221Sktlim@umich.edu "retry later\n", 6513221Sktlim@umich.edu inst->seqNum); 6522678Sktlim@umich.edu isStoreBlocked = true; 6532727Sktlim@umich.edu ++lsqCacheBlocked; 6542698Sktlim@umich.edu assert(retryPkt == NULL); 6552698Sktlim@umich.edu retryPkt = data_pkt; 6563014Srdreslin@umich.edu lsq->setRetryTid(lsqID); 6572669Sktlim@umich.edu } else { 6582693Sktlim@umich.edu storePostSend(data_pkt); 6592292SN/A } 6602292SN/A } 6612292SN/A 6622292SN/A // Not sure this should set it to 0. 6632292SN/A usedPorts = 0; 6642292SN/A 6652292SN/A assert(stores >= 0 && storesToWB >= 0); 6662292SN/A} 6672292SN/A 6682292SN/A/*template <class Impl> 6692292SN/Avoid 6702292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 6712292SN/A{ 6722292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 6732292SN/A mshrSeqNums.end(), 6742292SN/A seqNum); 6752292SN/A 6762292SN/A if (mshr_it != mshrSeqNums.end()) { 6772292SN/A mshrSeqNums.erase(mshr_it); 6782292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 6792292SN/A } 6802292SN/A}*/ 6812292SN/A 6822292SN/Atemplate <class Impl> 6832292SN/Avoid 6842292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 6852292SN/A{ 6862292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 6872329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 6882292SN/A 6892292SN/A int load_idx = loadTail; 6902292SN/A decrLdIdx(load_idx); 6912292SN/A 6922292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 6932292SN/A DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, " 6942292SN/A "[sn:%lli]\n", 6952292SN/A loadQueue[load_idx]->readPC(), 6962292SN/A loadQueue[load_idx]->seqNum); 6972292SN/A 6982292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 6992292SN/A stalled = false; 7002292SN/A stallingStoreIsn = 0; 7012292SN/A stallingLoadIdx = 0; 7022292SN/A } 7032292SN/A 7042329SN/A // Clear the smart pointer to make sure it is decremented. 7052731Sktlim@umich.edu loadQueue[load_idx]->setSquashed(); 7062292SN/A loadQueue[load_idx] = NULL; 7072292SN/A --loads; 7082292SN/A 7092292SN/A // Inefficient! 7102292SN/A loadTail = load_idx; 7112292SN/A 7122292SN/A decrLdIdx(load_idx); 7132727Sktlim@umich.edu ++lsqSquashedLoads; 7142292SN/A } 7152292SN/A 7162292SN/A if (isLoadBlocked) { 7172292SN/A if (squashed_num < blockedLoadSeqNum) { 7182292SN/A isLoadBlocked = false; 7192292SN/A loadBlockedHandled = false; 7202292SN/A blockedLoadSeqNum = 0; 7212292SN/A } 7222292SN/A } 7232292SN/A 7242292SN/A int store_idx = storeTail; 7252292SN/A decrStIdx(store_idx); 7262292SN/A 7272292SN/A while (stores != 0 && 7282292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 7292329SN/A // Instructions marked as can WB are already committed. 7302292SN/A if (storeQueue[store_idx].canWB) { 7312292SN/A break; 7322292SN/A } 7332292SN/A 7342292SN/A DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, " 7352292SN/A "idx:%i [sn:%lli]\n", 7362292SN/A storeQueue[store_idx].inst->readPC(), 7372292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 7382292SN/A 7392329SN/A // I don't think this can happen. It should have been cleared 7402329SN/A // by the stalling load. 7412292SN/A if (isStalled() && 7422292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 7432292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 7442292SN/A stalled = false; 7452292SN/A stallingStoreIsn = 0; 7462292SN/A } 7472292SN/A 7482329SN/A // Clear the smart pointer to make sure it is decremented. 7492731Sktlim@umich.edu storeQueue[store_idx].inst->setSquashed(); 7502292SN/A storeQueue[store_idx].inst = NULL; 7512292SN/A storeQueue[store_idx].canWB = 0; 7522292SN/A 7532292SN/A storeQueue[store_idx].req = NULL; 7542292SN/A --stores; 7552292SN/A 7562292SN/A // Inefficient! 7572292SN/A storeTail = store_idx; 7582292SN/A 7592292SN/A decrStIdx(store_idx); 7602727Sktlim@umich.edu ++lsqSquashedStores; 7612292SN/A } 7622292SN/A} 7632292SN/A 7642292SN/Atemplate <class Impl> 7652292SN/Avoid 7663349Sbinkertn@umich.eduLSQUnit<Impl>::storePostSend(PacketPtr pkt) 7672693Sktlim@umich.edu{ 7682693Sktlim@umich.edu if (isStalled() && 7692693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 7702693Sktlim@umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 7712693Sktlim@umich.edu "load idx:%i\n", 7722693Sktlim@umich.edu stallingStoreIsn, stallingLoadIdx); 7732693Sktlim@umich.edu stalled = false; 7742693Sktlim@umich.edu stallingStoreIsn = 0; 7752693Sktlim@umich.edu iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 7762693Sktlim@umich.edu } 7772693Sktlim@umich.edu 7782693Sktlim@umich.edu if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 7792693Sktlim@umich.edu // The store is basically completed at this time. This 7802693Sktlim@umich.edu // only works so long as the checker doesn't try to 7812693Sktlim@umich.edu // verify the value in memory for stores. 7822693Sktlim@umich.edu storeQueue[storeWBIdx].inst->setCompleted(); 7832733Sktlim@umich.edu#if USE_CHECKER 7842693Sktlim@umich.edu if (cpu->checker) { 7852732Sktlim@umich.edu cpu->checker->verify(storeQueue[storeWBIdx].inst); 7862693Sktlim@umich.edu } 7872733Sktlim@umich.edu#endif 7882693Sktlim@umich.edu } 7892693Sktlim@umich.edu 7902693Sktlim@umich.edu if (pkt->result != Packet::Success) { 7912693Sktlim@umich.edu DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n", 7922693Sktlim@umich.edu storeWBIdx); 7932693Sktlim@umich.edu 7942693Sktlim@umich.edu DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n", 7952693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum); 7962693Sktlim@umich.edu 7972693Sktlim@umich.edu //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum); 7982693Sktlim@umich.edu 7992693Sktlim@umich.edu //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size()); 8002693Sktlim@umich.edu 8012693Sktlim@umich.edu // @todo: Increment stat here. 8022693Sktlim@umich.edu } else { 8032693Sktlim@umich.edu DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n", 8042693Sktlim@umich.edu storeWBIdx); 8052693Sktlim@umich.edu 8062693Sktlim@umich.edu DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", 8072693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum); 8082693Sktlim@umich.edu } 8092693Sktlim@umich.edu 8102693Sktlim@umich.edu incrStIdx(storeWBIdx); 8112693Sktlim@umich.edu} 8122693Sktlim@umich.edu 8132693Sktlim@umich.edutemplate <class Impl> 8142693Sktlim@umich.eduvoid 8152678Sktlim@umich.eduLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 8162678Sktlim@umich.edu{ 8172678Sktlim@umich.edu iewStage->wakeCPU(); 8182678Sktlim@umich.edu 8192678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 8202678Sktlim@umich.edu if (inst->isSquashed()) { 8212927Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 8222678Sktlim@umich.edu assert(!inst->isStore()); 8232727Sktlim@umich.edu ++lsqIgnoredResponses; 8242678Sktlim@umich.edu return; 8252678Sktlim@umich.edu } 8262678Sktlim@umich.edu 8272678Sktlim@umich.edu if (!inst->isExecuted()) { 8282678Sktlim@umich.edu inst->setExecuted(); 8292678Sktlim@umich.edu 8302678Sktlim@umich.edu // Complete access to copy data to proper place. 8312678Sktlim@umich.edu inst->completeAcc(pkt); 8322678Sktlim@umich.edu } 8332678Sktlim@umich.edu 8342678Sktlim@umich.edu // Need to insert instruction into queue to commit 8352678Sktlim@umich.edu iewStage->instToCommit(inst); 8362678Sktlim@umich.edu 8372678Sktlim@umich.edu iewStage->activityThisCycle(); 8382678Sktlim@umich.edu} 8392678Sktlim@umich.edu 8402678Sktlim@umich.edutemplate <class Impl> 8412678Sktlim@umich.eduvoid 8422292SN/ALSQUnit<Impl>::completeStore(int store_idx) 8432292SN/A{ 8442292SN/A assert(storeQueue[store_idx].inst); 8452292SN/A storeQueue[store_idx].completed = true; 8462292SN/A --storesToWB; 8472292SN/A // A bit conservative because a store completion may not free up entries, 8482292SN/A // but hopefully avoids two store completions in one cycle from making 8492292SN/A // the CPU tick twice. 8503126Sktlim@umich.edu cpu->wakeCPU(); 8512292SN/A cpu->activityThisCycle(); 8522292SN/A 8532292SN/A if (store_idx == storeHead) { 8542292SN/A do { 8552292SN/A incrStIdx(storeHead); 8562292SN/A 8572292SN/A --stores; 8582292SN/A } while (storeQueue[storeHead].completed && 8592292SN/A storeHead != storeTail); 8602292SN/A 8612292SN/A iewStage->updateLSQNextCycle = true; 8622292SN/A } 8632292SN/A 8642329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 8652329SN/A "idx:%i\n", 8662329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 8672292SN/A 8682292SN/A if (isStalled() && 8692292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 8702292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 8712292SN/A "load idx:%i\n", 8722292SN/A stallingStoreIsn, stallingLoadIdx); 8732292SN/A stalled = false; 8742292SN/A stallingStoreIsn = 0; 8752292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 8762292SN/A } 8772316SN/A 8782316SN/A storeQueue[store_idx].inst->setCompleted(); 8792329SN/A 8802329SN/A // Tell the checker we've completed this instruction. Some stores 8812329SN/A // may get reported twice to the checker, but the checker can 8822329SN/A // handle that case. 8832733Sktlim@umich.edu#if USE_CHECKER 8842316SN/A if (cpu->checker) { 8852732Sktlim@umich.edu cpu->checker->verify(storeQueue[store_idx].inst); 8862316SN/A } 8872733Sktlim@umich.edu#endif 8882292SN/A} 8892292SN/A 8902292SN/Atemplate <class Impl> 8912693Sktlim@umich.eduvoid 8922693Sktlim@umich.eduLSQUnit<Impl>::recvRetry() 8932693Sktlim@umich.edu{ 8942698Sktlim@umich.edu if (isStoreBlocked) { 8952698Sktlim@umich.edu assert(retryPkt != NULL); 8962693Sktlim@umich.edu 8972698Sktlim@umich.edu if (dcachePort->sendTiming(retryPkt)) { 8983221Sktlim@umich.edu if (retryPkt->result == Packet::BadAddress) { 8993221Sktlim@umich.edu panic("LSQ sent out a bad address for a completed store!"); 9003221Sktlim@umich.edu } 9012698Sktlim@umich.edu storePostSend(retryPkt); 9022699Sktlim@umich.edu retryPkt = NULL; 9032693Sktlim@umich.edu isStoreBlocked = false; 9043014Srdreslin@umich.edu lsq->setRetryTid(-1); 9052693Sktlim@umich.edu } else { 9062693Sktlim@umich.edu // Still blocked! 9072727Sktlim@umich.edu ++lsqCacheBlocked; 9082907Sktlim@umich.edu lsq->setRetryTid(lsqID); 9092693Sktlim@umich.edu } 9102693Sktlim@umich.edu } else if (isLoadBlocked) { 9112693Sktlim@umich.edu DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 9122693Sktlim@umich.edu "no need to resend packet.\n"); 9132693Sktlim@umich.edu } else { 9142693Sktlim@umich.edu DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 9152693Sktlim@umich.edu } 9162693Sktlim@umich.edu} 9172693Sktlim@umich.edu 9182693Sktlim@umich.edutemplate <class Impl> 9192292SN/Ainline void 9202292SN/ALSQUnit<Impl>::incrStIdx(int &store_idx) 9212292SN/A{ 9222292SN/A if (++store_idx >= SQEntries) 9232292SN/A store_idx = 0; 9242292SN/A} 9252292SN/A 9262292SN/Atemplate <class Impl> 9272292SN/Ainline void 9282292SN/ALSQUnit<Impl>::decrStIdx(int &store_idx) 9292292SN/A{ 9302292SN/A if (--store_idx < 0) 9312292SN/A store_idx += SQEntries; 9322292SN/A} 9332292SN/A 9342292SN/Atemplate <class Impl> 9352292SN/Ainline void 9362292SN/ALSQUnit<Impl>::incrLdIdx(int &load_idx) 9372292SN/A{ 9382292SN/A if (++load_idx >= LQEntries) 9392292SN/A load_idx = 0; 9402292SN/A} 9412292SN/A 9422292SN/Atemplate <class Impl> 9432292SN/Ainline void 9442292SN/ALSQUnit<Impl>::decrLdIdx(int &load_idx) 9452292SN/A{ 9462292SN/A if (--load_idx < 0) 9472292SN/A load_idx += LQEntries; 9482292SN/A} 9492329SN/A 9502329SN/Atemplate <class Impl> 9512329SN/Avoid 9522329SN/ALSQUnit<Impl>::dumpInsts() 9532329SN/A{ 9542329SN/A cprintf("Load store queue: Dumping instructions.\n"); 9552329SN/A cprintf("Load queue size: %i\n", loads); 9562329SN/A cprintf("Load queue: "); 9572329SN/A 9582329SN/A int load_idx = loadHead; 9592329SN/A 9602329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 9612329SN/A cprintf("%#x ", loadQueue[load_idx]->readPC()); 9622329SN/A 9632329SN/A incrLdIdx(load_idx); 9642329SN/A } 9652329SN/A 9662329SN/A cprintf("Store queue size: %i\n", stores); 9672329SN/A cprintf("Store queue: "); 9682329SN/A 9692329SN/A int store_idx = storeHead; 9702329SN/A 9712329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 9722329SN/A cprintf("%#x ", storeQueue[store_idx].inst->readPC()); 9732329SN/A 9742329SN/A incrStIdx(store_idx); 9752329SN/A } 9762329SN/A 9772329SN/A cprintf("\n"); 9782329SN/A} 979