lsq_unit_impl.hh revision 2907
12292SN/A/* 22292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32292SN/A * All rights reserved. 42292SN/A * 52292SN/A * Redistribution and use in source and binary forms, with or without 62292SN/A * modification, are permitted provided that the following conditions are 72292SN/A * met: redistributions of source code must retain the above copyright 82292SN/A * notice, this list of conditions and the following disclaimer; 92292SN/A * redistributions in binary form must reproduce the above copyright 102292SN/A * notice, this list of conditions and the following disclaimer in the 112292SN/A * documentation and/or other materials provided with the distribution; 122292SN/A * neither the name of the copyright holders nor the names of its 132292SN/A * contributors may be used to endorse or promote products derived from 142292SN/A * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292689Sktlim@umich.edu * Korey Sewell 302292SN/A */ 312292SN/A 322733Sktlim@umich.edu#include "config/use_checker.hh" 332733Sktlim@umich.edu 342907Sktlim@umich.edu#include "cpu/o3/lsq.hh" 352292SN/A#include "cpu/o3/lsq_unit.hh" 362292SN/A#include "base/str.hh" 372722Sktlim@umich.edu#include "mem/packet.hh" 382669Sktlim@umich.edu#include "mem/request.hh" 392292SN/A 402790Sktlim@umich.edu#if USE_CHECKER 412790Sktlim@umich.edu#include "cpu/checker/cpu.hh" 422790Sktlim@umich.edu#endif 432790Sktlim@umich.edu 442669Sktlim@umich.edutemplate<class Impl> 452678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 462678Sktlim@umich.edu LSQUnit *lsq_ptr) 472678Sktlim@umich.edu : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 482292SN/A{ 492678Sktlim@umich.edu this->setFlags(Event::AutoDelete); 502292SN/A} 512292SN/A 522669Sktlim@umich.edutemplate<class Impl> 532292SN/Avoid 542678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 552292SN/A{ 562678Sktlim@umich.edu if (!lsqPtr->isSwitchedOut()) { 572678Sktlim@umich.edu lsqPtr->writeback(inst, pkt); 582678Sktlim@umich.edu } 592678Sktlim@umich.edu delete pkt; 602678Sktlim@umich.edu} 612292SN/A 622678Sktlim@umich.edutemplate<class Impl> 632678Sktlim@umich.educonst char * 642678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::description() 652678Sktlim@umich.edu{ 662678Sktlim@umich.edu return "Store writeback event"; 672678Sktlim@umich.edu} 682292SN/A 692678Sktlim@umich.edutemplate<class Impl> 702678Sktlim@umich.eduvoid 712678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 722678Sktlim@umich.edu{ 732678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 742678Sktlim@umich.edu DynInstPtr inst = state->inst; 752678Sktlim@umich.edu DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum); 762698Sktlim@umich.edu DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum); 772344SN/A 782678Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 792678Sktlim@umich.edu 802678Sktlim@umich.edu if (isSwitchedOut() || inst->isSquashed()) { 812820Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 822678Sktlim@umich.edu delete state; 832678Sktlim@umich.edu delete pkt; 842307SN/A return; 852678Sktlim@umich.edu } else { 862678Sktlim@umich.edu if (!state->noWB) { 872678Sktlim@umich.edu writeback(inst, pkt); 882678Sktlim@umich.edu } 892678Sktlim@umich.edu 902678Sktlim@umich.edu if (inst->isStore()) { 912678Sktlim@umich.edu completeStore(state->idx); 922678Sktlim@umich.edu } 932344SN/A } 942307SN/A 952678Sktlim@umich.edu delete state; 962678Sktlim@umich.edu delete pkt; 972292SN/A} 982292SN/A 992292SN/Atemplate <class Impl> 1002292SN/ALSQUnit<Impl>::LSQUnit() 1012678Sktlim@umich.edu : loads(0), stores(0), storesToWB(0), stalled(false), 1022678Sktlim@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1032292SN/A loadBlockedHandled(false) 1042292SN/A{ 1052292SN/A} 1062292SN/A 1072292SN/Atemplate<class Impl> 1082292SN/Avoid 1092907Sktlim@umich.eduLSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries, 1102292SN/A unsigned maxSQEntries, unsigned id) 1112292SN/A{ 1122292SN/A DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1132292SN/A 1142307SN/A switchedOut = false; 1152307SN/A 1162907Sktlim@umich.edu lsq = lsq_ptr; 1172907Sktlim@umich.edu 1182292SN/A lsqID = id; 1192292SN/A 1202329SN/A // Add 1 for the sentinel entry (they are circular queues). 1212329SN/A LQEntries = maxLQEntries + 1; 1222329SN/A SQEntries = maxSQEntries + 1; 1232292SN/A 1242292SN/A loadQueue.resize(LQEntries); 1252292SN/A storeQueue.resize(SQEntries); 1262292SN/A 1272292SN/A loadHead = loadTail = 0; 1282292SN/A 1292292SN/A storeHead = storeWBIdx = storeTail = 0; 1302292SN/A 1312292SN/A usedPorts = 0; 1322292SN/A cachePorts = params->cachePorts; 1332292SN/A 1342329SN/A memDepViolator = NULL; 1352292SN/A 1362292SN/A blockedLoadSeqNum = 0; 1372292SN/A} 1382292SN/A 1392292SN/Atemplate<class Impl> 1402669Sktlim@umich.eduvoid 1412733Sktlim@umich.eduLSQUnit<Impl>::setCPU(O3CPU *cpu_ptr) 1422669Sktlim@umich.edu{ 1432669Sktlim@umich.edu cpu = cpu_ptr; 1442678Sktlim@umich.edu 1452733Sktlim@umich.edu#if USE_CHECKER 1462679Sktlim@umich.edu if (cpu->checker) { 1472679Sktlim@umich.edu cpu->checker->setDcachePort(dcachePort); 1482679Sktlim@umich.edu } 1492733Sktlim@umich.edu#endif 1502669Sktlim@umich.edu} 1512669Sktlim@umich.edu 1522669Sktlim@umich.edutemplate<class Impl> 1532292SN/Astd::string 1542292SN/ALSQUnit<Impl>::name() const 1552292SN/A{ 1562292SN/A if (Impl::MaxThreads == 1) { 1572292SN/A return iewStage->name() + ".lsq"; 1582292SN/A } else { 1592292SN/A return iewStage->name() + ".lsq.thread." + to_string(lsqID); 1602292SN/A } 1612292SN/A} 1622292SN/A 1632292SN/Atemplate<class Impl> 1642292SN/Avoid 1652727Sktlim@umich.eduLSQUnit<Impl>::regStats() 1662727Sktlim@umich.edu{ 1672727Sktlim@umich.edu lsqForwLoads 1682727Sktlim@umich.edu .name(name() + ".forwLoads") 1692727Sktlim@umich.edu .desc("Number of loads that had data forwarded from stores"); 1702727Sktlim@umich.edu 1712727Sktlim@umich.edu invAddrLoads 1722727Sktlim@umich.edu .name(name() + ".invAddrLoads") 1732727Sktlim@umich.edu .desc("Number of loads ignored due to an invalid address"); 1742727Sktlim@umich.edu 1752727Sktlim@umich.edu lsqSquashedLoads 1762727Sktlim@umich.edu .name(name() + ".squashedLoads") 1772727Sktlim@umich.edu .desc("Number of loads squashed"); 1782727Sktlim@umich.edu 1792727Sktlim@umich.edu lsqIgnoredResponses 1802727Sktlim@umich.edu .name(name() + ".ignoredResponses") 1812727Sktlim@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 1822727Sktlim@umich.edu 1832727Sktlim@umich.edu lsqSquashedStores 1842727Sktlim@umich.edu .name(name() + ".squashedStores") 1852727Sktlim@umich.edu .desc("Number of stores squashed"); 1862727Sktlim@umich.edu 1872727Sktlim@umich.edu invAddrSwpfs 1882727Sktlim@umich.edu .name(name() + ".invAddrSwpfs") 1892727Sktlim@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 1902727Sktlim@umich.edu 1912727Sktlim@umich.edu lsqBlockedLoads 1922727Sktlim@umich.edu .name(name() + ".blockedLoads") 1932727Sktlim@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 1942727Sktlim@umich.edu 1952727Sktlim@umich.edu lsqRescheduledLoads 1962727Sktlim@umich.edu .name(name() + ".rescheduledLoads") 1972727Sktlim@umich.edu .desc("Number of loads that were rescheduled"); 1982727Sktlim@umich.edu 1992727Sktlim@umich.edu lsqCacheBlocked 2002727Sktlim@umich.edu .name(name() + ".cacheBlocked") 2012727Sktlim@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2022727Sktlim@umich.edu} 2032727Sktlim@umich.edu 2042727Sktlim@umich.edutemplate<class Impl> 2052727Sktlim@umich.eduvoid 2062292SN/ALSQUnit<Impl>::clearLQ() 2072292SN/A{ 2082292SN/A loadQueue.clear(); 2092292SN/A} 2102292SN/A 2112292SN/Atemplate<class Impl> 2122292SN/Avoid 2132292SN/ALSQUnit<Impl>::clearSQ() 2142292SN/A{ 2152292SN/A storeQueue.clear(); 2162292SN/A} 2172292SN/A 2182292SN/Atemplate<class Impl> 2192292SN/Avoid 2202307SN/ALSQUnit<Impl>::switchOut() 2212307SN/A{ 2222307SN/A switchedOut = true; 2232307SN/A for (int i = 0; i < loadQueue.size(); ++i) 2242307SN/A loadQueue[i] = NULL; 2252307SN/A 2262329SN/A assert(storesToWB == 0); 2272307SN/A} 2282307SN/A 2292307SN/Atemplate<class Impl> 2302307SN/Avoid 2312307SN/ALSQUnit<Impl>::takeOverFrom() 2322307SN/A{ 2332307SN/A switchedOut = false; 2342307SN/A loads = stores = storesToWB = 0; 2352307SN/A 2362307SN/A loadHead = loadTail = 0; 2372307SN/A 2382307SN/A storeHead = storeWBIdx = storeTail = 0; 2392307SN/A 2402307SN/A usedPorts = 0; 2412307SN/A 2422329SN/A memDepViolator = NULL; 2432307SN/A 2442307SN/A blockedLoadSeqNum = 0; 2452307SN/A 2462307SN/A stalled = false; 2472307SN/A isLoadBlocked = false; 2482307SN/A loadBlockedHandled = false; 2492307SN/A} 2502307SN/A 2512307SN/Atemplate<class Impl> 2522307SN/Avoid 2532292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 2542292SN/A{ 2552329SN/A unsigned size_plus_sentinel = size + 1; 2562329SN/A assert(size_plus_sentinel >= LQEntries); 2572292SN/A 2582329SN/A if (size_plus_sentinel > LQEntries) { 2592329SN/A while (size_plus_sentinel > loadQueue.size()) { 2602292SN/A DynInstPtr dummy; 2612292SN/A loadQueue.push_back(dummy); 2622292SN/A LQEntries++; 2632292SN/A } 2642292SN/A } else { 2652329SN/A LQEntries = size_plus_sentinel; 2662292SN/A } 2672292SN/A 2682292SN/A} 2692292SN/A 2702292SN/Atemplate<class Impl> 2712292SN/Avoid 2722292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 2732292SN/A{ 2742329SN/A unsigned size_plus_sentinel = size + 1; 2752329SN/A if (size_plus_sentinel > SQEntries) { 2762329SN/A while (size_plus_sentinel > storeQueue.size()) { 2772292SN/A SQEntry dummy; 2782292SN/A storeQueue.push_back(dummy); 2792292SN/A SQEntries++; 2802292SN/A } 2812292SN/A } else { 2822329SN/A SQEntries = size_plus_sentinel; 2832292SN/A } 2842292SN/A} 2852292SN/A 2862292SN/Atemplate <class Impl> 2872292SN/Avoid 2882292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 2892292SN/A{ 2902292SN/A assert(inst->isMemRef()); 2912292SN/A 2922292SN/A assert(inst->isLoad() || inst->isStore()); 2932292SN/A 2942292SN/A if (inst->isLoad()) { 2952292SN/A insertLoad(inst); 2962292SN/A } else { 2972292SN/A insertStore(inst); 2982292SN/A } 2992292SN/A 3002292SN/A inst->setInLSQ(); 3012292SN/A} 3022292SN/A 3032292SN/Atemplate <class Impl> 3042292SN/Avoid 3052292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3062292SN/A{ 3072329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3082329SN/A assert(loads < LQEntries); 3092292SN/A 3102292SN/A DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n", 3112292SN/A load_inst->readPC(), loadTail, load_inst->seqNum); 3122292SN/A 3132292SN/A load_inst->lqIdx = loadTail; 3142292SN/A 3152292SN/A if (stores == 0) { 3162292SN/A load_inst->sqIdx = -1; 3172292SN/A } else { 3182292SN/A load_inst->sqIdx = storeTail; 3192292SN/A } 3202292SN/A 3212292SN/A loadQueue[loadTail] = load_inst; 3222292SN/A 3232292SN/A incrLdIdx(loadTail); 3242292SN/A 3252292SN/A ++loads; 3262292SN/A} 3272292SN/A 3282292SN/Atemplate <class Impl> 3292292SN/Avoid 3302292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3312292SN/A{ 3322292SN/A // Make sure it is not full before inserting an instruction. 3332292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3342292SN/A assert(stores < SQEntries); 3352292SN/A 3362292SN/A DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n", 3372292SN/A store_inst->readPC(), storeTail, store_inst->seqNum); 3382292SN/A 3392292SN/A store_inst->sqIdx = storeTail; 3402292SN/A store_inst->lqIdx = loadTail; 3412292SN/A 3422292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3432292SN/A 3442292SN/A incrStIdx(storeTail); 3452292SN/A 3462292SN/A ++stores; 3472292SN/A} 3482292SN/A 3492292SN/Atemplate <class Impl> 3502292SN/Atypename Impl::DynInstPtr 3512292SN/ALSQUnit<Impl>::getMemDepViolator() 3522292SN/A{ 3532292SN/A DynInstPtr temp = memDepViolator; 3542292SN/A 3552292SN/A memDepViolator = NULL; 3562292SN/A 3572292SN/A return temp; 3582292SN/A} 3592292SN/A 3602292SN/Atemplate <class Impl> 3612292SN/Aunsigned 3622292SN/ALSQUnit<Impl>::numFreeEntries() 3632292SN/A{ 3642292SN/A unsigned free_lq_entries = LQEntries - loads; 3652292SN/A unsigned free_sq_entries = SQEntries - stores; 3662292SN/A 3672292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 3682292SN/A // empty/full conditions. Subtract 1 from the free entries. 3692292SN/A if (free_lq_entries < free_sq_entries) { 3702292SN/A return free_lq_entries - 1; 3712292SN/A } else { 3722292SN/A return free_sq_entries - 1; 3732292SN/A } 3742292SN/A} 3752292SN/A 3762292SN/Atemplate <class Impl> 3772292SN/Aint 3782292SN/ALSQUnit<Impl>::numLoadsReady() 3792292SN/A{ 3802292SN/A int load_idx = loadHead; 3812292SN/A int retval = 0; 3822292SN/A 3832292SN/A while (load_idx != loadTail) { 3842292SN/A assert(loadQueue[load_idx]); 3852292SN/A 3862292SN/A if (loadQueue[load_idx]->readyToIssue()) { 3872292SN/A ++retval; 3882292SN/A } 3892292SN/A } 3902292SN/A 3912292SN/A return retval; 3922292SN/A} 3932292SN/A 3942292SN/Atemplate <class Impl> 3952292SN/AFault 3962292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 3972292SN/A{ 3982292SN/A // Execute a specific load. 3992292SN/A Fault load_fault = NoFault; 4002292SN/A 4012292SN/A DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n", 4022292SN/A inst->readPC(),inst->seqNum); 4032292SN/A 4042669Sktlim@umich.edu load_fault = inst->initiateAcc(); 4052292SN/A 4062292SN/A // If the instruction faulted, then we need to send it along to commit 4072292SN/A // without the instruction completing. 4082292SN/A if (load_fault != NoFault) { 4092329SN/A // Send this instruction to commit, also make sure iew stage 4102329SN/A // realizes there is activity. 4112292SN/A iewStage->instToCommit(inst); 4122292SN/A iewStage->activityThisCycle(); 4132292SN/A } 4142292SN/A 4152292SN/A return load_fault; 4162292SN/A} 4172292SN/A 4182292SN/Atemplate <class Impl> 4192292SN/AFault 4202292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 4212292SN/A{ 4222292SN/A using namespace TheISA; 4232292SN/A // Make sure that a store exists. 4242292SN/A assert(stores != 0); 4252292SN/A 4262292SN/A int store_idx = store_inst->sqIdx; 4272292SN/A 4282292SN/A DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n", 4292292SN/A store_inst->readPC(), store_inst->seqNum); 4302292SN/A 4312292SN/A // Check the recently completed loads to see if any match this store's 4322292SN/A // address. If so, then we have a memory ordering violation. 4332292SN/A int load_idx = store_inst->lqIdx; 4342292SN/A 4352292SN/A Fault store_fault = store_inst->initiateAcc(); 4362292SN/A 4372329SN/A if (storeQueue[store_idx].size == 0) { 4382292SN/A DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n", 4392292SN/A store_inst->readPC(),store_inst->seqNum); 4402292SN/A 4412292SN/A return store_fault; 4422292SN/A } 4432292SN/A 4442292SN/A assert(store_fault == NoFault); 4452292SN/A 4462336SN/A if (store_inst->isStoreConditional()) { 4472336SN/A // Store conditionals need to set themselves as able to 4482336SN/A // writeback if we haven't had a fault by here. 4492329SN/A storeQueue[store_idx].canWB = true; 4502292SN/A 4512329SN/A ++storesToWB; 4522292SN/A } 4532292SN/A 4542292SN/A if (!memDepViolator) { 4552292SN/A while (load_idx != loadTail) { 4562329SN/A // Really only need to check loads that have actually executed 4572329SN/A // It's safe to check all loads because effAddr is set to 4582329SN/A // InvalAddr when the dyn inst is created. 4592292SN/A 4602329SN/A // @todo: For now this is extra conservative, detecting a 4612329SN/A // violation if the addresses match assuming all accesses 4622329SN/A // are quad word accesses. 4632329SN/A 4642292SN/A // @todo: Fix this, magic number being used here 4652292SN/A if ((loadQueue[load_idx]->effAddr >> 8) == 4662292SN/A (store_inst->effAddr >> 8)) { 4672292SN/A // A load incorrectly passed this store. Squash and refetch. 4682292SN/A // For now return a fault to show that it was unsuccessful. 4692292SN/A memDepViolator = loadQueue[load_idx]; 4702292SN/A 4712292SN/A return genMachineCheckFault(); 4722292SN/A } 4732292SN/A 4742292SN/A incrLdIdx(load_idx); 4752292SN/A } 4762292SN/A 4772292SN/A // If we've reached this point, there was no violation. 4782292SN/A memDepViolator = NULL; 4792292SN/A } 4802292SN/A 4812292SN/A return store_fault; 4822292SN/A} 4832292SN/A 4842292SN/Atemplate <class Impl> 4852292SN/Avoid 4862292SN/ALSQUnit<Impl>::commitLoad() 4872292SN/A{ 4882292SN/A assert(loadQueue[loadHead]); 4892292SN/A 4902292SN/A DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n", 4912292SN/A loadQueue[loadHead]->readPC()); 4922292SN/A 4932292SN/A loadQueue[loadHead] = NULL; 4942292SN/A 4952292SN/A incrLdIdx(loadHead); 4962292SN/A 4972292SN/A --loads; 4982292SN/A} 4992292SN/A 5002292SN/Atemplate <class Impl> 5012292SN/Avoid 5022292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 5032292SN/A{ 5042292SN/A assert(loads == 0 || loadQueue[loadHead]); 5052292SN/A 5062292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 5072292SN/A commitLoad(); 5082292SN/A } 5092292SN/A} 5102292SN/A 5112292SN/Atemplate <class Impl> 5122292SN/Avoid 5132292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 5142292SN/A{ 5152292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 5162292SN/A 5172292SN/A int store_idx = storeHead; 5182292SN/A 5192292SN/A while (store_idx != storeTail) { 5202292SN/A assert(storeQueue[store_idx].inst); 5212329SN/A // Mark any stores that are now committed and have not yet 5222329SN/A // been marked as able to write back. 5232292SN/A if (!storeQueue[store_idx].canWB) { 5242292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 5252292SN/A break; 5262292SN/A } 5272292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 5282292SN/A "%#x [sn:%lli]\n", 5292292SN/A storeQueue[store_idx].inst->readPC(), 5302292SN/A storeQueue[store_idx].inst->seqNum); 5312292SN/A 5322292SN/A storeQueue[store_idx].canWB = true; 5332292SN/A 5342292SN/A ++storesToWB; 5352292SN/A } 5362292SN/A 5372292SN/A incrStIdx(store_idx); 5382292SN/A } 5392292SN/A} 5402292SN/A 5412292SN/Atemplate <class Impl> 5422292SN/Avoid 5432292SN/ALSQUnit<Impl>::writebackStores() 5442292SN/A{ 5452292SN/A while (storesToWB > 0 && 5462292SN/A storeWBIdx != storeTail && 5472292SN/A storeQueue[storeWBIdx].inst && 5482292SN/A storeQueue[storeWBIdx].canWB && 5492292SN/A usedPorts < cachePorts) { 5502292SN/A 5512907Sktlim@umich.edu if (isStoreBlocked || lsq->cacheBlocked()) { 5522678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 5532678Sktlim@umich.edu " is blocked!\n"); 5542678Sktlim@umich.edu break; 5552678Sktlim@umich.edu } 5562678Sktlim@umich.edu 5572329SN/A // Store didn't write any data so no need to write it back to 5582329SN/A // memory. 5592292SN/A if (storeQueue[storeWBIdx].size == 0) { 5602292SN/A completeStore(storeWBIdx); 5612292SN/A 5622292SN/A incrStIdx(storeWBIdx); 5632292SN/A 5642292SN/A continue; 5652292SN/A } 5662678Sktlim@umich.edu 5672292SN/A ++usedPorts; 5682292SN/A 5692292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 5702292SN/A incrStIdx(storeWBIdx); 5712292SN/A 5722292SN/A continue; 5732292SN/A } 5742292SN/A 5752292SN/A assert(storeQueue[storeWBIdx].req); 5762292SN/A assert(!storeQueue[storeWBIdx].committed); 5772292SN/A 5782669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 5792669Sktlim@umich.edu 5802669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 5812292SN/A storeQueue[storeWBIdx].committed = true; 5822292SN/A 5832669Sktlim@umich.edu assert(!inst->memData); 5842669Sktlim@umich.edu inst->memData = new uint8_t[64]; 5852678Sktlim@umich.edu memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data, 5862678Sktlim@umich.edu req->getSize()); 5872669Sktlim@umich.edu 5882669Sktlim@umich.edu PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 5892669Sktlim@umich.edu data_pkt->dataStatic(inst->memData); 5902292SN/A 5912678Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 5922678Sktlim@umich.edu state->isLoad = false; 5932678Sktlim@umich.edu state->idx = storeWBIdx; 5942678Sktlim@umich.edu state->inst = inst; 5952678Sktlim@umich.edu data_pkt->senderState = state; 5962678Sktlim@umich.edu 5972292SN/A DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " 5982292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 5992669Sktlim@umich.edu storeWBIdx, storeQueue[storeWBIdx].inst->readPC(), 6002669Sktlim@umich.edu req->getPaddr(), *(inst->memData), 6012292SN/A storeQueue[storeWBIdx].inst->seqNum); 6022292SN/A 6032693Sktlim@umich.edu // @todo: Remove this SC hack once the memory system handles it. 6042693Sktlim@umich.edu if (req->getFlags() & LOCKED) { 6052693Sktlim@umich.edu if (req->getFlags() & UNCACHEABLE) { 6062693Sktlim@umich.edu req->setScResult(2); 6072693Sktlim@umich.edu } else { 6082693Sktlim@umich.edu if (cpu->lockFlag) { 6092693Sktlim@umich.edu req->setScResult(1); 6102693Sktlim@umich.edu } else { 6112693Sktlim@umich.edu req->setScResult(0); 6122693Sktlim@umich.edu // Hack: Instantly complete this store. 6132693Sktlim@umich.edu completeDataAccess(data_pkt); 6142693Sktlim@umich.edu incrStIdx(storeWBIdx); 6152693Sktlim@umich.edu continue; 6162693Sktlim@umich.edu } 6172693Sktlim@umich.edu } 6182693Sktlim@umich.edu } else { 6192693Sktlim@umich.edu // Non-store conditionals do not need a writeback. 6202693Sktlim@umich.edu state->noWB = true; 6212693Sktlim@umich.edu } 6222693Sktlim@umich.edu 6232669Sktlim@umich.edu if (!dcachePort->sendTiming(data_pkt)) { 6242669Sktlim@umich.edu // Need to handle becoming blocked on a store. 6252678Sktlim@umich.edu isStoreBlocked = true; 6262727Sktlim@umich.edu ++lsqCacheBlocked; 6272698Sktlim@umich.edu assert(retryPkt == NULL); 6282698Sktlim@umich.edu retryPkt = data_pkt; 6292669Sktlim@umich.edu } else { 6302693Sktlim@umich.edu storePostSend(data_pkt); 6312292SN/A } 6322292SN/A } 6332292SN/A 6342292SN/A // Not sure this should set it to 0. 6352292SN/A usedPorts = 0; 6362292SN/A 6372292SN/A assert(stores >= 0 && storesToWB >= 0); 6382292SN/A} 6392292SN/A 6402292SN/A/*template <class Impl> 6412292SN/Avoid 6422292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 6432292SN/A{ 6442292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 6452292SN/A mshrSeqNums.end(), 6462292SN/A seqNum); 6472292SN/A 6482292SN/A if (mshr_it != mshrSeqNums.end()) { 6492292SN/A mshrSeqNums.erase(mshr_it); 6502292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 6512292SN/A } 6522292SN/A}*/ 6532292SN/A 6542292SN/Atemplate <class Impl> 6552292SN/Avoid 6562292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 6572292SN/A{ 6582292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 6592329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 6602292SN/A 6612292SN/A int load_idx = loadTail; 6622292SN/A decrLdIdx(load_idx); 6632292SN/A 6642292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 6652292SN/A DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, " 6662292SN/A "[sn:%lli]\n", 6672292SN/A loadQueue[load_idx]->readPC(), 6682292SN/A loadQueue[load_idx]->seqNum); 6692292SN/A 6702292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 6712292SN/A stalled = false; 6722292SN/A stallingStoreIsn = 0; 6732292SN/A stallingLoadIdx = 0; 6742292SN/A } 6752292SN/A 6762329SN/A // Clear the smart pointer to make sure it is decremented. 6772731Sktlim@umich.edu loadQueue[load_idx]->setSquashed(); 6782292SN/A loadQueue[load_idx] = NULL; 6792292SN/A --loads; 6802292SN/A 6812292SN/A // Inefficient! 6822292SN/A loadTail = load_idx; 6832292SN/A 6842292SN/A decrLdIdx(load_idx); 6852727Sktlim@umich.edu ++lsqSquashedLoads; 6862292SN/A } 6872292SN/A 6882292SN/A if (isLoadBlocked) { 6892292SN/A if (squashed_num < blockedLoadSeqNum) { 6902292SN/A isLoadBlocked = false; 6912292SN/A loadBlockedHandled = false; 6922292SN/A blockedLoadSeqNum = 0; 6932292SN/A } 6942292SN/A } 6952292SN/A 6962292SN/A int store_idx = storeTail; 6972292SN/A decrStIdx(store_idx); 6982292SN/A 6992292SN/A while (stores != 0 && 7002292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 7012329SN/A // Instructions marked as can WB are already committed. 7022292SN/A if (storeQueue[store_idx].canWB) { 7032292SN/A break; 7042292SN/A } 7052292SN/A 7062292SN/A DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, " 7072292SN/A "idx:%i [sn:%lli]\n", 7082292SN/A storeQueue[store_idx].inst->readPC(), 7092292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 7102292SN/A 7112329SN/A // I don't think this can happen. It should have been cleared 7122329SN/A // by the stalling load. 7132292SN/A if (isStalled() && 7142292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 7152292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 7162292SN/A stalled = false; 7172292SN/A stallingStoreIsn = 0; 7182292SN/A } 7192292SN/A 7202329SN/A // Clear the smart pointer to make sure it is decremented. 7212731Sktlim@umich.edu storeQueue[store_idx].inst->setSquashed(); 7222292SN/A storeQueue[store_idx].inst = NULL; 7232292SN/A storeQueue[store_idx].canWB = 0; 7242292SN/A 7252292SN/A storeQueue[store_idx].req = NULL; 7262292SN/A --stores; 7272292SN/A 7282292SN/A // Inefficient! 7292292SN/A storeTail = store_idx; 7302292SN/A 7312292SN/A decrStIdx(store_idx); 7322727Sktlim@umich.edu ++lsqSquashedStores; 7332292SN/A } 7342292SN/A} 7352292SN/A 7362292SN/Atemplate <class Impl> 7372292SN/Avoid 7382693Sktlim@umich.eduLSQUnit<Impl>::storePostSend(Packet *pkt) 7392693Sktlim@umich.edu{ 7402693Sktlim@umich.edu if (isStalled() && 7412693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 7422693Sktlim@umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 7432693Sktlim@umich.edu "load idx:%i\n", 7442693Sktlim@umich.edu stallingStoreIsn, stallingLoadIdx); 7452693Sktlim@umich.edu stalled = false; 7462693Sktlim@umich.edu stallingStoreIsn = 0; 7472693Sktlim@umich.edu iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 7482693Sktlim@umich.edu } 7492693Sktlim@umich.edu 7502693Sktlim@umich.edu if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 7512693Sktlim@umich.edu // The store is basically completed at this time. This 7522693Sktlim@umich.edu // only works so long as the checker doesn't try to 7532693Sktlim@umich.edu // verify the value in memory for stores. 7542693Sktlim@umich.edu storeQueue[storeWBIdx].inst->setCompleted(); 7552733Sktlim@umich.edu#if USE_CHECKER 7562693Sktlim@umich.edu if (cpu->checker) { 7572732Sktlim@umich.edu cpu->checker->verify(storeQueue[storeWBIdx].inst); 7582693Sktlim@umich.edu } 7592733Sktlim@umich.edu#endif 7602693Sktlim@umich.edu } 7612693Sktlim@umich.edu 7622693Sktlim@umich.edu if (pkt->result != Packet::Success) { 7632693Sktlim@umich.edu DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n", 7642693Sktlim@umich.edu storeWBIdx); 7652693Sktlim@umich.edu 7662693Sktlim@umich.edu DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n", 7672693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum); 7682693Sktlim@umich.edu 7692693Sktlim@umich.edu //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum); 7702693Sktlim@umich.edu 7712693Sktlim@umich.edu //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size()); 7722693Sktlim@umich.edu 7732693Sktlim@umich.edu // @todo: Increment stat here. 7742693Sktlim@umich.edu } else { 7752693Sktlim@umich.edu DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n", 7762693Sktlim@umich.edu storeWBIdx); 7772693Sktlim@umich.edu 7782693Sktlim@umich.edu DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", 7792693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum); 7802693Sktlim@umich.edu } 7812693Sktlim@umich.edu 7822693Sktlim@umich.edu incrStIdx(storeWBIdx); 7832693Sktlim@umich.edu} 7842693Sktlim@umich.edu 7852693Sktlim@umich.edutemplate <class Impl> 7862693Sktlim@umich.eduvoid 7872678Sktlim@umich.eduLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 7882678Sktlim@umich.edu{ 7892678Sktlim@umich.edu iewStage->wakeCPU(); 7902678Sktlim@umich.edu 7912678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 7922678Sktlim@umich.edu if (inst->isSquashed()) { 7932678Sktlim@umich.edu assert(!inst->isStore()); 7942727Sktlim@umich.edu ++lsqIgnoredResponses; 7952678Sktlim@umich.edu return; 7962678Sktlim@umich.edu } 7972678Sktlim@umich.edu 7982678Sktlim@umich.edu if (!inst->isExecuted()) { 7992678Sktlim@umich.edu inst->setExecuted(); 8002678Sktlim@umich.edu 8012678Sktlim@umich.edu // Complete access to copy data to proper place. 8022678Sktlim@umich.edu inst->completeAcc(pkt); 8032678Sktlim@umich.edu } 8042678Sktlim@umich.edu 8052678Sktlim@umich.edu // Need to insert instruction into queue to commit 8062678Sktlim@umich.edu iewStage->instToCommit(inst); 8072678Sktlim@umich.edu 8082678Sktlim@umich.edu iewStage->activityThisCycle(); 8092678Sktlim@umich.edu} 8102678Sktlim@umich.edu 8112678Sktlim@umich.edutemplate <class Impl> 8122678Sktlim@umich.eduvoid 8132292SN/ALSQUnit<Impl>::completeStore(int store_idx) 8142292SN/A{ 8152292SN/A assert(storeQueue[store_idx].inst); 8162292SN/A storeQueue[store_idx].completed = true; 8172292SN/A --storesToWB; 8182292SN/A // A bit conservative because a store completion may not free up entries, 8192292SN/A // but hopefully avoids two store completions in one cycle from making 8202292SN/A // the CPU tick twice. 8212292SN/A cpu->activityThisCycle(); 8222292SN/A 8232292SN/A if (store_idx == storeHead) { 8242292SN/A do { 8252292SN/A incrStIdx(storeHead); 8262292SN/A 8272292SN/A --stores; 8282292SN/A } while (storeQueue[storeHead].completed && 8292292SN/A storeHead != storeTail); 8302292SN/A 8312292SN/A iewStage->updateLSQNextCycle = true; 8322292SN/A } 8332292SN/A 8342329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 8352329SN/A "idx:%i\n", 8362329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 8372292SN/A 8382292SN/A if (isStalled() && 8392292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 8402292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 8412292SN/A "load idx:%i\n", 8422292SN/A stallingStoreIsn, stallingLoadIdx); 8432292SN/A stalled = false; 8442292SN/A stallingStoreIsn = 0; 8452292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 8462292SN/A } 8472316SN/A 8482316SN/A storeQueue[store_idx].inst->setCompleted(); 8492329SN/A 8502329SN/A // Tell the checker we've completed this instruction. Some stores 8512329SN/A // may get reported twice to the checker, but the checker can 8522329SN/A // handle that case. 8532733Sktlim@umich.edu#if USE_CHECKER 8542316SN/A if (cpu->checker) { 8552732Sktlim@umich.edu cpu->checker->verify(storeQueue[store_idx].inst); 8562316SN/A } 8572733Sktlim@umich.edu#endif 8582292SN/A} 8592292SN/A 8602292SN/Atemplate <class Impl> 8612693Sktlim@umich.eduvoid 8622693Sktlim@umich.eduLSQUnit<Impl>::recvRetry() 8632693Sktlim@umich.edu{ 8642698Sktlim@umich.edu if (isStoreBlocked) { 8652698Sktlim@umich.edu assert(retryPkt != NULL); 8662693Sktlim@umich.edu 8672698Sktlim@umich.edu if (dcachePort->sendTiming(retryPkt)) { 8682698Sktlim@umich.edu storePostSend(retryPkt); 8692699Sktlim@umich.edu retryPkt = NULL; 8702693Sktlim@umich.edu isStoreBlocked = false; 8712693Sktlim@umich.edu } else { 8722693Sktlim@umich.edu // Still blocked! 8732727Sktlim@umich.edu ++lsqCacheBlocked; 8742907Sktlim@umich.edu lsq->setRetryTid(lsqID); 8752693Sktlim@umich.edu } 8762693Sktlim@umich.edu } else if (isLoadBlocked) { 8772693Sktlim@umich.edu DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 8782693Sktlim@umich.edu "no need to resend packet.\n"); 8792693Sktlim@umich.edu } else { 8802693Sktlim@umich.edu DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 8812693Sktlim@umich.edu } 8822693Sktlim@umich.edu} 8832693Sktlim@umich.edu 8842693Sktlim@umich.edutemplate <class Impl> 8852292SN/Ainline void 8862292SN/ALSQUnit<Impl>::incrStIdx(int &store_idx) 8872292SN/A{ 8882292SN/A if (++store_idx >= SQEntries) 8892292SN/A store_idx = 0; 8902292SN/A} 8912292SN/A 8922292SN/Atemplate <class Impl> 8932292SN/Ainline void 8942292SN/ALSQUnit<Impl>::decrStIdx(int &store_idx) 8952292SN/A{ 8962292SN/A if (--store_idx < 0) 8972292SN/A store_idx += SQEntries; 8982292SN/A} 8992292SN/A 9002292SN/Atemplate <class Impl> 9012292SN/Ainline void 9022292SN/ALSQUnit<Impl>::incrLdIdx(int &load_idx) 9032292SN/A{ 9042292SN/A if (++load_idx >= LQEntries) 9052292SN/A load_idx = 0; 9062292SN/A} 9072292SN/A 9082292SN/Atemplate <class Impl> 9092292SN/Ainline void 9102292SN/ALSQUnit<Impl>::decrLdIdx(int &load_idx) 9112292SN/A{ 9122292SN/A if (--load_idx < 0) 9132292SN/A load_idx += LQEntries; 9142292SN/A} 9152329SN/A 9162329SN/Atemplate <class Impl> 9172329SN/Avoid 9182329SN/ALSQUnit<Impl>::dumpInsts() 9192329SN/A{ 9202329SN/A cprintf("Load store queue: Dumping instructions.\n"); 9212329SN/A cprintf("Load queue size: %i\n", loads); 9222329SN/A cprintf("Load queue: "); 9232329SN/A 9242329SN/A int load_idx = loadHead; 9252329SN/A 9262329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 9272329SN/A cprintf("%#x ", loadQueue[load_idx]->readPC()); 9282329SN/A 9292329SN/A incrLdIdx(load_idx); 9302329SN/A } 9312329SN/A 9322329SN/A cprintf("Store queue size: %i\n", stores); 9332329SN/A cprintf("Store queue: "); 9342329SN/A 9352329SN/A int store_idx = storeHead; 9362329SN/A 9372329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 9382329SN/A cprintf("%#x ", storeQueue[store_idx].inst->readPC()); 9392329SN/A 9402329SN/A incrStIdx(store_idx); 9412329SN/A } 9422329SN/A 9432329SN/A cprintf("\n"); 9442329SN/A} 945