lsq_unit_impl.hh revision 2727
12292SN/A/* 22292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32292SN/A * All rights reserved. 42292SN/A * 52292SN/A * Redistribution and use in source and binary forms, with or without 62292SN/A * modification, are permitted provided that the following conditions are 72292SN/A * met: redistributions of source code must retain the above copyright 82292SN/A * notice, this list of conditions and the following disclaimer; 92292SN/A * redistributions in binary form must reproduce the above copyright 102292SN/A * notice, this list of conditions and the following disclaimer in the 112292SN/A * documentation and/or other materials provided with the distribution; 122292SN/A * neither the name of the copyright holders nor the names of its 132292SN/A * contributors may be used to endorse or promote products derived from 142292SN/A * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292689Sktlim@umich.edu * Korey Sewell 302292SN/A */ 312292SN/A 322316SN/A#include "cpu/checker/cpu.hh" 332292SN/A#include "cpu/o3/lsq_unit.hh" 342292SN/A#include "base/str.hh" 352722Sktlim@umich.edu#include "mem/packet.hh" 362669Sktlim@umich.edu#include "mem/request.hh" 372292SN/A 382669Sktlim@umich.edutemplate<class Impl> 392678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 402678Sktlim@umich.edu LSQUnit *lsq_ptr) 412678Sktlim@umich.edu : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 422292SN/A{ 432678Sktlim@umich.edu this->setFlags(Event::AutoDelete); 442292SN/A} 452292SN/A 462669Sktlim@umich.edutemplate<class Impl> 472292SN/Avoid 482678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 492292SN/A{ 502678Sktlim@umich.edu if (!lsqPtr->isSwitchedOut()) { 512678Sktlim@umich.edu lsqPtr->writeback(inst, pkt); 522678Sktlim@umich.edu } 532678Sktlim@umich.edu delete pkt; 542678Sktlim@umich.edu} 552292SN/A 562678Sktlim@umich.edutemplate<class Impl> 572678Sktlim@umich.educonst char * 582678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::description() 592678Sktlim@umich.edu{ 602678Sktlim@umich.edu return "Store writeback event"; 612678Sktlim@umich.edu} 622292SN/A 632678Sktlim@umich.edutemplate<class Impl> 642678Sktlim@umich.eduvoid 652678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 662678Sktlim@umich.edu{ 672678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 682678Sktlim@umich.edu DynInstPtr inst = state->inst; 692678Sktlim@umich.edu DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum); 702698Sktlim@umich.edu DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum); 712344SN/A 722678Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 732678Sktlim@umich.edu 742678Sktlim@umich.edu if (isSwitchedOut() || inst->isSquashed()) { 752678Sktlim@umich.edu delete state; 762678Sktlim@umich.edu delete pkt; 772307SN/A return; 782678Sktlim@umich.edu } else { 792678Sktlim@umich.edu if (!state->noWB) { 802678Sktlim@umich.edu writeback(inst, pkt); 812678Sktlim@umich.edu } 822678Sktlim@umich.edu 832678Sktlim@umich.edu if (inst->isStore()) { 842678Sktlim@umich.edu completeStore(state->idx); 852678Sktlim@umich.edu } 862344SN/A } 872307SN/A 882678Sktlim@umich.edu delete state; 892678Sktlim@umich.edu delete pkt; 902292SN/A} 912292SN/A 922292SN/Atemplate <class Impl> 932669Sktlim@umich.eduTick 942669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvAtomic(PacketPtr pkt) 952292SN/A{ 962669Sktlim@umich.edu panic("O3CPU model does not work with atomic mode!"); 972669Sktlim@umich.edu return curTick; 982669Sktlim@umich.edu} 992669Sktlim@umich.edu 1002669Sktlim@umich.edutemplate <class Impl> 1012669Sktlim@umich.eduvoid 1022669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvFunctional(PacketPtr pkt) 1032669Sktlim@umich.edu{ 1042669Sktlim@umich.edu panic("O3CPU doesn't expect recvFunctional callback!"); 1052669Sktlim@umich.edu} 1062669Sktlim@umich.edu 1072669Sktlim@umich.edutemplate <class Impl> 1082669Sktlim@umich.eduvoid 1092669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvStatusChange(Status status) 1102669Sktlim@umich.edu{ 1112669Sktlim@umich.edu if (status == RangeChange) 1122669Sktlim@umich.edu return; 1132669Sktlim@umich.edu 1142669Sktlim@umich.edu panic("O3CPU doesn't expect recvStatusChange callback!"); 1152669Sktlim@umich.edu} 1162669Sktlim@umich.edu 1172669Sktlim@umich.edutemplate <class Impl> 1182669Sktlim@umich.edubool 1192669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvTiming(PacketPtr pkt) 1202669Sktlim@umich.edu{ 1212669Sktlim@umich.edu lsq->completeDataAccess(pkt); 1222669Sktlim@umich.edu return true; 1232669Sktlim@umich.edu} 1242669Sktlim@umich.edu 1252669Sktlim@umich.edutemplate <class Impl> 1262669Sktlim@umich.eduvoid 1272669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvRetry() 1282669Sktlim@umich.edu{ 1292693Sktlim@umich.edu lsq->recvRetry(); 1302292SN/A} 1312292SN/A 1322292SN/Atemplate <class Impl> 1332292SN/ALSQUnit<Impl>::LSQUnit() 1342678Sktlim@umich.edu : loads(0), stores(0), storesToWB(0), stalled(false), 1352678Sktlim@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1362292SN/A loadBlockedHandled(false) 1372292SN/A{ 1382292SN/A} 1392292SN/A 1402292SN/Atemplate<class Impl> 1412292SN/Avoid 1422292SN/ALSQUnit<Impl>::init(Params *params, unsigned maxLQEntries, 1432292SN/A unsigned maxSQEntries, unsigned id) 1442292SN/A{ 1452292SN/A DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1462292SN/A 1472307SN/A switchedOut = false; 1482307SN/A 1492292SN/A lsqID = id; 1502292SN/A 1512329SN/A // Add 1 for the sentinel entry (they are circular queues). 1522329SN/A LQEntries = maxLQEntries + 1; 1532329SN/A SQEntries = maxSQEntries + 1; 1542292SN/A 1552292SN/A loadQueue.resize(LQEntries); 1562292SN/A storeQueue.resize(SQEntries); 1572292SN/A 1582292SN/A loadHead = loadTail = 0; 1592292SN/A 1602292SN/A storeHead = storeWBIdx = storeTail = 0; 1612292SN/A 1622292SN/A usedPorts = 0; 1632292SN/A cachePorts = params->cachePorts; 1642292SN/A 1652678Sktlim@umich.edu mem = params->mem; 1662292SN/A 1672329SN/A memDepViolator = NULL; 1682292SN/A 1692292SN/A blockedLoadSeqNum = 0; 1702292SN/A} 1712292SN/A 1722292SN/Atemplate<class Impl> 1732669Sktlim@umich.eduvoid 1742669Sktlim@umich.eduLSQUnit<Impl>::setCPU(FullCPU *cpu_ptr) 1752669Sktlim@umich.edu{ 1762669Sktlim@umich.edu cpu = cpu_ptr; 1772669Sktlim@umich.edu dcachePort = new DcachePort(cpu, this); 1782678Sktlim@umich.edu 1792678Sktlim@umich.edu Port *mem_dport = mem->getPort(""); 1802678Sktlim@umich.edu dcachePort->setPeer(mem_dport); 1812678Sktlim@umich.edu mem_dport->setPeer(dcachePort); 1822679Sktlim@umich.edu 1832679Sktlim@umich.edu if (cpu->checker) { 1842679Sktlim@umich.edu cpu->checker->setDcachePort(dcachePort); 1852679Sktlim@umich.edu } 1862669Sktlim@umich.edu} 1872669Sktlim@umich.edu 1882669Sktlim@umich.edutemplate<class Impl> 1892292SN/Astd::string 1902292SN/ALSQUnit<Impl>::name() const 1912292SN/A{ 1922292SN/A if (Impl::MaxThreads == 1) { 1932292SN/A return iewStage->name() + ".lsq"; 1942292SN/A } else { 1952292SN/A return iewStage->name() + ".lsq.thread." + to_string(lsqID); 1962292SN/A } 1972292SN/A} 1982292SN/A 1992292SN/Atemplate<class Impl> 2002292SN/Avoid 2012727Sktlim@umich.eduLSQUnit<Impl>::regStats() 2022727Sktlim@umich.edu{ 2032727Sktlim@umich.edu lsqForwLoads 2042727Sktlim@umich.edu .name(name() + ".forwLoads") 2052727Sktlim@umich.edu .desc("Number of loads that had data forwarded from stores"); 2062727Sktlim@umich.edu 2072727Sktlim@umich.edu invAddrLoads 2082727Sktlim@umich.edu .name(name() + ".invAddrLoads") 2092727Sktlim@umich.edu .desc("Number of loads ignored due to an invalid address"); 2102727Sktlim@umich.edu 2112727Sktlim@umich.edu lsqSquashedLoads 2122727Sktlim@umich.edu .name(name() + ".squashedLoads") 2132727Sktlim@umich.edu .desc("Number of loads squashed"); 2142727Sktlim@umich.edu 2152727Sktlim@umich.edu lsqIgnoredResponses 2162727Sktlim@umich.edu .name(name() + ".ignoredResponses") 2172727Sktlim@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 2182727Sktlim@umich.edu 2192727Sktlim@umich.edu lsqSquashedStores 2202727Sktlim@umich.edu .name(name() + ".squashedStores") 2212727Sktlim@umich.edu .desc("Number of stores squashed"); 2222727Sktlim@umich.edu 2232727Sktlim@umich.edu invAddrSwpfs 2242727Sktlim@umich.edu .name(name() + ".invAddrSwpfs") 2252727Sktlim@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 2262727Sktlim@umich.edu 2272727Sktlim@umich.edu lsqBlockedLoads 2282727Sktlim@umich.edu .name(name() + ".blockedLoads") 2292727Sktlim@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 2302727Sktlim@umich.edu 2312727Sktlim@umich.edu lsqRescheduledLoads 2322727Sktlim@umich.edu .name(name() + ".rescheduledLoads") 2332727Sktlim@umich.edu .desc("Number of loads that were rescheduled"); 2342727Sktlim@umich.edu 2352727Sktlim@umich.edu lsqCacheBlocked 2362727Sktlim@umich.edu .name(name() + ".cacheBlocked") 2372727Sktlim@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2382727Sktlim@umich.edu} 2392727Sktlim@umich.edu 2402727Sktlim@umich.edutemplate<class Impl> 2412727Sktlim@umich.eduvoid 2422292SN/ALSQUnit<Impl>::clearLQ() 2432292SN/A{ 2442292SN/A loadQueue.clear(); 2452292SN/A} 2462292SN/A 2472292SN/Atemplate<class Impl> 2482292SN/Avoid 2492292SN/ALSQUnit<Impl>::clearSQ() 2502292SN/A{ 2512292SN/A storeQueue.clear(); 2522292SN/A} 2532292SN/A 2542292SN/Atemplate<class Impl> 2552292SN/Avoid 2562307SN/ALSQUnit<Impl>::switchOut() 2572307SN/A{ 2582307SN/A switchedOut = true; 2592307SN/A for (int i = 0; i < loadQueue.size(); ++i) 2602307SN/A loadQueue[i] = NULL; 2612307SN/A 2622329SN/A assert(storesToWB == 0); 2632307SN/A} 2642307SN/A 2652307SN/Atemplate<class Impl> 2662307SN/Avoid 2672307SN/ALSQUnit<Impl>::takeOverFrom() 2682307SN/A{ 2692307SN/A switchedOut = false; 2702307SN/A loads = stores = storesToWB = 0; 2712307SN/A 2722307SN/A loadHead = loadTail = 0; 2732307SN/A 2742307SN/A storeHead = storeWBIdx = storeTail = 0; 2752307SN/A 2762307SN/A usedPorts = 0; 2772307SN/A 2782329SN/A memDepViolator = NULL; 2792307SN/A 2802307SN/A blockedLoadSeqNum = 0; 2812307SN/A 2822307SN/A stalled = false; 2832307SN/A isLoadBlocked = false; 2842307SN/A loadBlockedHandled = false; 2852307SN/A} 2862307SN/A 2872307SN/Atemplate<class Impl> 2882307SN/Avoid 2892292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 2902292SN/A{ 2912329SN/A unsigned size_plus_sentinel = size + 1; 2922329SN/A assert(size_plus_sentinel >= LQEntries); 2932292SN/A 2942329SN/A if (size_plus_sentinel > LQEntries) { 2952329SN/A while (size_plus_sentinel > loadQueue.size()) { 2962292SN/A DynInstPtr dummy; 2972292SN/A loadQueue.push_back(dummy); 2982292SN/A LQEntries++; 2992292SN/A } 3002292SN/A } else { 3012329SN/A LQEntries = size_plus_sentinel; 3022292SN/A } 3032292SN/A 3042292SN/A} 3052292SN/A 3062292SN/Atemplate<class Impl> 3072292SN/Avoid 3082292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 3092292SN/A{ 3102329SN/A unsigned size_plus_sentinel = size + 1; 3112329SN/A if (size_plus_sentinel > SQEntries) { 3122329SN/A while (size_plus_sentinel > storeQueue.size()) { 3132292SN/A SQEntry dummy; 3142292SN/A storeQueue.push_back(dummy); 3152292SN/A SQEntries++; 3162292SN/A } 3172292SN/A } else { 3182329SN/A SQEntries = size_plus_sentinel; 3192292SN/A } 3202292SN/A} 3212292SN/A 3222292SN/Atemplate <class Impl> 3232292SN/Avoid 3242292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 3252292SN/A{ 3262292SN/A assert(inst->isMemRef()); 3272292SN/A 3282292SN/A assert(inst->isLoad() || inst->isStore()); 3292292SN/A 3302292SN/A if (inst->isLoad()) { 3312292SN/A insertLoad(inst); 3322292SN/A } else { 3332292SN/A insertStore(inst); 3342292SN/A } 3352292SN/A 3362292SN/A inst->setInLSQ(); 3372292SN/A} 3382292SN/A 3392292SN/Atemplate <class Impl> 3402292SN/Avoid 3412292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3422292SN/A{ 3432329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3442329SN/A assert(loads < LQEntries); 3452292SN/A 3462292SN/A DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n", 3472292SN/A load_inst->readPC(), loadTail, load_inst->seqNum); 3482292SN/A 3492292SN/A load_inst->lqIdx = loadTail; 3502292SN/A 3512292SN/A if (stores == 0) { 3522292SN/A load_inst->sqIdx = -1; 3532292SN/A } else { 3542292SN/A load_inst->sqIdx = storeTail; 3552292SN/A } 3562292SN/A 3572292SN/A loadQueue[loadTail] = load_inst; 3582292SN/A 3592292SN/A incrLdIdx(loadTail); 3602292SN/A 3612292SN/A ++loads; 3622292SN/A} 3632292SN/A 3642292SN/Atemplate <class Impl> 3652292SN/Avoid 3662292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3672292SN/A{ 3682292SN/A // Make sure it is not full before inserting an instruction. 3692292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3702292SN/A assert(stores < SQEntries); 3712292SN/A 3722292SN/A DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n", 3732292SN/A store_inst->readPC(), storeTail, store_inst->seqNum); 3742292SN/A 3752292SN/A store_inst->sqIdx = storeTail; 3762292SN/A store_inst->lqIdx = loadTail; 3772292SN/A 3782292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3792292SN/A 3802292SN/A incrStIdx(storeTail); 3812292SN/A 3822292SN/A ++stores; 3832292SN/A} 3842292SN/A 3852292SN/Atemplate <class Impl> 3862292SN/Atypename Impl::DynInstPtr 3872292SN/ALSQUnit<Impl>::getMemDepViolator() 3882292SN/A{ 3892292SN/A DynInstPtr temp = memDepViolator; 3902292SN/A 3912292SN/A memDepViolator = NULL; 3922292SN/A 3932292SN/A return temp; 3942292SN/A} 3952292SN/A 3962292SN/Atemplate <class Impl> 3972292SN/Aunsigned 3982292SN/ALSQUnit<Impl>::numFreeEntries() 3992292SN/A{ 4002292SN/A unsigned free_lq_entries = LQEntries - loads; 4012292SN/A unsigned free_sq_entries = SQEntries - stores; 4022292SN/A 4032292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 4042292SN/A // empty/full conditions. Subtract 1 from the free entries. 4052292SN/A if (free_lq_entries < free_sq_entries) { 4062292SN/A return free_lq_entries - 1; 4072292SN/A } else { 4082292SN/A return free_sq_entries - 1; 4092292SN/A } 4102292SN/A} 4112292SN/A 4122292SN/Atemplate <class Impl> 4132292SN/Aint 4142292SN/ALSQUnit<Impl>::numLoadsReady() 4152292SN/A{ 4162292SN/A int load_idx = loadHead; 4172292SN/A int retval = 0; 4182292SN/A 4192292SN/A while (load_idx != loadTail) { 4202292SN/A assert(loadQueue[load_idx]); 4212292SN/A 4222292SN/A if (loadQueue[load_idx]->readyToIssue()) { 4232292SN/A ++retval; 4242292SN/A } 4252292SN/A } 4262292SN/A 4272292SN/A return retval; 4282292SN/A} 4292292SN/A 4302292SN/Atemplate <class Impl> 4312292SN/AFault 4322292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 4332292SN/A{ 4342292SN/A // Execute a specific load. 4352292SN/A Fault load_fault = NoFault; 4362292SN/A 4372292SN/A DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n", 4382292SN/A inst->readPC(),inst->seqNum); 4392292SN/A 4402669Sktlim@umich.edu load_fault = inst->initiateAcc(); 4412292SN/A 4422292SN/A // If the instruction faulted, then we need to send it along to commit 4432292SN/A // without the instruction completing. 4442292SN/A if (load_fault != NoFault) { 4452329SN/A // Send this instruction to commit, also make sure iew stage 4462329SN/A // realizes there is activity. 4472292SN/A iewStage->instToCommit(inst); 4482292SN/A iewStage->activityThisCycle(); 4492292SN/A } 4502292SN/A 4512292SN/A return load_fault; 4522292SN/A} 4532292SN/A 4542292SN/Atemplate <class Impl> 4552292SN/AFault 4562292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 4572292SN/A{ 4582292SN/A using namespace TheISA; 4592292SN/A // Make sure that a store exists. 4602292SN/A assert(stores != 0); 4612292SN/A 4622292SN/A int store_idx = store_inst->sqIdx; 4632292SN/A 4642292SN/A DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n", 4652292SN/A store_inst->readPC(), store_inst->seqNum); 4662292SN/A 4672292SN/A // Check the recently completed loads to see if any match this store's 4682292SN/A // address. If so, then we have a memory ordering violation. 4692292SN/A int load_idx = store_inst->lqIdx; 4702292SN/A 4712292SN/A Fault store_fault = store_inst->initiateAcc(); 4722292SN/A 4732329SN/A if (storeQueue[store_idx].size == 0) { 4742292SN/A DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n", 4752292SN/A store_inst->readPC(),store_inst->seqNum); 4762292SN/A 4772292SN/A return store_fault; 4782292SN/A } 4792292SN/A 4802292SN/A assert(store_fault == NoFault); 4812292SN/A 4822336SN/A if (store_inst->isStoreConditional()) { 4832336SN/A // Store conditionals need to set themselves as able to 4842336SN/A // writeback if we haven't had a fault by here. 4852329SN/A storeQueue[store_idx].canWB = true; 4862292SN/A 4872329SN/A ++storesToWB; 4882292SN/A } 4892292SN/A 4902292SN/A if (!memDepViolator) { 4912292SN/A while (load_idx != loadTail) { 4922329SN/A // Really only need to check loads that have actually executed 4932329SN/A // It's safe to check all loads because effAddr is set to 4942329SN/A // InvalAddr when the dyn inst is created. 4952292SN/A 4962329SN/A // @todo: For now this is extra conservative, detecting a 4972329SN/A // violation if the addresses match assuming all accesses 4982329SN/A // are quad word accesses. 4992329SN/A 5002292SN/A // @todo: Fix this, magic number being used here 5012292SN/A if ((loadQueue[load_idx]->effAddr >> 8) == 5022292SN/A (store_inst->effAddr >> 8)) { 5032292SN/A // A load incorrectly passed this store. Squash and refetch. 5042292SN/A // For now return a fault to show that it was unsuccessful. 5052292SN/A memDepViolator = loadQueue[load_idx]; 5062292SN/A 5072292SN/A return genMachineCheckFault(); 5082292SN/A } 5092292SN/A 5102292SN/A incrLdIdx(load_idx); 5112292SN/A } 5122292SN/A 5132292SN/A // If we've reached this point, there was no violation. 5142292SN/A memDepViolator = NULL; 5152292SN/A } 5162292SN/A 5172292SN/A return store_fault; 5182292SN/A} 5192292SN/A 5202292SN/Atemplate <class Impl> 5212292SN/Avoid 5222292SN/ALSQUnit<Impl>::commitLoad() 5232292SN/A{ 5242292SN/A assert(loadQueue[loadHead]); 5252292SN/A 5262292SN/A DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n", 5272292SN/A loadQueue[loadHead]->readPC()); 5282292SN/A 5292292SN/A loadQueue[loadHead] = NULL; 5302292SN/A 5312292SN/A incrLdIdx(loadHead); 5322292SN/A 5332292SN/A --loads; 5342292SN/A} 5352292SN/A 5362292SN/Atemplate <class Impl> 5372292SN/Avoid 5382292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 5392292SN/A{ 5402292SN/A assert(loads == 0 || loadQueue[loadHead]); 5412292SN/A 5422292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 5432292SN/A commitLoad(); 5442292SN/A } 5452292SN/A} 5462292SN/A 5472292SN/Atemplate <class Impl> 5482292SN/Avoid 5492292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 5502292SN/A{ 5512292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 5522292SN/A 5532292SN/A int store_idx = storeHead; 5542292SN/A 5552292SN/A while (store_idx != storeTail) { 5562292SN/A assert(storeQueue[store_idx].inst); 5572329SN/A // Mark any stores that are now committed and have not yet 5582329SN/A // been marked as able to write back. 5592292SN/A if (!storeQueue[store_idx].canWB) { 5602292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 5612292SN/A break; 5622292SN/A } 5632292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 5642292SN/A "%#x [sn:%lli]\n", 5652292SN/A storeQueue[store_idx].inst->readPC(), 5662292SN/A storeQueue[store_idx].inst->seqNum); 5672292SN/A 5682292SN/A storeQueue[store_idx].canWB = true; 5692292SN/A 5702292SN/A ++storesToWB; 5712292SN/A } 5722292SN/A 5732292SN/A incrStIdx(store_idx); 5742292SN/A } 5752292SN/A} 5762292SN/A 5772292SN/Atemplate <class Impl> 5782292SN/Avoid 5792292SN/ALSQUnit<Impl>::writebackStores() 5802292SN/A{ 5812292SN/A while (storesToWB > 0 && 5822292SN/A storeWBIdx != storeTail && 5832292SN/A storeQueue[storeWBIdx].inst && 5842292SN/A storeQueue[storeWBIdx].canWB && 5852292SN/A usedPorts < cachePorts) { 5862292SN/A 5872678Sktlim@umich.edu if (isStoreBlocked) { 5882678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 5892678Sktlim@umich.edu " is blocked!\n"); 5902678Sktlim@umich.edu break; 5912678Sktlim@umich.edu } 5922678Sktlim@umich.edu 5932329SN/A // Store didn't write any data so no need to write it back to 5942329SN/A // memory. 5952292SN/A if (storeQueue[storeWBIdx].size == 0) { 5962292SN/A completeStore(storeWBIdx); 5972292SN/A 5982292SN/A incrStIdx(storeWBIdx); 5992292SN/A 6002292SN/A continue; 6012292SN/A } 6022678Sktlim@umich.edu 6032292SN/A ++usedPorts; 6042292SN/A 6052292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 6062292SN/A incrStIdx(storeWBIdx); 6072292SN/A 6082292SN/A continue; 6092292SN/A } 6102292SN/A 6112292SN/A assert(storeQueue[storeWBIdx].req); 6122292SN/A assert(!storeQueue[storeWBIdx].committed); 6132292SN/A 6142669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 6152669Sktlim@umich.edu 6162669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 6172292SN/A storeQueue[storeWBIdx].committed = true; 6182292SN/A 6192669Sktlim@umich.edu assert(!inst->memData); 6202669Sktlim@umich.edu inst->memData = new uint8_t[64]; 6212678Sktlim@umich.edu memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data, 6222678Sktlim@umich.edu req->getSize()); 6232669Sktlim@umich.edu 6242669Sktlim@umich.edu PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 6252669Sktlim@umich.edu data_pkt->dataStatic(inst->memData); 6262292SN/A 6272678Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 6282678Sktlim@umich.edu state->isLoad = false; 6292678Sktlim@umich.edu state->idx = storeWBIdx; 6302678Sktlim@umich.edu state->inst = inst; 6312678Sktlim@umich.edu data_pkt->senderState = state; 6322678Sktlim@umich.edu 6332292SN/A DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " 6342292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 6352669Sktlim@umich.edu storeWBIdx, storeQueue[storeWBIdx].inst->readPC(), 6362669Sktlim@umich.edu req->getPaddr(), *(inst->memData), 6372292SN/A storeQueue[storeWBIdx].inst->seqNum); 6382292SN/A 6392693Sktlim@umich.edu // @todo: Remove this SC hack once the memory system handles it. 6402693Sktlim@umich.edu if (req->getFlags() & LOCKED) { 6412693Sktlim@umich.edu if (req->getFlags() & UNCACHEABLE) { 6422693Sktlim@umich.edu req->setScResult(2); 6432693Sktlim@umich.edu } else { 6442693Sktlim@umich.edu if (cpu->lockFlag) { 6452693Sktlim@umich.edu req->setScResult(1); 6462693Sktlim@umich.edu } else { 6472693Sktlim@umich.edu req->setScResult(0); 6482693Sktlim@umich.edu // Hack: Instantly complete this store. 6492693Sktlim@umich.edu completeDataAccess(data_pkt); 6502693Sktlim@umich.edu incrStIdx(storeWBIdx); 6512693Sktlim@umich.edu continue; 6522693Sktlim@umich.edu } 6532693Sktlim@umich.edu } 6542693Sktlim@umich.edu } else { 6552693Sktlim@umich.edu // Non-store conditionals do not need a writeback. 6562693Sktlim@umich.edu state->noWB = true; 6572693Sktlim@umich.edu } 6582693Sktlim@umich.edu 6592669Sktlim@umich.edu if (!dcachePort->sendTiming(data_pkt)) { 6602669Sktlim@umich.edu // Need to handle becoming blocked on a store. 6612678Sktlim@umich.edu isStoreBlocked = true; 6622727Sktlim@umich.edu ++lsqCacheBlocked; 6632698Sktlim@umich.edu assert(retryPkt == NULL); 6642698Sktlim@umich.edu retryPkt = data_pkt; 6652669Sktlim@umich.edu } else { 6662693Sktlim@umich.edu storePostSend(data_pkt); 6672292SN/A } 6682292SN/A } 6692292SN/A 6702292SN/A // Not sure this should set it to 0. 6712292SN/A usedPorts = 0; 6722292SN/A 6732292SN/A assert(stores >= 0 && storesToWB >= 0); 6742292SN/A} 6752292SN/A 6762292SN/A/*template <class Impl> 6772292SN/Avoid 6782292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 6792292SN/A{ 6802292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 6812292SN/A mshrSeqNums.end(), 6822292SN/A seqNum); 6832292SN/A 6842292SN/A if (mshr_it != mshrSeqNums.end()) { 6852292SN/A mshrSeqNums.erase(mshr_it); 6862292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 6872292SN/A } 6882292SN/A}*/ 6892292SN/A 6902292SN/Atemplate <class Impl> 6912292SN/Avoid 6922292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 6932292SN/A{ 6942292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 6952329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 6962292SN/A 6972292SN/A int load_idx = loadTail; 6982292SN/A decrLdIdx(load_idx); 6992292SN/A 7002292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 7012292SN/A DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, " 7022292SN/A "[sn:%lli]\n", 7032292SN/A loadQueue[load_idx]->readPC(), 7042292SN/A loadQueue[load_idx]->seqNum); 7052292SN/A 7062292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 7072292SN/A stalled = false; 7082292SN/A stallingStoreIsn = 0; 7092292SN/A stallingLoadIdx = 0; 7102292SN/A } 7112292SN/A 7122329SN/A // Clear the smart pointer to make sure it is decremented. 7132292SN/A loadQueue[load_idx]->squashed = true; 7142292SN/A loadQueue[load_idx] = NULL; 7152292SN/A --loads; 7162292SN/A 7172292SN/A // Inefficient! 7182292SN/A loadTail = load_idx; 7192292SN/A 7202292SN/A decrLdIdx(load_idx); 7212727Sktlim@umich.edu ++lsqSquashedLoads; 7222292SN/A } 7232292SN/A 7242292SN/A if (isLoadBlocked) { 7252292SN/A if (squashed_num < blockedLoadSeqNum) { 7262292SN/A isLoadBlocked = false; 7272292SN/A loadBlockedHandled = false; 7282292SN/A blockedLoadSeqNum = 0; 7292292SN/A } 7302292SN/A } 7312292SN/A 7322292SN/A int store_idx = storeTail; 7332292SN/A decrStIdx(store_idx); 7342292SN/A 7352292SN/A while (stores != 0 && 7362292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 7372329SN/A // Instructions marked as can WB are already committed. 7382292SN/A if (storeQueue[store_idx].canWB) { 7392292SN/A break; 7402292SN/A } 7412292SN/A 7422292SN/A DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, " 7432292SN/A "idx:%i [sn:%lli]\n", 7442292SN/A storeQueue[store_idx].inst->readPC(), 7452292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 7462292SN/A 7472329SN/A // I don't think this can happen. It should have been cleared 7482329SN/A // by the stalling load. 7492292SN/A if (isStalled() && 7502292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 7512292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 7522292SN/A stalled = false; 7532292SN/A stallingStoreIsn = 0; 7542292SN/A } 7552292SN/A 7562329SN/A // Clear the smart pointer to make sure it is decremented. 7572292SN/A storeQueue[store_idx].inst->squashed = true; 7582292SN/A storeQueue[store_idx].inst = NULL; 7592292SN/A storeQueue[store_idx].canWB = 0; 7602292SN/A 7612292SN/A storeQueue[store_idx].req = NULL; 7622292SN/A --stores; 7632292SN/A 7642292SN/A // Inefficient! 7652292SN/A storeTail = store_idx; 7662292SN/A 7672292SN/A decrStIdx(store_idx); 7682727Sktlim@umich.edu ++lsqSquashedStores; 7692292SN/A } 7702292SN/A} 7712292SN/A 7722292SN/Atemplate <class Impl> 7732292SN/Avoid 7742693Sktlim@umich.eduLSQUnit<Impl>::storePostSend(Packet *pkt) 7752693Sktlim@umich.edu{ 7762693Sktlim@umich.edu if (isStalled() && 7772693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 7782693Sktlim@umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 7792693Sktlim@umich.edu "load idx:%i\n", 7802693Sktlim@umich.edu stallingStoreIsn, stallingLoadIdx); 7812693Sktlim@umich.edu stalled = false; 7822693Sktlim@umich.edu stallingStoreIsn = 0; 7832693Sktlim@umich.edu iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 7842693Sktlim@umich.edu } 7852693Sktlim@umich.edu 7862693Sktlim@umich.edu if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 7872693Sktlim@umich.edu // The store is basically completed at this time. This 7882693Sktlim@umich.edu // only works so long as the checker doesn't try to 7892693Sktlim@umich.edu // verify the value in memory for stores. 7902693Sktlim@umich.edu storeQueue[storeWBIdx].inst->setCompleted(); 7912693Sktlim@umich.edu if (cpu->checker) { 7922693Sktlim@umich.edu cpu->checker->tick(storeQueue[storeWBIdx].inst); 7932693Sktlim@umich.edu } 7942693Sktlim@umich.edu } 7952693Sktlim@umich.edu 7962693Sktlim@umich.edu if (pkt->result != Packet::Success) { 7972693Sktlim@umich.edu DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n", 7982693Sktlim@umich.edu storeWBIdx); 7992693Sktlim@umich.edu 8002693Sktlim@umich.edu DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n", 8012693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum); 8022693Sktlim@umich.edu 8032693Sktlim@umich.edu //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum); 8042693Sktlim@umich.edu 8052693Sktlim@umich.edu //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size()); 8062693Sktlim@umich.edu 8072693Sktlim@umich.edu // @todo: Increment stat here. 8082693Sktlim@umich.edu } else { 8092693Sktlim@umich.edu DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n", 8102693Sktlim@umich.edu storeWBIdx); 8112693Sktlim@umich.edu 8122693Sktlim@umich.edu DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", 8132693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum); 8142693Sktlim@umich.edu } 8152693Sktlim@umich.edu 8162693Sktlim@umich.edu incrStIdx(storeWBIdx); 8172693Sktlim@umich.edu} 8182693Sktlim@umich.edu 8192693Sktlim@umich.edutemplate <class Impl> 8202693Sktlim@umich.eduvoid 8212678Sktlim@umich.eduLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 8222678Sktlim@umich.edu{ 8232678Sktlim@umich.edu iewStage->wakeCPU(); 8242678Sktlim@umich.edu 8252678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 8262678Sktlim@umich.edu if (inst->isSquashed()) { 8272678Sktlim@umich.edu assert(!inst->isStore()); 8282727Sktlim@umich.edu ++lsqIgnoredResponses; 8292678Sktlim@umich.edu return; 8302678Sktlim@umich.edu } 8312678Sktlim@umich.edu 8322678Sktlim@umich.edu if (!inst->isExecuted()) { 8332678Sktlim@umich.edu inst->setExecuted(); 8342678Sktlim@umich.edu 8352678Sktlim@umich.edu // Complete access to copy data to proper place. 8362678Sktlim@umich.edu inst->completeAcc(pkt); 8372678Sktlim@umich.edu } 8382678Sktlim@umich.edu 8392678Sktlim@umich.edu // Need to insert instruction into queue to commit 8402678Sktlim@umich.edu iewStage->instToCommit(inst); 8412678Sktlim@umich.edu 8422678Sktlim@umich.edu iewStage->activityThisCycle(); 8432678Sktlim@umich.edu} 8442678Sktlim@umich.edu 8452678Sktlim@umich.edutemplate <class Impl> 8462678Sktlim@umich.eduvoid 8472292SN/ALSQUnit<Impl>::completeStore(int store_idx) 8482292SN/A{ 8492292SN/A assert(storeQueue[store_idx].inst); 8502292SN/A storeQueue[store_idx].completed = true; 8512292SN/A --storesToWB; 8522292SN/A // A bit conservative because a store completion may not free up entries, 8532292SN/A // but hopefully avoids two store completions in one cycle from making 8542292SN/A // the CPU tick twice. 8552292SN/A cpu->activityThisCycle(); 8562292SN/A 8572292SN/A if (store_idx == storeHead) { 8582292SN/A do { 8592292SN/A incrStIdx(storeHead); 8602292SN/A 8612292SN/A --stores; 8622292SN/A } while (storeQueue[storeHead].completed && 8632292SN/A storeHead != storeTail); 8642292SN/A 8652292SN/A iewStage->updateLSQNextCycle = true; 8662292SN/A } 8672292SN/A 8682329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 8692329SN/A "idx:%i\n", 8702329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 8712292SN/A 8722292SN/A if (isStalled() && 8732292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 8742292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 8752292SN/A "load idx:%i\n", 8762292SN/A stallingStoreIsn, stallingLoadIdx); 8772292SN/A stalled = false; 8782292SN/A stallingStoreIsn = 0; 8792292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 8802292SN/A } 8812316SN/A 8822316SN/A storeQueue[store_idx].inst->setCompleted(); 8832329SN/A 8842329SN/A // Tell the checker we've completed this instruction. Some stores 8852329SN/A // may get reported twice to the checker, but the checker can 8862329SN/A // handle that case. 8872316SN/A if (cpu->checker) { 8882316SN/A cpu->checker->tick(storeQueue[store_idx].inst); 8892316SN/A } 8902292SN/A} 8912292SN/A 8922292SN/Atemplate <class Impl> 8932693Sktlim@umich.eduvoid 8942693Sktlim@umich.eduLSQUnit<Impl>::recvRetry() 8952693Sktlim@umich.edu{ 8962698Sktlim@umich.edu if (isStoreBlocked) { 8972698Sktlim@umich.edu assert(retryPkt != NULL); 8982693Sktlim@umich.edu 8992698Sktlim@umich.edu if (dcachePort->sendTiming(retryPkt)) { 9002698Sktlim@umich.edu storePostSend(retryPkt); 9012699Sktlim@umich.edu retryPkt = NULL; 9022693Sktlim@umich.edu isStoreBlocked = false; 9032693Sktlim@umich.edu } else { 9042693Sktlim@umich.edu // Still blocked! 9052727Sktlim@umich.edu ++lsqCacheBlocked; 9062693Sktlim@umich.edu } 9072693Sktlim@umich.edu } else if (isLoadBlocked) { 9082693Sktlim@umich.edu DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 9092693Sktlim@umich.edu "no need to resend packet.\n"); 9102693Sktlim@umich.edu } else { 9112693Sktlim@umich.edu DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 9122693Sktlim@umich.edu } 9132693Sktlim@umich.edu} 9142693Sktlim@umich.edu 9152693Sktlim@umich.edutemplate <class Impl> 9162292SN/Ainline void 9172292SN/ALSQUnit<Impl>::incrStIdx(int &store_idx) 9182292SN/A{ 9192292SN/A if (++store_idx >= SQEntries) 9202292SN/A store_idx = 0; 9212292SN/A} 9222292SN/A 9232292SN/Atemplate <class Impl> 9242292SN/Ainline void 9252292SN/ALSQUnit<Impl>::decrStIdx(int &store_idx) 9262292SN/A{ 9272292SN/A if (--store_idx < 0) 9282292SN/A store_idx += SQEntries; 9292292SN/A} 9302292SN/A 9312292SN/Atemplate <class Impl> 9322292SN/Ainline void 9332292SN/ALSQUnit<Impl>::incrLdIdx(int &load_idx) 9342292SN/A{ 9352292SN/A if (++load_idx >= LQEntries) 9362292SN/A load_idx = 0; 9372292SN/A} 9382292SN/A 9392292SN/Atemplate <class Impl> 9402292SN/Ainline void 9412292SN/ALSQUnit<Impl>::decrLdIdx(int &load_idx) 9422292SN/A{ 9432292SN/A if (--load_idx < 0) 9442292SN/A load_idx += LQEntries; 9452292SN/A} 9462329SN/A 9472329SN/Atemplate <class Impl> 9482329SN/Avoid 9492329SN/ALSQUnit<Impl>::dumpInsts() 9502329SN/A{ 9512329SN/A cprintf("Load store queue: Dumping instructions.\n"); 9522329SN/A cprintf("Load queue size: %i\n", loads); 9532329SN/A cprintf("Load queue: "); 9542329SN/A 9552329SN/A int load_idx = loadHead; 9562329SN/A 9572329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 9582329SN/A cprintf("%#x ", loadQueue[load_idx]->readPC()); 9592329SN/A 9602329SN/A incrLdIdx(load_idx); 9612329SN/A } 9622329SN/A 9632329SN/A cprintf("Store queue size: %i\n", stores); 9642329SN/A cprintf("Store queue: "); 9652329SN/A 9662329SN/A int store_idx = storeHead; 9672329SN/A 9682329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 9692329SN/A cprintf("%#x ", storeQueue[store_idx].inst->readPC()); 9702329SN/A 9712329SN/A incrStIdx(store_idx); 9722329SN/A } 9732329SN/A 9742329SN/A cprintf("\n"); 9752329SN/A} 976