lsq_unit_impl.hh revision 2722
12292SN/A/* 22292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32292SN/A * All rights reserved. 42292SN/A * 52292SN/A * Redistribution and use in source and binary forms, with or without 62292SN/A * modification, are permitted provided that the following conditions are 72292SN/A * met: redistributions of source code must retain the above copyright 82292SN/A * notice, this list of conditions and the following disclaimer; 92292SN/A * redistributions in binary form must reproduce the above copyright 102292SN/A * notice, this list of conditions and the following disclaimer in the 112292SN/A * documentation and/or other materials provided with the distribution; 122292SN/A * neither the name of the copyright holders nor the names of its 132292SN/A * contributors may be used to endorse or promote products derived from 142292SN/A * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292689Sktlim@umich.edu * Korey Sewell 302292SN/A */ 312292SN/A 322316SN/A#include "cpu/checker/cpu.hh" 332292SN/A#include "cpu/o3/lsq_unit.hh" 342292SN/A#include "base/str.hh" 352722Sktlim@umich.edu#include "mem/packet.hh" 362669Sktlim@umich.edu#include "mem/request.hh" 372292SN/A 382669Sktlim@umich.edutemplate<class Impl> 392678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 402678Sktlim@umich.edu LSQUnit *lsq_ptr) 412678Sktlim@umich.edu : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 422292SN/A{ 432678Sktlim@umich.edu this->setFlags(Event::AutoDelete); 442292SN/A} 452292SN/A 462669Sktlim@umich.edutemplate<class Impl> 472292SN/Avoid 482678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 492292SN/A{ 502678Sktlim@umich.edu if (!lsqPtr->isSwitchedOut()) { 512678Sktlim@umich.edu lsqPtr->writeback(inst, pkt); 522678Sktlim@umich.edu } 532678Sktlim@umich.edu delete pkt; 542678Sktlim@umich.edu} 552292SN/A 562678Sktlim@umich.edutemplate<class Impl> 572678Sktlim@umich.educonst char * 582678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::description() 592678Sktlim@umich.edu{ 602678Sktlim@umich.edu return "Store writeback event"; 612678Sktlim@umich.edu} 622292SN/A 632678Sktlim@umich.edutemplate<class Impl> 642678Sktlim@umich.eduvoid 652678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 662678Sktlim@umich.edu{ 672678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 682678Sktlim@umich.edu DynInstPtr inst = state->inst; 692678Sktlim@umich.edu DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum); 702698Sktlim@umich.edu DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum); 712344SN/A 722678Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 732678Sktlim@umich.edu 742678Sktlim@umich.edu if (isSwitchedOut() || inst->isSquashed()) { 752678Sktlim@umich.edu delete state; 762678Sktlim@umich.edu delete pkt; 772307SN/A return; 782678Sktlim@umich.edu } else { 792678Sktlim@umich.edu if (!state->noWB) { 802678Sktlim@umich.edu writeback(inst, pkt); 812678Sktlim@umich.edu } 822678Sktlim@umich.edu 832678Sktlim@umich.edu if (inst->isStore()) { 842678Sktlim@umich.edu completeStore(state->idx); 852678Sktlim@umich.edu } 862344SN/A } 872307SN/A 882678Sktlim@umich.edu delete state; 892678Sktlim@umich.edu delete pkt; 902292SN/A} 912292SN/A 922292SN/Atemplate <class Impl> 932669Sktlim@umich.eduTick 942669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvAtomic(PacketPtr pkt) 952292SN/A{ 962669Sktlim@umich.edu panic("O3CPU model does not work with atomic mode!"); 972669Sktlim@umich.edu return curTick; 982669Sktlim@umich.edu} 992669Sktlim@umich.edu 1002669Sktlim@umich.edutemplate <class Impl> 1012669Sktlim@umich.eduvoid 1022669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvFunctional(PacketPtr pkt) 1032669Sktlim@umich.edu{ 1042669Sktlim@umich.edu panic("O3CPU doesn't expect recvFunctional callback!"); 1052669Sktlim@umich.edu} 1062669Sktlim@umich.edu 1072669Sktlim@umich.edutemplate <class Impl> 1082669Sktlim@umich.eduvoid 1092669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvStatusChange(Status status) 1102669Sktlim@umich.edu{ 1112669Sktlim@umich.edu if (status == RangeChange) 1122669Sktlim@umich.edu return; 1132669Sktlim@umich.edu 1142669Sktlim@umich.edu panic("O3CPU doesn't expect recvStatusChange callback!"); 1152669Sktlim@umich.edu} 1162669Sktlim@umich.edu 1172669Sktlim@umich.edutemplate <class Impl> 1182669Sktlim@umich.edubool 1192669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvTiming(PacketPtr pkt) 1202669Sktlim@umich.edu{ 1212669Sktlim@umich.edu lsq->completeDataAccess(pkt); 1222669Sktlim@umich.edu return true; 1232669Sktlim@umich.edu} 1242669Sktlim@umich.edu 1252669Sktlim@umich.edutemplate <class Impl> 1262669Sktlim@umich.eduvoid 1272669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvRetry() 1282669Sktlim@umich.edu{ 1292693Sktlim@umich.edu lsq->recvRetry(); 1302292SN/A} 1312292SN/A 1322292SN/Atemplate <class Impl> 1332292SN/ALSQUnit<Impl>::LSQUnit() 1342678Sktlim@umich.edu : loads(0), stores(0), storesToWB(0), stalled(false), 1352678Sktlim@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1362292SN/A loadBlockedHandled(false) 1372292SN/A{ 1382292SN/A} 1392292SN/A 1402292SN/Atemplate<class Impl> 1412292SN/Avoid 1422292SN/ALSQUnit<Impl>::init(Params *params, unsigned maxLQEntries, 1432292SN/A unsigned maxSQEntries, unsigned id) 1442292SN/A{ 1452292SN/A DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1462292SN/A 1472307SN/A switchedOut = false; 1482307SN/A 1492292SN/A lsqID = id; 1502292SN/A 1512329SN/A // Add 1 for the sentinel entry (they are circular queues). 1522329SN/A LQEntries = maxLQEntries + 1; 1532329SN/A SQEntries = maxSQEntries + 1; 1542292SN/A 1552292SN/A loadQueue.resize(LQEntries); 1562292SN/A storeQueue.resize(SQEntries); 1572292SN/A 1582292SN/A loadHead = loadTail = 0; 1592292SN/A 1602292SN/A storeHead = storeWBIdx = storeTail = 0; 1612292SN/A 1622292SN/A usedPorts = 0; 1632292SN/A cachePorts = params->cachePorts; 1642292SN/A 1652678Sktlim@umich.edu mem = params->mem; 1662292SN/A 1672329SN/A memDepViolator = NULL; 1682292SN/A 1692292SN/A blockedLoadSeqNum = 0; 1702292SN/A} 1712292SN/A 1722292SN/Atemplate<class Impl> 1732669Sktlim@umich.eduvoid 1742669Sktlim@umich.eduLSQUnit<Impl>::setCPU(FullCPU *cpu_ptr) 1752669Sktlim@umich.edu{ 1762669Sktlim@umich.edu cpu = cpu_ptr; 1772669Sktlim@umich.edu dcachePort = new DcachePort(cpu, this); 1782678Sktlim@umich.edu 1792678Sktlim@umich.edu Port *mem_dport = mem->getPort(""); 1802678Sktlim@umich.edu dcachePort->setPeer(mem_dport); 1812678Sktlim@umich.edu mem_dport->setPeer(dcachePort); 1822679Sktlim@umich.edu 1832679Sktlim@umich.edu if (cpu->checker) { 1842679Sktlim@umich.edu cpu->checker->setDcachePort(dcachePort); 1852679Sktlim@umich.edu } 1862669Sktlim@umich.edu} 1872669Sktlim@umich.edu 1882669Sktlim@umich.edutemplate<class Impl> 1892292SN/Astd::string 1902292SN/ALSQUnit<Impl>::name() const 1912292SN/A{ 1922292SN/A if (Impl::MaxThreads == 1) { 1932292SN/A return iewStage->name() + ".lsq"; 1942292SN/A } else { 1952292SN/A return iewStage->name() + ".lsq.thread." + to_string(lsqID); 1962292SN/A } 1972292SN/A} 1982292SN/A 1992292SN/Atemplate<class Impl> 2002292SN/Avoid 2012292SN/ALSQUnit<Impl>::clearLQ() 2022292SN/A{ 2032292SN/A loadQueue.clear(); 2042292SN/A} 2052292SN/A 2062292SN/Atemplate<class Impl> 2072292SN/Avoid 2082292SN/ALSQUnit<Impl>::clearSQ() 2092292SN/A{ 2102292SN/A storeQueue.clear(); 2112292SN/A} 2122292SN/A 2132292SN/Atemplate<class Impl> 2142292SN/Avoid 2152307SN/ALSQUnit<Impl>::switchOut() 2162307SN/A{ 2172307SN/A switchedOut = true; 2182307SN/A for (int i = 0; i < loadQueue.size(); ++i) 2192307SN/A loadQueue[i] = NULL; 2202307SN/A 2212329SN/A assert(storesToWB == 0); 2222307SN/A} 2232307SN/A 2242307SN/Atemplate<class Impl> 2252307SN/Avoid 2262307SN/ALSQUnit<Impl>::takeOverFrom() 2272307SN/A{ 2282307SN/A switchedOut = false; 2292307SN/A loads = stores = storesToWB = 0; 2302307SN/A 2312307SN/A loadHead = loadTail = 0; 2322307SN/A 2332307SN/A storeHead = storeWBIdx = storeTail = 0; 2342307SN/A 2352307SN/A usedPorts = 0; 2362307SN/A 2372329SN/A memDepViolator = NULL; 2382307SN/A 2392307SN/A blockedLoadSeqNum = 0; 2402307SN/A 2412307SN/A stalled = false; 2422307SN/A isLoadBlocked = false; 2432307SN/A loadBlockedHandled = false; 2442307SN/A} 2452307SN/A 2462307SN/Atemplate<class Impl> 2472307SN/Avoid 2482292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 2492292SN/A{ 2502329SN/A unsigned size_plus_sentinel = size + 1; 2512329SN/A assert(size_plus_sentinel >= LQEntries); 2522292SN/A 2532329SN/A if (size_plus_sentinel > LQEntries) { 2542329SN/A while (size_plus_sentinel > loadQueue.size()) { 2552292SN/A DynInstPtr dummy; 2562292SN/A loadQueue.push_back(dummy); 2572292SN/A LQEntries++; 2582292SN/A } 2592292SN/A } else { 2602329SN/A LQEntries = size_plus_sentinel; 2612292SN/A } 2622292SN/A 2632292SN/A} 2642292SN/A 2652292SN/Atemplate<class Impl> 2662292SN/Avoid 2672292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 2682292SN/A{ 2692329SN/A unsigned size_plus_sentinel = size + 1; 2702329SN/A if (size_plus_sentinel > SQEntries) { 2712329SN/A while (size_plus_sentinel > storeQueue.size()) { 2722292SN/A SQEntry dummy; 2732292SN/A storeQueue.push_back(dummy); 2742292SN/A SQEntries++; 2752292SN/A } 2762292SN/A } else { 2772329SN/A SQEntries = size_plus_sentinel; 2782292SN/A } 2792292SN/A} 2802292SN/A 2812292SN/Atemplate <class Impl> 2822292SN/Avoid 2832292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 2842292SN/A{ 2852292SN/A assert(inst->isMemRef()); 2862292SN/A 2872292SN/A assert(inst->isLoad() || inst->isStore()); 2882292SN/A 2892292SN/A if (inst->isLoad()) { 2902292SN/A insertLoad(inst); 2912292SN/A } else { 2922292SN/A insertStore(inst); 2932292SN/A } 2942292SN/A 2952292SN/A inst->setInLSQ(); 2962292SN/A} 2972292SN/A 2982292SN/Atemplate <class Impl> 2992292SN/Avoid 3002292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3012292SN/A{ 3022329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3032329SN/A assert(loads < LQEntries); 3042292SN/A 3052292SN/A DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n", 3062292SN/A load_inst->readPC(), loadTail, load_inst->seqNum); 3072292SN/A 3082292SN/A load_inst->lqIdx = loadTail; 3092292SN/A 3102292SN/A if (stores == 0) { 3112292SN/A load_inst->sqIdx = -1; 3122292SN/A } else { 3132292SN/A load_inst->sqIdx = storeTail; 3142292SN/A } 3152292SN/A 3162292SN/A loadQueue[loadTail] = load_inst; 3172292SN/A 3182292SN/A incrLdIdx(loadTail); 3192292SN/A 3202292SN/A ++loads; 3212292SN/A} 3222292SN/A 3232292SN/Atemplate <class Impl> 3242292SN/Avoid 3252292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3262292SN/A{ 3272292SN/A // Make sure it is not full before inserting an instruction. 3282292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3292292SN/A assert(stores < SQEntries); 3302292SN/A 3312292SN/A DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n", 3322292SN/A store_inst->readPC(), storeTail, store_inst->seqNum); 3332292SN/A 3342292SN/A store_inst->sqIdx = storeTail; 3352292SN/A store_inst->lqIdx = loadTail; 3362292SN/A 3372292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3382292SN/A 3392292SN/A incrStIdx(storeTail); 3402292SN/A 3412292SN/A ++stores; 3422292SN/A} 3432292SN/A 3442292SN/Atemplate <class Impl> 3452292SN/Atypename Impl::DynInstPtr 3462292SN/ALSQUnit<Impl>::getMemDepViolator() 3472292SN/A{ 3482292SN/A DynInstPtr temp = memDepViolator; 3492292SN/A 3502292SN/A memDepViolator = NULL; 3512292SN/A 3522292SN/A return temp; 3532292SN/A} 3542292SN/A 3552292SN/Atemplate <class Impl> 3562292SN/Aunsigned 3572292SN/ALSQUnit<Impl>::numFreeEntries() 3582292SN/A{ 3592292SN/A unsigned free_lq_entries = LQEntries - loads; 3602292SN/A unsigned free_sq_entries = SQEntries - stores; 3612292SN/A 3622292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 3632292SN/A // empty/full conditions. Subtract 1 from the free entries. 3642292SN/A if (free_lq_entries < free_sq_entries) { 3652292SN/A return free_lq_entries - 1; 3662292SN/A } else { 3672292SN/A return free_sq_entries - 1; 3682292SN/A } 3692292SN/A} 3702292SN/A 3712292SN/Atemplate <class Impl> 3722292SN/Aint 3732292SN/ALSQUnit<Impl>::numLoadsReady() 3742292SN/A{ 3752292SN/A int load_idx = loadHead; 3762292SN/A int retval = 0; 3772292SN/A 3782292SN/A while (load_idx != loadTail) { 3792292SN/A assert(loadQueue[load_idx]); 3802292SN/A 3812292SN/A if (loadQueue[load_idx]->readyToIssue()) { 3822292SN/A ++retval; 3832292SN/A } 3842292SN/A } 3852292SN/A 3862292SN/A return retval; 3872292SN/A} 3882292SN/A 3892292SN/Atemplate <class Impl> 3902292SN/AFault 3912292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 3922292SN/A{ 3932292SN/A // Execute a specific load. 3942292SN/A Fault load_fault = NoFault; 3952292SN/A 3962292SN/A DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n", 3972292SN/A inst->readPC(),inst->seqNum); 3982292SN/A 3992669Sktlim@umich.edu load_fault = inst->initiateAcc(); 4002292SN/A 4012292SN/A // If the instruction faulted, then we need to send it along to commit 4022292SN/A // without the instruction completing. 4032292SN/A if (load_fault != NoFault) { 4042329SN/A // Send this instruction to commit, also make sure iew stage 4052329SN/A // realizes there is activity. 4062292SN/A iewStage->instToCommit(inst); 4072292SN/A iewStage->activityThisCycle(); 4082292SN/A } 4092292SN/A 4102292SN/A return load_fault; 4112292SN/A} 4122292SN/A 4132292SN/Atemplate <class Impl> 4142292SN/AFault 4152292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 4162292SN/A{ 4172292SN/A using namespace TheISA; 4182292SN/A // Make sure that a store exists. 4192292SN/A assert(stores != 0); 4202292SN/A 4212292SN/A int store_idx = store_inst->sqIdx; 4222292SN/A 4232292SN/A DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n", 4242292SN/A store_inst->readPC(), store_inst->seqNum); 4252292SN/A 4262292SN/A // Check the recently completed loads to see if any match this store's 4272292SN/A // address. If so, then we have a memory ordering violation. 4282292SN/A int load_idx = store_inst->lqIdx; 4292292SN/A 4302292SN/A Fault store_fault = store_inst->initiateAcc(); 4312292SN/A 4322329SN/A if (storeQueue[store_idx].size == 0) { 4332292SN/A DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n", 4342292SN/A store_inst->readPC(),store_inst->seqNum); 4352292SN/A 4362292SN/A return store_fault; 4372292SN/A } 4382292SN/A 4392292SN/A assert(store_fault == NoFault); 4402292SN/A 4412336SN/A if (store_inst->isStoreConditional()) { 4422336SN/A // Store conditionals need to set themselves as able to 4432336SN/A // writeback if we haven't had a fault by here. 4442329SN/A storeQueue[store_idx].canWB = true; 4452292SN/A 4462329SN/A ++storesToWB; 4472292SN/A } 4482292SN/A 4492292SN/A if (!memDepViolator) { 4502292SN/A while (load_idx != loadTail) { 4512329SN/A // Really only need to check loads that have actually executed 4522329SN/A // It's safe to check all loads because effAddr is set to 4532329SN/A // InvalAddr when the dyn inst is created. 4542292SN/A 4552329SN/A // @todo: For now this is extra conservative, detecting a 4562329SN/A // violation if the addresses match assuming all accesses 4572329SN/A // are quad word accesses. 4582329SN/A 4592292SN/A // @todo: Fix this, magic number being used here 4602292SN/A if ((loadQueue[load_idx]->effAddr >> 8) == 4612292SN/A (store_inst->effAddr >> 8)) { 4622292SN/A // A load incorrectly passed this store. Squash and refetch. 4632292SN/A // For now return a fault to show that it was unsuccessful. 4642292SN/A memDepViolator = loadQueue[load_idx]; 4652292SN/A 4662292SN/A return genMachineCheckFault(); 4672292SN/A } 4682292SN/A 4692292SN/A incrLdIdx(load_idx); 4702292SN/A } 4712292SN/A 4722292SN/A // If we've reached this point, there was no violation. 4732292SN/A memDepViolator = NULL; 4742292SN/A } 4752292SN/A 4762292SN/A return store_fault; 4772292SN/A} 4782292SN/A 4792292SN/Atemplate <class Impl> 4802292SN/Avoid 4812292SN/ALSQUnit<Impl>::commitLoad() 4822292SN/A{ 4832292SN/A assert(loadQueue[loadHead]); 4842292SN/A 4852292SN/A DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n", 4862292SN/A loadQueue[loadHead]->readPC()); 4872292SN/A 4882292SN/A loadQueue[loadHead] = NULL; 4892292SN/A 4902292SN/A incrLdIdx(loadHead); 4912292SN/A 4922292SN/A --loads; 4932292SN/A} 4942292SN/A 4952292SN/Atemplate <class Impl> 4962292SN/Avoid 4972292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 4982292SN/A{ 4992292SN/A assert(loads == 0 || loadQueue[loadHead]); 5002292SN/A 5012292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 5022292SN/A commitLoad(); 5032292SN/A } 5042292SN/A} 5052292SN/A 5062292SN/Atemplate <class Impl> 5072292SN/Avoid 5082292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 5092292SN/A{ 5102292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 5112292SN/A 5122292SN/A int store_idx = storeHead; 5132292SN/A 5142292SN/A while (store_idx != storeTail) { 5152292SN/A assert(storeQueue[store_idx].inst); 5162329SN/A // Mark any stores that are now committed and have not yet 5172329SN/A // been marked as able to write back. 5182292SN/A if (!storeQueue[store_idx].canWB) { 5192292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 5202292SN/A break; 5212292SN/A } 5222292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 5232292SN/A "%#x [sn:%lli]\n", 5242292SN/A storeQueue[store_idx].inst->readPC(), 5252292SN/A storeQueue[store_idx].inst->seqNum); 5262292SN/A 5272292SN/A storeQueue[store_idx].canWB = true; 5282292SN/A 5292292SN/A ++storesToWB; 5302292SN/A } 5312292SN/A 5322292SN/A incrStIdx(store_idx); 5332292SN/A } 5342292SN/A} 5352292SN/A 5362292SN/Atemplate <class Impl> 5372292SN/Avoid 5382292SN/ALSQUnit<Impl>::writebackStores() 5392292SN/A{ 5402292SN/A while (storesToWB > 0 && 5412292SN/A storeWBIdx != storeTail && 5422292SN/A storeQueue[storeWBIdx].inst && 5432292SN/A storeQueue[storeWBIdx].canWB && 5442292SN/A usedPorts < cachePorts) { 5452292SN/A 5462678Sktlim@umich.edu if (isStoreBlocked) { 5472678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 5482678Sktlim@umich.edu " is blocked!\n"); 5492678Sktlim@umich.edu break; 5502678Sktlim@umich.edu } 5512678Sktlim@umich.edu 5522329SN/A // Store didn't write any data so no need to write it back to 5532329SN/A // memory. 5542292SN/A if (storeQueue[storeWBIdx].size == 0) { 5552292SN/A completeStore(storeWBIdx); 5562292SN/A 5572292SN/A incrStIdx(storeWBIdx); 5582292SN/A 5592292SN/A continue; 5602292SN/A } 5612678Sktlim@umich.edu 5622292SN/A ++usedPorts; 5632292SN/A 5642292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 5652292SN/A incrStIdx(storeWBIdx); 5662292SN/A 5672292SN/A continue; 5682292SN/A } 5692292SN/A 5702292SN/A assert(storeQueue[storeWBIdx].req); 5712292SN/A assert(!storeQueue[storeWBIdx].committed); 5722292SN/A 5732669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 5742669Sktlim@umich.edu 5752669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 5762292SN/A storeQueue[storeWBIdx].committed = true; 5772292SN/A 5782669Sktlim@umich.edu assert(!inst->memData); 5792669Sktlim@umich.edu inst->memData = new uint8_t[64]; 5802678Sktlim@umich.edu memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data, 5812678Sktlim@umich.edu req->getSize()); 5822669Sktlim@umich.edu 5832669Sktlim@umich.edu PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 5842669Sktlim@umich.edu data_pkt->dataStatic(inst->memData); 5852292SN/A 5862678Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 5872678Sktlim@umich.edu state->isLoad = false; 5882678Sktlim@umich.edu state->idx = storeWBIdx; 5892678Sktlim@umich.edu state->inst = inst; 5902678Sktlim@umich.edu data_pkt->senderState = state; 5912678Sktlim@umich.edu 5922292SN/A DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " 5932292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 5942669Sktlim@umich.edu storeWBIdx, storeQueue[storeWBIdx].inst->readPC(), 5952669Sktlim@umich.edu req->getPaddr(), *(inst->memData), 5962292SN/A storeQueue[storeWBIdx].inst->seqNum); 5972292SN/A 5982693Sktlim@umich.edu // @todo: Remove this SC hack once the memory system handles it. 5992693Sktlim@umich.edu if (req->getFlags() & LOCKED) { 6002693Sktlim@umich.edu if (req->getFlags() & UNCACHEABLE) { 6012693Sktlim@umich.edu req->setScResult(2); 6022693Sktlim@umich.edu } else { 6032693Sktlim@umich.edu if (cpu->lockFlag) { 6042693Sktlim@umich.edu req->setScResult(1); 6052693Sktlim@umich.edu } else { 6062693Sktlim@umich.edu req->setScResult(0); 6072693Sktlim@umich.edu // Hack: Instantly complete this store. 6082693Sktlim@umich.edu completeDataAccess(data_pkt); 6092693Sktlim@umich.edu incrStIdx(storeWBIdx); 6102693Sktlim@umich.edu continue; 6112693Sktlim@umich.edu } 6122693Sktlim@umich.edu } 6132693Sktlim@umich.edu } else { 6142693Sktlim@umich.edu // Non-store conditionals do not need a writeback. 6152693Sktlim@umich.edu state->noWB = true; 6162693Sktlim@umich.edu } 6172693Sktlim@umich.edu 6182669Sktlim@umich.edu if (!dcachePort->sendTiming(data_pkt)) { 6192669Sktlim@umich.edu // Need to handle becoming blocked on a store. 6202678Sktlim@umich.edu isStoreBlocked = true; 6212693Sktlim@umich.edu 6222698Sktlim@umich.edu assert(retryPkt == NULL); 6232698Sktlim@umich.edu retryPkt = data_pkt; 6242669Sktlim@umich.edu } else { 6252693Sktlim@umich.edu storePostSend(data_pkt); 6262292SN/A } 6272292SN/A } 6282292SN/A 6292292SN/A // Not sure this should set it to 0. 6302292SN/A usedPorts = 0; 6312292SN/A 6322292SN/A assert(stores >= 0 && storesToWB >= 0); 6332292SN/A} 6342292SN/A 6352292SN/A/*template <class Impl> 6362292SN/Avoid 6372292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 6382292SN/A{ 6392292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 6402292SN/A mshrSeqNums.end(), 6412292SN/A seqNum); 6422292SN/A 6432292SN/A if (mshr_it != mshrSeqNums.end()) { 6442292SN/A mshrSeqNums.erase(mshr_it); 6452292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 6462292SN/A } 6472292SN/A}*/ 6482292SN/A 6492292SN/Atemplate <class Impl> 6502292SN/Avoid 6512292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 6522292SN/A{ 6532292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 6542329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 6552292SN/A 6562292SN/A int load_idx = loadTail; 6572292SN/A decrLdIdx(load_idx); 6582292SN/A 6592292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 6602292SN/A DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, " 6612292SN/A "[sn:%lli]\n", 6622292SN/A loadQueue[load_idx]->readPC(), 6632292SN/A loadQueue[load_idx]->seqNum); 6642292SN/A 6652292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 6662292SN/A stalled = false; 6672292SN/A stallingStoreIsn = 0; 6682292SN/A stallingLoadIdx = 0; 6692292SN/A } 6702292SN/A 6712329SN/A // Clear the smart pointer to make sure it is decremented. 6722292SN/A loadQueue[load_idx]->squashed = true; 6732292SN/A loadQueue[load_idx] = NULL; 6742292SN/A --loads; 6752292SN/A 6762292SN/A // Inefficient! 6772292SN/A loadTail = load_idx; 6782292SN/A 6792292SN/A decrLdIdx(load_idx); 6802292SN/A } 6812292SN/A 6822292SN/A if (isLoadBlocked) { 6832292SN/A if (squashed_num < blockedLoadSeqNum) { 6842292SN/A isLoadBlocked = false; 6852292SN/A loadBlockedHandled = false; 6862292SN/A blockedLoadSeqNum = 0; 6872292SN/A } 6882292SN/A } 6892292SN/A 6902292SN/A int store_idx = storeTail; 6912292SN/A decrStIdx(store_idx); 6922292SN/A 6932292SN/A while (stores != 0 && 6942292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 6952329SN/A // Instructions marked as can WB are already committed. 6962292SN/A if (storeQueue[store_idx].canWB) { 6972292SN/A break; 6982292SN/A } 6992292SN/A 7002292SN/A DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, " 7012292SN/A "idx:%i [sn:%lli]\n", 7022292SN/A storeQueue[store_idx].inst->readPC(), 7032292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 7042292SN/A 7052329SN/A // I don't think this can happen. It should have been cleared 7062329SN/A // by the stalling load. 7072292SN/A if (isStalled() && 7082292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 7092292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 7102292SN/A stalled = false; 7112292SN/A stallingStoreIsn = 0; 7122292SN/A } 7132292SN/A 7142329SN/A // Clear the smart pointer to make sure it is decremented. 7152292SN/A storeQueue[store_idx].inst->squashed = true; 7162292SN/A storeQueue[store_idx].inst = NULL; 7172292SN/A storeQueue[store_idx].canWB = 0; 7182292SN/A 7192292SN/A storeQueue[store_idx].req = NULL; 7202292SN/A --stores; 7212292SN/A 7222292SN/A // Inefficient! 7232292SN/A storeTail = store_idx; 7242292SN/A 7252292SN/A decrStIdx(store_idx); 7262292SN/A } 7272292SN/A} 7282292SN/A 7292292SN/Atemplate <class Impl> 7302292SN/Avoid 7312693Sktlim@umich.eduLSQUnit<Impl>::storePostSend(Packet *pkt) 7322693Sktlim@umich.edu{ 7332693Sktlim@umich.edu if (isStalled() && 7342693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 7352693Sktlim@umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 7362693Sktlim@umich.edu "load idx:%i\n", 7372693Sktlim@umich.edu stallingStoreIsn, stallingLoadIdx); 7382693Sktlim@umich.edu stalled = false; 7392693Sktlim@umich.edu stallingStoreIsn = 0; 7402693Sktlim@umich.edu iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 7412693Sktlim@umich.edu } 7422693Sktlim@umich.edu 7432693Sktlim@umich.edu if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 7442693Sktlim@umich.edu // The store is basically completed at this time. This 7452693Sktlim@umich.edu // only works so long as the checker doesn't try to 7462693Sktlim@umich.edu // verify the value in memory for stores. 7472693Sktlim@umich.edu storeQueue[storeWBIdx].inst->setCompleted(); 7482693Sktlim@umich.edu if (cpu->checker) { 7492693Sktlim@umich.edu cpu->checker->tick(storeQueue[storeWBIdx].inst); 7502693Sktlim@umich.edu } 7512693Sktlim@umich.edu } 7522693Sktlim@umich.edu 7532693Sktlim@umich.edu if (pkt->result != Packet::Success) { 7542693Sktlim@umich.edu DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n", 7552693Sktlim@umich.edu storeWBIdx); 7562693Sktlim@umich.edu 7572693Sktlim@umich.edu DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n", 7582693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum); 7592693Sktlim@umich.edu 7602693Sktlim@umich.edu //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum); 7612693Sktlim@umich.edu 7622693Sktlim@umich.edu //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size()); 7632693Sktlim@umich.edu 7642693Sktlim@umich.edu // @todo: Increment stat here. 7652693Sktlim@umich.edu } else { 7662693Sktlim@umich.edu DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n", 7672693Sktlim@umich.edu storeWBIdx); 7682693Sktlim@umich.edu 7692693Sktlim@umich.edu DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", 7702693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum); 7712693Sktlim@umich.edu } 7722693Sktlim@umich.edu 7732693Sktlim@umich.edu incrStIdx(storeWBIdx); 7742693Sktlim@umich.edu} 7752693Sktlim@umich.edu 7762693Sktlim@umich.edutemplate <class Impl> 7772693Sktlim@umich.eduvoid 7782678Sktlim@umich.eduLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 7792678Sktlim@umich.edu{ 7802678Sktlim@umich.edu iewStage->wakeCPU(); 7812678Sktlim@umich.edu 7822678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 7832678Sktlim@umich.edu if (inst->isSquashed()) { 7842678Sktlim@umich.edu assert(!inst->isStore()); 7852678Sktlim@umich.edu return; 7862678Sktlim@umich.edu } 7872678Sktlim@umich.edu 7882678Sktlim@umich.edu if (!inst->isExecuted()) { 7892678Sktlim@umich.edu inst->setExecuted(); 7902678Sktlim@umich.edu 7912678Sktlim@umich.edu // Complete access to copy data to proper place. 7922678Sktlim@umich.edu inst->completeAcc(pkt); 7932678Sktlim@umich.edu } 7942678Sktlim@umich.edu 7952678Sktlim@umich.edu // Need to insert instruction into queue to commit 7962678Sktlim@umich.edu iewStage->instToCommit(inst); 7972678Sktlim@umich.edu 7982678Sktlim@umich.edu iewStage->activityThisCycle(); 7992678Sktlim@umich.edu} 8002678Sktlim@umich.edu 8012678Sktlim@umich.edutemplate <class Impl> 8022678Sktlim@umich.eduvoid 8032292SN/ALSQUnit<Impl>::completeStore(int store_idx) 8042292SN/A{ 8052292SN/A assert(storeQueue[store_idx].inst); 8062292SN/A storeQueue[store_idx].completed = true; 8072292SN/A --storesToWB; 8082292SN/A // A bit conservative because a store completion may not free up entries, 8092292SN/A // but hopefully avoids two store completions in one cycle from making 8102292SN/A // the CPU tick twice. 8112292SN/A cpu->activityThisCycle(); 8122292SN/A 8132292SN/A if (store_idx == storeHead) { 8142292SN/A do { 8152292SN/A incrStIdx(storeHead); 8162292SN/A 8172292SN/A --stores; 8182292SN/A } while (storeQueue[storeHead].completed && 8192292SN/A storeHead != storeTail); 8202292SN/A 8212292SN/A iewStage->updateLSQNextCycle = true; 8222292SN/A } 8232292SN/A 8242329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 8252329SN/A "idx:%i\n", 8262329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 8272292SN/A 8282292SN/A if (isStalled() && 8292292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 8302292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 8312292SN/A "load idx:%i\n", 8322292SN/A stallingStoreIsn, stallingLoadIdx); 8332292SN/A stalled = false; 8342292SN/A stallingStoreIsn = 0; 8352292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 8362292SN/A } 8372316SN/A 8382316SN/A storeQueue[store_idx].inst->setCompleted(); 8392329SN/A 8402329SN/A // Tell the checker we've completed this instruction. Some stores 8412329SN/A // may get reported twice to the checker, but the checker can 8422329SN/A // handle that case. 8432316SN/A if (cpu->checker) { 8442316SN/A cpu->checker->tick(storeQueue[store_idx].inst); 8452316SN/A } 8462292SN/A} 8472292SN/A 8482292SN/Atemplate <class Impl> 8492693Sktlim@umich.eduvoid 8502693Sktlim@umich.eduLSQUnit<Impl>::recvRetry() 8512693Sktlim@umich.edu{ 8522698Sktlim@umich.edu if (isStoreBlocked) { 8532698Sktlim@umich.edu assert(retryPkt != NULL); 8542693Sktlim@umich.edu 8552698Sktlim@umich.edu if (dcachePort->sendTiming(retryPkt)) { 8562698Sktlim@umich.edu storePostSend(retryPkt); 8572699Sktlim@umich.edu retryPkt = NULL; 8582693Sktlim@umich.edu isStoreBlocked = false; 8592693Sktlim@umich.edu } else { 8602693Sktlim@umich.edu // Still blocked! 8612693Sktlim@umich.edu } 8622693Sktlim@umich.edu } else if (isLoadBlocked) { 8632693Sktlim@umich.edu DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 8642693Sktlim@umich.edu "no need to resend packet.\n"); 8652693Sktlim@umich.edu } else { 8662693Sktlim@umich.edu DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 8672693Sktlim@umich.edu } 8682693Sktlim@umich.edu} 8692693Sktlim@umich.edu 8702693Sktlim@umich.edutemplate <class Impl> 8712292SN/Ainline void 8722292SN/ALSQUnit<Impl>::incrStIdx(int &store_idx) 8732292SN/A{ 8742292SN/A if (++store_idx >= SQEntries) 8752292SN/A store_idx = 0; 8762292SN/A} 8772292SN/A 8782292SN/Atemplate <class Impl> 8792292SN/Ainline void 8802292SN/ALSQUnit<Impl>::decrStIdx(int &store_idx) 8812292SN/A{ 8822292SN/A if (--store_idx < 0) 8832292SN/A store_idx += SQEntries; 8842292SN/A} 8852292SN/A 8862292SN/Atemplate <class Impl> 8872292SN/Ainline void 8882292SN/ALSQUnit<Impl>::incrLdIdx(int &load_idx) 8892292SN/A{ 8902292SN/A if (++load_idx >= LQEntries) 8912292SN/A load_idx = 0; 8922292SN/A} 8932292SN/A 8942292SN/Atemplate <class Impl> 8952292SN/Ainline void 8962292SN/ALSQUnit<Impl>::decrLdIdx(int &load_idx) 8972292SN/A{ 8982292SN/A if (--load_idx < 0) 8992292SN/A load_idx += LQEntries; 9002292SN/A} 9012329SN/A 9022329SN/Atemplate <class Impl> 9032329SN/Avoid 9042329SN/ALSQUnit<Impl>::dumpInsts() 9052329SN/A{ 9062329SN/A cprintf("Load store queue: Dumping instructions.\n"); 9072329SN/A cprintf("Load queue size: %i\n", loads); 9082329SN/A cprintf("Load queue: "); 9092329SN/A 9102329SN/A int load_idx = loadHead; 9112329SN/A 9122329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 9132329SN/A cprintf("%#x ", loadQueue[load_idx]->readPC()); 9142329SN/A 9152329SN/A incrLdIdx(load_idx); 9162329SN/A } 9172329SN/A 9182329SN/A cprintf("Store queue size: %i\n", stores); 9192329SN/A cprintf("Store queue: "); 9202329SN/A 9212329SN/A int store_idx = storeHead; 9222329SN/A 9232329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 9242329SN/A cprintf("%#x ", storeQueue[store_idx].inst->readPC()); 9252329SN/A 9262329SN/A incrStIdx(store_idx); 9272329SN/A } 9282329SN/A 9292329SN/A cprintf("\n"); 9302329SN/A} 931