lsq_unit_impl.hh revision 2689
12292SN/A/* 22292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32292SN/A * All rights reserved. 42292SN/A * 52292SN/A * Redistribution and use in source and binary forms, with or without 62292SN/A * modification, are permitted provided that the following conditions are 72292SN/A * met: redistributions of source code must retain the above copyright 82292SN/A * notice, this list of conditions and the following disclaimer; 92292SN/A * redistributions in binary form must reproduce the above copyright 102292SN/A * notice, this list of conditions and the following disclaimer in the 112292SN/A * documentation and/or other materials provided with the distribution; 122292SN/A * neither the name of the copyright holders nor the names of its 132292SN/A * contributors may be used to endorse or promote products derived from 142292SN/A * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292689Sktlim@umich.edu * Korey Sewell 302292SN/A */ 312292SN/A 322316SN/A#include "cpu/checker/cpu.hh" 332292SN/A#include "cpu/o3/lsq_unit.hh" 342292SN/A#include "base/str.hh" 352669Sktlim@umich.edu#include "mem/request.hh" 362292SN/A 372669Sktlim@umich.edutemplate<class Impl> 382678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 392678Sktlim@umich.edu LSQUnit *lsq_ptr) 402678Sktlim@umich.edu : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 412292SN/A{ 422678Sktlim@umich.edu this->setFlags(Event::AutoDelete); 432292SN/A} 442292SN/A 452669Sktlim@umich.edutemplate<class Impl> 462292SN/Avoid 472678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 482292SN/A{ 492678Sktlim@umich.edu if (!lsqPtr->isSwitchedOut()) { 502678Sktlim@umich.edu lsqPtr->writeback(inst, pkt); 512678Sktlim@umich.edu } 522678Sktlim@umich.edu delete pkt; 532678Sktlim@umich.edu} 542292SN/A 552678Sktlim@umich.edutemplate<class Impl> 562678Sktlim@umich.educonst char * 572678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::description() 582678Sktlim@umich.edu{ 592678Sktlim@umich.edu return "Store writeback event"; 602678Sktlim@umich.edu} 612292SN/A 622678Sktlim@umich.edutemplate<class Impl> 632678Sktlim@umich.eduvoid 642678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 652678Sktlim@umich.edu{ 662678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 672678Sktlim@umich.edu DynInstPtr inst = state->inst; 682678Sktlim@umich.edu DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum); 692678Sktlim@umich.edu// DPRINTF(Activity, "Activity: Ld Writeback event [sn:%lli]\n", inst->seqNum); 702344SN/A 712678Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 722678Sktlim@umich.edu 732678Sktlim@umich.edu if (isSwitchedOut() || inst->isSquashed()) { 742678Sktlim@umich.edu delete state; 752678Sktlim@umich.edu delete pkt; 762307SN/A return; 772678Sktlim@umich.edu } else { 782678Sktlim@umich.edu if (!state->noWB) { 792678Sktlim@umich.edu writeback(inst, pkt); 802678Sktlim@umich.edu } 812678Sktlim@umich.edu 822678Sktlim@umich.edu if (inst->isStore()) { 832678Sktlim@umich.edu completeStore(state->idx); 842678Sktlim@umich.edu } 852344SN/A } 862307SN/A 872678Sktlim@umich.edu delete state; 882678Sktlim@umich.edu delete pkt; 892292SN/A} 902292SN/A 912292SN/Atemplate <class Impl> 922669Sktlim@umich.eduTick 932669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvAtomic(PacketPtr pkt) 942292SN/A{ 952669Sktlim@umich.edu panic("O3CPU model does not work with atomic mode!"); 962669Sktlim@umich.edu return curTick; 972669Sktlim@umich.edu} 982669Sktlim@umich.edu 992669Sktlim@umich.edutemplate <class Impl> 1002669Sktlim@umich.eduvoid 1012669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvFunctional(PacketPtr pkt) 1022669Sktlim@umich.edu{ 1032669Sktlim@umich.edu panic("O3CPU doesn't expect recvFunctional callback!"); 1042669Sktlim@umich.edu} 1052669Sktlim@umich.edu 1062669Sktlim@umich.edutemplate <class Impl> 1072669Sktlim@umich.eduvoid 1082669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvStatusChange(Status status) 1092669Sktlim@umich.edu{ 1102669Sktlim@umich.edu if (status == RangeChange) 1112669Sktlim@umich.edu return; 1122669Sktlim@umich.edu 1132669Sktlim@umich.edu panic("O3CPU doesn't expect recvStatusChange callback!"); 1142669Sktlim@umich.edu} 1152669Sktlim@umich.edu 1162669Sktlim@umich.edutemplate <class Impl> 1172669Sktlim@umich.edubool 1182669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvTiming(PacketPtr pkt) 1192669Sktlim@umich.edu{ 1202669Sktlim@umich.edu lsq->completeDataAccess(pkt); 1212669Sktlim@umich.edu return true; 1222669Sktlim@umich.edu} 1232669Sktlim@umich.edu 1242669Sktlim@umich.edutemplate <class Impl> 1252669Sktlim@umich.eduvoid 1262669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvRetry() 1272669Sktlim@umich.edu{ 1282669Sktlim@umich.edu panic("Retry unsupported for now!"); 1292669Sktlim@umich.edu // we shouldn't get a retry unless we have a packet that we're 1302669Sktlim@umich.edu // waiting to transmit 1312669Sktlim@umich.edu/* 1322669Sktlim@umich.edu assert(cpu->dcache_pkt != NULL); 1332669Sktlim@umich.edu assert(cpu->_status == DcacheRetry); 1342669Sktlim@umich.edu PacketPtr tmp = cpu->dcache_pkt; 1352669Sktlim@umich.edu if (sendTiming(tmp)) { 1362669Sktlim@umich.edu cpu->_status = DcacheWaitResponse; 1372669Sktlim@umich.edu cpu->dcache_pkt = NULL; 1382669Sktlim@umich.edu } 1392669Sktlim@umich.edu*/ 1402292SN/A} 1412292SN/A 1422292SN/Atemplate <class Impl> 1432292SN/ALSQUnit<Impl>::LSQUnit() 1442678Sktlim@umich.edu : loads(0), stores(0), storesToWB(0), stalled(false), 1452678Sktlim@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1462292SN/A loadBlockedHandled(false) 1472292SN/A{ 1482292SN/A} 1492292SN/A 1502292SN/Atemplate<class Impl> 1512292SN/Avoid 1522292SN/ALSQUnit<Impl>::init(Params *params, unsigned maxLQEntries, 1532292SN/A unsigned maxSQEntries, unsigned id) 1542292SN/A{ 1552292SN/A DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1562292SN/A 1572307SN/A switchedOut = false; 1582307SN/A 1592292SN/A lsqID = id; 1602292SN/A 1612329SN/A // Add 1 for the sentinel entry (they are circular queues). 1622329SN/A LQEntries = maxLQEntries + 1; 1632329SN/A SQEntries = maxSQEntries + 1; 1642292SN/A 1652292SN/A loadQueue.resize(LQEntries); 1662292SN/A storeQueue.resize(SQEntries); 1672292SN/A 1682292SN/A loadHead = loadTail = 0; 1692292SN/A 1702292SN/A storeHead = storeWBIdx = storeTail = 0; 1712292SN/A 1722292SN/A usedPorts = 0; 1732292SN/A cachePorts = params->cachePorts; 1742292SN/A 1752678Sktlim@umich.edu mem = params->mem; 1762292SN/A 1772329SN/A memDepViolator = NULL; 1782292SN/A 1792292SN/A blockedLoadSeqNum = 0; 1802292SN/A} 1812292SN/A 1822292SN/Atemplate<class Impl> 1832669Sktlim@umich.eduvoid 1842669Sktlim@umich.eduLSQUnit<Impl>::setCPU(FullCPU *cpu_ptr) 1852669Sktlim@umich.edu{ 1862669Sktlim@umich.edu cpu = cpu_ptr; 1872669Sktlim@umich.edu dcachePort = new DcachePort(cpu, this); 1882678Sktlim@umich.edu 1892678Sktlim@umich.edu Port *mem_dport = mem->getPort(""); 1902678Sktlim@umich.edu dcachePort->setPeer(mem_dport); 1912678Sktlim@umich.edu mem_dport->setPeer(dcachePort); 1922679Sktlim@umich.edu 1932679Sktlim@umich.edu if (cpu->checker) { 1942679Sktlim@umich.edu cpu->checker->setDcachePort(dcachePort); 1952679Sktlim@umich.edu } 1962669Sktlim@umich.edu} 1972669Sktlim@umich.edu 1982669Sktlim@umich.edutemplate<class Impl> 1992292SN/Astd::string 2002292SN/ALSQUnit<Impl>::name() const 2012292SN/A{ 2022292SN/A if (Impl::MaxThreads == 1) { 2032292SN/A return iewStage->name() + ".lsq"; 2042292SN/A } else { 2052292SN/A return iewStage->name() + ".lsq.thread." + to_string(lsqID); 2062292SN/A } 2072292SN/A} 2082292SN/A 2092292SN/Atemplate<class Impl> 2102292SN/Avoid 2112292SN/ALSQUnit<Impl>::clearLQ() 2122292SN/A{ 2132292SN/A loadQueue.clear(); 2142292SN/A} 2152292SN/A 2162292SN/Atemplate<class Impl> 2172292SN/Avoid 2182292SN/ALSQUnit<Impl>::clearSQ() 2192292SN/A{ 2202292SN/A storeQueue.clear(); 2212292SN/A} 2222292SN/A 2232292SN/A#if 0 2242292SN/Atemplate<class Impl> 2252292SN/Avoid 2262292SN/ALSQUnit<Impl>::setPageTable(PageTable *pt_ptr) 2272292SN/A{ 2282292SN/A DPRINTF(LSQUnit, "Setting the page table pointer.\n"); 2292292SN/A pTable = pt_ptr; 2302292SN/A} 2312292SN/A#endif 2322292SN/A 2332292SN/Atemplate<class Impl> 2342292SN/Avoid 2352307SN/ALSQUnit<Impl>::switchOut() 2362307SN/A{ 2372307SN/A switchedOut = true; 2382307SN/A for (int i = 0; i < loadQueue.size(); ++i) 2392307SN/A loadQueue[i] = NULL; 2402307SN/A 2412329SN/A assert(storesToWB == 0); 2422307SN/A} 2432307SN/A 2442307SN/Atemplate<class Impl> 2452307SN/Avoid 2462307SN/ALSQUnit<Impl>::takeOverFrom() 2472307SN/A{ 2482307SN/A switchedOut = false; 2492307SN/A loads = stores = storesToWB = 0; 2502307SN/A 2512307SN/A loadHead = loadTail = 0; 2522307SN/A 2532307SN/A storeHead = storeWBIdx = storeTail = 0; 2542307SN/A 2552307SN/A usedPorts = 0; 2562307SN/A 2572329SN/A memDepViolator = NULL; 2582307SN/A 2592307SN/A blockedLoadSeqNum = 0; 2602307SN/A 2612307SN/A stalled = false; 2622307SN/A isLoadBlocked = false; 2632307SN/A loadBlockedHandled = false; 2642307SN/A} 2652307SN/A 2662307SN/Atemplate<class Impl> 2672307SN/Avoid 2682292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 2692292SN/A{ 2702329SN/A unsigned size_plus_sentinel = size + 1; 2712329SN/A assert(size_plus_sentinel >= LQEntries); 2722292SN/A 2732329SN/A if (size_plus_sentinel > LQEntries) { 2742329SN/A while (size_plus_sentinel > loadQueue.size()) { 2752292SN/A DynInstPtr dummy; 2762292SN/A loadQueue.push_back(dummy); 2772292SN/A LQEntries++; 2782292SN/A } 2792292SN/A } else { 2802329SN/A LQEntries = size_plus_sentinel; 2812292SN/A } 2822292SN/A 2832292SN/A} 2842292SN/A 2852292SN/Atemplate<class Impl> 2862292SN/Avoid 2872292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 2882292SN/A{ 2892329SN/A unsigned size_plus_sentinel = size + 1; 2902329SN/A if (size_plus_sentinel > SQEntries) { 2912329SN/A while (size_plus_sentinel > storeQueue.size()) { 2922292SN/A SQEntry dummy; 2932292SN/A storeQueue.push_back(dummy); 2942292SN/A SQEntries++; 2952292SN/A } 2962292SN/A } else { 2972329SN/A SQEntries = size_plus_sentinel; 2982292SN/A } 2992292SN/A} 3002292SN/A 3012292SN/Atemplate <class Impl> 3022292SN/Avoid 3032292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 3042292SN/A{ 3052292SN/A assert(inst->isMemRef()); 3062292SN/A 3072292SN/A assert(inst->isLoad() || inst->isStore()); 3082292SN/A 3092292SN/A if (inst->isLoad()) { 3102292SN/A insertLoad(inst); 3112292SN/A } else { 3122292SN/A insertStore(inst); 3132292SN/A } 3142292SN/A 3152292SN/A inst->setInLSQ(); 3162292SN/A} 3172292SN/A 3182292SN/Atemplate <class Impl> 3192292SN/Avoid 3202292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3212292SN/A{ 3222329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3232329SN/A assert(loads < LQEntries); 3242292SN/A 3252292SN/A DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n", 3262292SN/A load_inst->readPC(), loadTail, load_inst->seqNum); 3272292SN/A 3282292SN/A load_inst->lqIdx = loadTail; 3292292SN/A 3302292SN/A if (stores == 0) { 3312292SN/A load_inst->sqIdx = -1; 3322292SN/A } else { 3332292SN/A load_inst->sqIdx = storeTail; 3342292SN/A } 3352292SN/A 3362292SN/A loadQueue[loadTail] = load_inst; 3372292SN/A 3382292SN/A incrLdIdx(loadTail); 3392292SN/A 3402292SN/A ++loads; 3412292SN/A} 3422292SN/A 3432292SN/Atemplate <class Impl> 3442292SN/Avoid 3452292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3462292SN/A{ 3472292SN/A // Make sure it is not full before inserting an instruction. 3482292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3492292SN/A assert(stores < SQEntries); 3502292SN/A 3512292SN/A DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n", 3522292SN/A store_inst->readPC(), storeTail, store_inst->seqNum); 3532292SN/A 3542292SN/A store_inst->sqIdx = storeTail; 3552292SN/A store_inst->lqIdx = loadTail; 3562292SN/A 3572292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3582292SN/A 3592292SN/A incrStIdx(storeTail); 3602292SN/A 3612292SN/A ++stores; 3622292SN/A} 3632292SN/A 3642292SN/Atemplate <class Impl> 3652292SN/Atypename Impl::DynInstPtr 3662292SN/ALSQUnit<Impl>::getMemDepViolator() 3672292SN/A{ 3682292SN/A DynInstPtr temp = memDepViolator; 3692292SN/A 3702292SN/A memDepViolator = NULL; 3712292SN/A 3722292SN/A return temp; 3732292SN/A} 3742292SN/A 3752292SN/Atemplate <class Impl> 3762292SN/Aunsigned 3772292SN/ALSQUnit<Impl>::numFreeEntries() 3782292SN/A{ 3792292SN/A unsigned free_lq_entries = LQEntries - loads; 3802292SN/A unsigned free_sq_entries = SQEntries - stores; 3812292SN/A 3822292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 3832292SN/A // empty/full conditions. Subtract 1 from the free entries. 3842292SN/A if (free_lq_entries < free_sq_entries) { 3852292SN/A return free_lq_entries - 1; 3862292SN/A } else { 3872292SN/A return free_sq_entries - 1; 3882292SN/A } 3892292SN/A} 3902292SN/A 3912292SN/Atemplate <class Impl> 3922292SN/Aint 3932292SN/ALSQUnit<Impl>::numLoadsReady() 3942292SN/A{ 3952292SN/A int load_idx = loadHead; 3962292SN/A int retval = 0; 3972292SN/A 3982292SN/A while (load_idx != loadTail) { 3992292SN/A assert(loadQueue[load_idx]); 4002292SN/A 4012292SN/A if (loadQueue[load_idx]->readyToIssue()) { 4022292SN/A ++retval; 4032292SN/A } 4042292SN/A } 4052292SN/A 4062292SN/A return retval; 4072292SN/A} 4082292SN/A 4092292SN/Atemplate <class Impl> 4102292SN/AFault 4112292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 4122292SN/A{ 4132292SN/A // Execute a specific load. 4142292SN/A Fault load_fault = NoFault; 4152292SN/A 4162292SN/A DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n", 4172292SN/A inst->readPC(),inst->seqNum); 4182292SN/A 4192669Sktlim@umich.edu load_fault = inst->initiateAcc(); 4202292SN/A 4212292SN/A // If the instruction faulted, then we need to send it along to commit 4222292SN/A // without the instruction completing. 4232292SN/A if (load_fault != NoFault) { 4242329SN/A // Send this instruction to commit, also make sure iew stage 4252329SN/A // realizes there is activity. 4262292SN/A iewStage->instToCommit(inst); 4272292SN/A iewStage->activityThisCycle(); 4282292SN/A } 4292292SN/A 4302292SN/A return load_fault; 4312292SN/A} 4322292SN/A 4332292SN/Atemplate <class Impl> 4342292SN/AFault 4352292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 4362292SN/A{ 4372292SN/A using namespace TheISA; 4382292SN/A // Make sure that a store exists. 4392292SN/A assert(stores != 0); 4402292SN/A 4412292SN/A int store_idx = store_inst->sqIdx; 4422292SN/A 4432292SN/A DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n", 4442292SN/A store_inst->readPC(), store_inst->seqNum); 4452292SN/A 4462292SN/A // Check the recently completed loads to see if any match this store's 4472292SN/A // address. If so, then we have a memory ordering violation. 4482292SN/A int load_idx = store_inst->lqIdx; 4492292SN/A 4502292SN/A Fault store_fault = store_inst->initiateAcc(); 4512292SN/A 4522329SN/A if (storeQueue[store_idx].size == 0) { 4532292SN/A DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n", 4542292SN/A store_inst->readPC(),store_inst->seqNum); 4552292SN/A 4562292SN/A return store_fault; 4572292SN/A } 4582292SN/A 4592292SN/A assert(store_fault == NoFault); 4602292SN/A 4612336SN/A if (store_inst->isStoreConditional()) { 4622336SN/A // Store conditionals need to set themselves as able to 4632336SN/A // writeback if we haven't had a fault by here. 4642329SN/A storeQueue[store_idx].canWB = true; 4652292SN/A 4662329SN/A ++storesToWB; 4672292SN/A } 4682292SN/A 4692292SN/A if (!memDepViolator) { 4702292SN/A while (load_idx != loadTail) { 4712329SN/A // Really only need to check loads that have actually executed 4722329SN/A // It's safe to check all loads because effAddr is set to 4732329SN/A // InvalAddr when the dyn inst is created. 4742292SN/A 4752329SN/A // @todo: For now this is extra conservative, detecting a 4762329SN/A // violation if the addresses match assuming all accesses 4772329SN/A // are quad word accesses. 4782329SN/A 4792292SN/A // @todo: Fix this, magic number being used here 4802292SN/A if ((loadQueue[load_idx]->effAddr >> 8) == 4812292SN/A (store_inst->effAddr >> 8)) { 4822292SN/A // A load incorrectly passed this store. Squash and refetch. 4832292SN/A // For now return a fault to show that it was unsuccessful. 4842292SN/A memDepViolator = loadQueue[load_idx]; 4852292SN/A 4862292SN/A return genMachineCheckFault(); 4872292SN/A } 4882292SN/A 4892292SN/A incrLdIdx(load_idx); 4902292SN/A } 4912292SN/A 4922292SN/A // If we've reached this point, there was no violation. 4932292SN/A memDepViolator = NULL; 4942292SN/A } 4952292SN/A 4962292SN/A return store_fault; 4972292SN/A} 4982292SN/A 4992292SN/Atemplate <class Impl> 5002292SN/Avoid 5012292SN/ALSQUnit<Impl>::commitLoad() 5022292SN/A{ 5032292SN/A assert(loadQueue[loadHead]); 5042292SN/A 5052292SN/A DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n", 5062292SN/A loadQueue[loadHead]->readPC()); 5072292SN/A 5082292SN/A loadQueue[loadHead] = NULL; 5092292SN/A 5102292SN/A incrLdIdx(loadHead); 5112292SN/A 5122292SN/A --loads; 5132292SN/A} 5142292SN/A 5152292SN/Atemplate <class Impl> 5162292SN/Avoid 5172292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 5182292SN/A{ 5192292SN/A assert(loads == 0 || loadQueue[loadHead]); 5202292SN/A 5212292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 5222292SN/A commitLoad(); 5232292SN/A } 5242292SN/A} 5252292SN/A 5262292SN/Atemplate <class Impl> 5272292SN/Avoid 5282292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 5292292SN/A{ 5302292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 5312292SN/A 5322292SN/A int store_idx = storeHead; 5332292SN/A 5342292SN/A while (store_idx != storeTail) { 5352292SN/A assert(storeQueue[store_idx].inst); 5362329SN/A // Mark any stores that are now committed and have not yet 5372329SN/A // been marked as able to write back. 5382292SN/A if (!storeQueue[store_idx].canWB) { 5392292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 5402292SN/A break; 5412292SN/A } 5422292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 5432292SN/A "%#x [sn:%lli]\n", 5442292SN/A storeQueue[store_idx].inst->readPC(), 5452292SN/A storeQueue[store_idx].inst->seqNum); 5462292SN/A 5472292SN/A storeQueue[store_idx].canWB = true; 5482292SN/A 5492292SN/A ++storesToWB; 5502292SN/A } 5512292SN/A 5522292SN/A incrStIdx(store_idx); 5532292SN/A } 5542292SN/A} 5552292SN/A 5562292SN/Atemplate <class Impl> 5572292SN/Avoid 5582292SN/ALSQUnit<Impl>::writebackStores() 5592292SN/A{ 5602292SN/A while (storesToWB > 0 && 5612292SN/A storeWBIdx != storeTail && 5622292SN/A storeQueue[storeWBIdx].inst && 5632292SN/A storeQueue[storeWBIdx].canWB && 5642292SN/A usedPorts < cachePorts) { 5652292SN/A 5662678Sktlim@umich.edu if (isStoreBlocked) { 5672678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 5682678Sktlim@umich.edu " is blocked!\n"); 5692678Sktlim@umich.edu break; 5702678Sktlim@umich.edu } 5712678Sktlim@umich.edu 5722329SN/A // Store didn't write any data so no need to write it back to 5732329SN/A // memory. 5742292SN/A if (storeQueue[storeWBIdx].size == 0) { 5752292SN/A completeStore(storeWBIdx); 5762292SN/A 5772292SN/A incrStIdx(storeWBIdx); 5782292SN/A 5792292SN/A continue; 5802292SN/A } 5812678Sktlim@umich.edu 5822292SN/A ++usedPorts; 5832292SN/A 5842292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 5852292SN/A incrStIdx(storeWBIdx); 5862292SN/A 5872292SN/A continue; 5882292SN/A } 5892292SN/A 5902292SN/A assert(storeQueue[storeWBIdx].req); 5912292SN/A assert(!storeQueue[storeWBIdx].committed); 5922292SN/A 5932669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 5942669Sktlim@umich.edu 5952669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 5962292SN/A storeQueue[storeWBIdx].committed = true; 5972292SN/A 5982669Sktlim@umich.edu assert(!inst->memData); 5992669Sktlim@umich.edu inst->memData = new uint8_t[64]; 6002678Sktlim@umich.edu memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data, 6012678Sktlim@umich.edu req->getSize()); 6022669Sktlim@umich.edu 6032669Sktlim@umich.edu PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 6042669Sktlim@umich.edu data_pkt->dataStatic(inst->memData); 6052292SN/A 6062678Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 6072678Sktlim@umich.edu state->isLoad = false; 6082678Sktlim@umich.edu state->idx = storeWBIdx; 6092678Sktlim@umich.edu state->inst = inst; 6102678Sktlim@umich.edu data_pkt->senderState = state; 6112678Sktlim@umich.edu 6122292SN/A DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " 6132292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 6142669Sktlim@umich.edu storeWBIdx, storeQueue[storeWBIdx].inst->readPC(), 6152669Sktlim@umich.edu req->getPaddr(), *(inst->memData), 6162292SN/A storeQueue[storeWBIdx].inst->seqNum); 6172292SN/A 6182669Sktlim@umich.edu if (!dcachePort->sendTiming(data_pkt)) { 6192669Sktlim@umich.edu // Need to handle becoming blocked on a store. 6202678Sktlim@umich.edu isStoreBlocked = true; 6212669Sktlim@umich.edu } else { 6222292SN/A if (isStalled() && 6232292SN/A storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 6242292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 6252292SN/A "load idx:%i\n", 6262292SN/A stallingStoreIsn, stallingLoadIdx); 6272292SN/A stalled = false; 6282292SN/A stallingStoreIsn = 0; 6292292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 6302292SN/A } 6312678Sktlim@umich.edu 6322678Sktlim@umich.edu if (!(req->getFlags() & LOCKED)) { 6332678Sktlim@umich.edu assert(!storeQueue[storeWBIdx].inst->isStoreConditional()); 6342678Sktlim@umich.edu // Non-store conditionals do not need a writeback. 6352678Sktlim@umich.edu state->noWB = true; 6362329SN/A } 6372678Sktlim@umich.edu 6382669Sktlim@umich.edu if (data_pkt->result != Packet::Success) { 6392329SN/A DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n", 6402329SN/A storeWBIdx); 6412292SN/A 6422292SN/A DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n", 6432292SN/A storeQueue[storeWBIdx].inst->seqNum); 6442292SN/A 6452292SN/A //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum); 6462292SN/A 6472292SN/A //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size()); 6482292SN/A 6492329SN/A // @todo: Increment stat here. 6502292SN/A } else { 6512292SN/A DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n", 6522292SN/A storeWBIdx); 6532292SN/A 6542292SN/A DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", 6552292SN/A storeQueue[storeWBIdx].inst->seqNum); 6562292SN/A } 6572292SN/A 6582292SN/A incrStIdx(storeWBIdx); 6592292SN/A } 6602292SN/A } 6612292SN/A 6622292SN/A // Not sure this should set it to 0. 6632292SN/A usedPorts = 0; 6642292SN/A 6652292SN/A assert(stores >= 0 && storesToWB >= 0); 6662292SN/A} 6672292SN/A 6682292SN/A/*template <class Impl> 6692292SN/Avoid 6702292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 6712292SN/A{ 6722292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 6732292SN/A mshrSeqNums.end(), 6742292SN/A seqNum); 6752292SN/A 6762292SN/A if (mshr_it != mshrSeqNums.end()) { 6772292SN/A mshrSeqNums.erase(mshr_it); 6782292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 6792292SN/A } 6802292SN/A}*/ 6812292SN/A 6822292SN/Atemplate <class Impl> 6832292SN/Avoid 6842292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 6852292SN/A{ 6862292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 6872329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 6882292SN/A 6892292SN/A int load_idx = loadTail; 6902292SN/A decrLdIdx(load_idx); 6912292SN/A 6922292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 6932292SN/A DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, " 6942292SN/A "[sn:%lli]\n", 6952292SN/A loadQueue[load_idx]->readPC(), 6962292SN/A loadQueue[load_idx]->seqNum); 6972292SN/A 6982292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 6992292SN/A stalled = false; 7002292SN/A stallingStoreIsn = 0; 7012292SN/A stallingLoadIdx = 0; 7022292SN/A } 7032292SN/A 7042329SN/A // Clear the smart pointer to make sure it is decremented. 7052292SN/A loadQueue[load_idx]->squashed = true; 7062292SN/A loadQueue[load_idx] = NULL; 7072292SN/A --loads; 7082292SN/A 7092292SN/A // Inefficient! 7102292SN/A loadTail = load_idx; 7112292SN/A 7122292SN/A decrLdIdx(load_idx); 7132292SN/A } 7142292SN/A 7152292SN/A if (isLoadBlocked) { 7162292SN/A if (squashed_num < blockedLoadSeqNum) { 7172292SN/A isLoadBlocked = false; 7182292SN/A loadBlockedHandled = false; 7192292SN/A blockedLoadSeqNum = 0; 7202292SN/A } 7212292SN/A } 7222292SN/A 7232292SN/A int store_idx = storeTail; 7242292SN/A decrStIdx(store_idx); 7252292SN/A 7262292SN/A while (stores != 0 && 7272292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 7282329SN/A // Instructions marked as can WB are already committed. 7292292SN/A if (storeQueue[store_idx].canWB) { 7302292SN/A break; 7312292SN/A } 7322292SN/A 7332292SN/A DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, " 7342292SN/A "idx:%i [sn:%lli]\n", 7352292SN/A storeQueue[store_idx].inst->readPC(), 7362292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 7372292SN/A 7382329SN/A // I don't think this can happen. It should have been cleared 7392329SN/A // by the stalling load. 7402292SN/A if (isStalled() && 7412292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 7422292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 7432292SN/A stalled = false; 7442292SN/A stallingStoreIsn = 0; 7452292SN/A } 7462292SN/A 7472329SN/A // Clear the smart pointer to make sure it is decremented. 7482292SN/A storeQueue[store_idx].inst->squashed = true; 7492292SN/A storeQueue[store_idx].inst = NULL; 7502292SN/A storeQueue[store_idx].canWB = 0; 7512292SN/A 7522292SN/A storeQueue[store_idx].req = NULL; 7532292SN/A --stores; 7542292SN/A 7552292SN/A // Inefficient! 7562292SN/A storeTail = store_idx; 7572292SN/A 7582292SN/A decrStIdx(store_idx); 7592292SN/A } 7602292SN/A} 7612292SN/A 7622292SN/Atemplate <class Impl> 7632292SN/Avoid 7642678Sktlim@umich.eduLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 7652678Sktlim@umich.edu{ 7662678Sktlim@umich.edu iewStage->wakeCPU(); 7672678Sktlim@umich.edu 7682678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 7692678Sktlim@umich.edu if (inst->isSquashed()) { 7702678Sktlim@umich.edu assert(!inst->isStore()); 7712678Sktlim@umich.edu return; 7722678Sktlim@umich.edu } 7732678Sktlim@umich.edu 7742678Sktlim@umich.edu if (!inst->isExecuted()) { 7752678Sktlim@umich.edu inst->setExecuted(); 7762678Sktlim@umich.edu 7772678Sktlim@umich.edu // Complete access to copy data to proper place. 7782678Sktlim@umich.edu inst->completeAcc(pkt); 7792678Sktlim@umich.edu } 7802678Sktlim@umich.edu 7812678Sktlim@umich.edu // Need to insert instruction into queue to commit 7822678Sktlim@umich.edu iewStage->instToCommit(inst); 7832678Sktlim@umich.edu 7842678Sktlim@umich.edu iewStage->activityThisCycle(); 7852678Sktlim@umich.edu} 7862678Sktlim@umich.edu 7872678Sktlim@umich.edutemplate <class Impl> 7882678Sktlim@umich.eduvoid 7892292SN/ALSQUnit<Impl>::completeStore(int store_idx) 7902292SN/A{ 7912292SN/A assert(storeQueue[store_idx].inst); 7922292SN/A storeQueue[store_idx].completed = true; 7932292SN/A --storesToWB; 7942292SN/A // A bit conservative because a store completion may not free up entries, 7952292SN/A // but hopefully avoids two store completions in one cycle from making 7962292SN/A // the CPU tick twice. 7972292SN/A cpu->activityThisCycle(); 7982292SN/A 7992292SN/A if (store_idx == storeHead) { 8002292SN/A do { 8012292SN/A incrStIdx(storeHead); 8022292SN/A 8032292SN/A --stores; 8042292SN/A } while (storeQueue[storeHead].completed && 8052292SN/A storeHead != storeTail); 8062292SN/A 8072292SN/A iewStage->updateLSQNextCycle = true; 8082292SN/A } 8092292SN/A 8102329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 8112329SN/A "idx:%i\n", 8122329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 8132292SN/A 8142292SN/A if (isStalled() && 8152292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 8162292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 8172292SN/A "load idx:%i\n", 8182292SN/A stallingStoreIsn, stallingLoadIdx); 8192292SN/A stalled = false; 8202292SN/A stallingStoreIsn = 0; 8212292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 8222292SN/A } 8232316SN/A 8242316SN/A storeQueue[store_idx].inst->setCompleted(); 8252329SN/A 8262329SN/A // Tell the checker we've completed this instruction. Some stores 8272329SN/A // may get reported twice to the checker, but the checker can 8282329SN/A // handle that case. 8292316SN/A if (cpu->checker) { 8302316SN/A cpu->checker->tick(storeQueue[store_idx].inst); 8312316SN/A } 8322292SN/A} 8332292SN/A 8342292SN/Atemplate <class Impl> 8352292SN/Ainline void 8362292SN/ALSQUnit<Impl>::incrStIdx(int &store_idx) 8372292SN/A{ 8382292SN/A if (++store_idx >= SQEntries) 8392292SN/A store_idx = 0; 8402292SN/A} 8412292SN/A 8422292SN/Atemplate <class Impl> 8432292SN/Ainline void 8442292SN/ALSQUnit<Impl>::decrStIdx(int &store_idx) 8452292SN/A{ 8462292SN/A if (--store_idx < 0) 8472292SN/A store_idx += SQEntries; 8482292SN/A} 8492292SN/A 8502292SN/Atemplate <class Impl> 8512292SN/Ainline void 8522292SN/ALSQUnit<Impl>::incrLdIdx(int &load_idx) 8532292SN/A{ 8542292SN/A if (++load_idx >= LQEntries) 8552292SN/A load_idx = 0; 8562292SN/A} 8572292SN/A 8582292SN/Atemplate <class Impl> 8592292SN/Ainline void 8602292SN/ALSQUnit<Impl>::decrLdIdx(int &load_idx) 8612292SN/A{ 8622292SN/A if (--load_idx < 0) 8632292SN/A load_idx += LQEntries; 8642292SN/A} 8652329SN/A 8662329SN/Atemplate <class Impl> 8672329SN/Avoid 8682329SN/ALSQUnit<Impl>::dumpInsts() 8692329SN/A{ 8702329SN/A cprintf("Load store queue: Dumping instructions.\n"); 8712329SN/A cprintf("Load queue size: %i\n", loads); 8722329SN/A cprintf("Load queue: "); 8732329SN/A 8742329SN/A int load_idx = loadHead; 8752329SN/A 8762329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 8772329SN/A cprintf("%#x ", loadQueue[load_idx]->readPC()); 8782329SN/A 8792329SN/A incrLdIdx(load_idx); 8802329SN/A } 8812329SN/A 8822329SN/A cprintf("Store queue size: %i\n", stores); 8832329SN/A cprintf("Store queue: "); 8842329SN/A 8852329SN/A int store_idx = storeHead; 8862329SN/A 8872329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 8882329SN/A cprintf("%#x ", storeQueue[store_idx].inst->readPC()); 8892329SN/A 8902329SN/A incrStIdx(store_idx); 8912329SN/A } 8922329SN/A 8932329SN/A cprintf("\n"); 8942329SN/A} 895