lsq_unit_impl.hh revision 2678
12292SN/A/* 22292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32292SN/A * All rights reserved. 42292SN/A * 52292SN/A * Redistribution and use in source and binary forms, with or without 62292SN/A * modification, are permitted provided that the following conditions are 72292SN/A * met: redistributions of source code must retain the above copyright 82292SN/A * notice, this list of conditions and the following disclaimer; 92292SN/A * redistributions in binary form must reproduce the above copyright 102292SN/A * notice, this list of conditions and the following disclaimer in the 112292SN/A * documentation and/or other materials provided with the distribution; 122292SN/A * neither the name of the copyright holders nor the names of its 132292SN/A * contributors may be used to endorse or promote products derived from 142292SN/A * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272292SN/A */ 282292SN/A 292316SN/A#include "cpu/checker/cpu.hh" 302292SN/A#include "cpu/o3/lsq_unit.hh" 312292SN/A#include "base/str.hh" 322669Sktlim@umich.edu#include "mem/request.hh" 332292SN/A 342669Sktlim@umich.edutemplate<class Impl> 352678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 362678Sktlim@umich.edu LSQUnit *lsq_ptr) 372678Sktlim@umich.edu : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 382292SN/A{ 392678Sktlim@umich.edu this->setFlags(Event::AutoDelete); 402292SN/A} 412292SN/A 422669Sktlim@umich.edutemplate<class Impl> 432292SN/Avoid 442678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 452292SN/A{ 462678Sktlim@umich.edu if (!lsqPtr->isSwitchedOut()) { 472678Sktlim@umich.edu lsqPtr->writeback(inst, pkt); 482678Sktlim@umich.edu } 492678Sktlim@umich.edu delete pkt; 502678Sktlim@umich.edu} 512292SN/A 522678Sktlim@umich.edutemplate<class Impl> 532678Sktlim@umich.educonst char * 542678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::description() 552678Sktlim@umich.edu{ 562678Sktlim@umich.edu return "Store writeback event"; 572678Sktlim@umich.edu} 582292SN/A 592678Sktlim@umich.edutemplate<class Impl> 602678Sktlim@umich.eduvoid 612678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 622678Sktlim@umich.edu{ 632678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 642678Sktlim@umich.edu DynInstPtr inst = state->inst; 652678Sktlim@umich.edu DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum); 662678Sktlim@umich.edu// DPRINTF(Activity, "Activity: Ld Writeback event [sn:%lli]\n", inst->seqNum); 672344SN/A 682678Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 692678Sktlim@umich.edu 702678Sktlim@umich.edu if (isSwitchedOut() || inst->isSquashed()) { 712678Sktlim@umich.edu delete state; 722678Sktlim@umich.edu delete pkt; 732307SN/A return; 742678Sktlim@umich.edu } else { 752678Sktlim@umich.edu if (!state->noWB) { 762678Sktlim@umich.edu writeback(inst, pkt); 772678Sktlim@umich.edu } 782678Sktlim@umich.edu 792678Sktlim@umich.edu if (inst->isStore()) { 802678Sktlim@umich.edu completeStore(state->idx); 812678Sktlim@umich.edu } 822344SN/A } 832307SN/A 842678Sktlim@umich.edu delete state; 852678Sktlim@umich.edu delete pkt; 862292SN/A} 872292SN/A 882292SN/Atemplate <class Impl> 892669Sktlim@umich.eduTick 902669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvAtomic(PacketPtr pkt) 912292SN/A{ 922669Sktlim@umich.edu panic("O3CPU model does not work with atomic mode!"); 932669Sktlim@umich.edu return curTick; 942669Sktlim@umich.edu} 952669Sktlim@umich.edu 962669Sktlim@umich.edutemplate <class Impl> 972669Sktlim@umich.eduvoid 982669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvFunctional(PacketPtr pkt) 992669Sktlim@umich.edu{ 1002669Sktlim@umich.edu panic("O3CPU doesn't expect recvFunctional callback!"); 1012669Sktlim@umich.edu} 1022669Sktlim@umich.edu 1032669Sktlim@umich.edutemplate <class Impl> 1042669Sktlim@umich.eduvoid 1052669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvStatusChange(Status status) 1062669Sktlim@umich.edu{ 1072669Sktlim@umich.edu if (status == RangeChange) 1082669Sktlim@umich.edu return; 1092669Sktlim@umich.edu 1102669Sktlim@umich.edu panic("O3CPU doesn't expect recvStatusChange callback!"); 1112669Sktlim@umich.edu} 1122669Sktlim@umich.edu 1132669Sktlim@umich.edutemplate <class Impl> 1142669Sktlim@umich.edubool 1152669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvTiming(PacketPtr pkt) 1162669Sktlim@umich.edu{ 1172669Sktlim@umich.edu lsq->completeDataAccess(pkt); 1182669Sktlim@umich.edu return true; 1192669Sktlim@umich.edu} 1202669Sktlim@umich.edu 1212669Sktlim@umich.edutemplate <class Impl> 1222669Sktlim@umich.eduvoid 1232669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvRetry() 1242669Sktlim@umich.edu{ 1252669Sktlim@umich.edu panic("Retry unsupported for now!"); 1262669Sktlim@umich.edu // we shouldn't get a retry unless we have a packet that we're 1272669Sktlim@umich.edu // waiting to transmit 1282669Sktlim@umich.edu/* 1292669Sktlim@umich.edu assert(cpu->dcache_pkt != NULL); 1302669Sktlim@umich.edu assert(cpu->_status == DcacheRetry); 1312669Sktlim@umich.edu PacketPtr tmp = cpu->dcache_pkt; 1322669Sktlim@umich.edu if (sendTiming(tmp)) { 1332669Sktlim@umich.edu cpu->_status = DcacheWaitResponse; 1342669Sktlim@umich.edu cpu->dcache_pkt = NULL; 1352669Sktlim@umich.edu } 1362669Sktlim@umich.edu*/ 1372292SN/A} 1382292SN/A 1392292SN/Atemplate <class Impl> 1402292SN/ALSQUnit<Impl>::LSQUnit() 1412678Sktlim@umich.edu : loads(0), stores(0), storesToWB(0), stalled(false), 1422678Sktlim@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1432292SN/A loadBlockedHandled(false) 1442292SN/A{ 1452292SN/A} 1462292SN/A 1472292SN/Atemplate<class Impl> 1482292SN/Avoid 1492292SN/ALSQUnit<Impl>::init(Params *params, unsigned maxLQEntries, 1502292SN/A unsigned maxSQEntries, unsigned id) 1512292SN/A{ 1522292SN/A DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1532292SN/A 1542307SN/A switchedOut = false; 1552307SN/A 1562292SN/A lsqID = id; 1572292SN/A 1582329SN/A // Add 1 for the sentinel entry (they are circular queues). 1592329SN/A LQEntries = maxLQEntries + 1; 1602329SN/A SQEntries = maxSQEntries + 1; 1612292SN/A 1622292SN/A loadQueue.resize(LQEntries); 1632292SN/A storeQueue.resize(SQEntries); 1642292SN/A 1652292SN/A loadHead = loadTail = 0; 1662292SN/A 1672292SN/A storeHead = storeWBIdx = storeTail = 0; 1682292SN/A 1692292SN/A usedPorts = 0; 1702292SN/A cachePorts = params->cachePorts; 1712292SN/A 1722678Sktlim@umich.edu mem = params->mem; 1732292SN/A 1742329SN/A memDepViolator = NULL; 1752292SN/A 1762292SN/A blockedLoadSeqNum = 0; 1772292SN/A} 1782292SN/A 1792292SN/Atemplate<class Impl> 1802669Sktlim@umich.eduvoid 1812669Sktlim@umich.eduLSQUnit<Impl>::setCPU(FullCPU *cpu_ptr) 1822669Sktlim@umich.edu{ 1832669Sktlim@umich.edu cpu = cpu_ptr; 1842669Sktlim@umich.edu dcachePort = new DcachePort(cpu, this); 1852678Sktlim@umich.edu 1862678Sktlim@umich.edu Port *mem_dport = mem->getPort(""); 1872678Sktlim@umich.edu dcachePort->setPeer(mem_dport); 1882678Sktlim@umich.edu mem_dport->setPeer(dcachePort); 1892669Sktlim@umich.edu} 1902669Sktlim@umich.edu 1912669Sktlim@umich.edutemplate<class Impl> 1922292SN/Astd::string 1932292SN/ALSQUnit<Impl>::name() const 1942292SN/A{ 1952292SN/A if (Impl::MaxThreads == 1) { 1962292SN/A return iewStage->name() + ".lsq"; 1972292SN/A } else { 1982292SN/A return iewStage->name() + ".lsq.thread." + to_string(lsqID); 1992292SN/A } 2002292SN/A} 2012292SN/A 2022292SN/Atemplate<class Impl> 2032292SN/Avoid 2042292SN/ALSQUnit<Impl>::clearLQ() 2052292SN/A{ 2062292SN/A loadQueue.clear(); 2072292SN/A} 2082292SN/A 2092292SN/Atemplate<class Impl> 2102292SN/Avoid 2112292SN/ALSQUnit<Impl>::clearSQ() 2122292SN/A{ 2132292SN/A storeQueue.clear(); 2142292SN/A} 2152292SN/A 2162292SN/A#if 0 2172292SN/Atemplate<class Impl> 2182292SN/Avoid 2192292SN/ALSQUnit<Impl>::setPageTable(PageTable *pt_ptr) 2202292SN/A{ 2212292SN/A DPRINTF(LSQUnit, "Setting the page table pointer.\n"); 2222292SN/A pTable = pt_ptr; 2232292SN/A} 2242292SN/A#endif 2252292SN/A 2262292SN/Atemplate<class Impl> 2272292SN/Avoid 2282307SN/ALSQUnit<Impl>::switchOut() 2292307SN/A{ 2302307SN/A switchedOut = true; 2312307SN/A for (int i = 0; i < loadQueue.size(); ++i) 2322307SN/A loadQueue[i] = NULL; 2332307SN/A 2342329SN/A assert(storesToWB == 0); 2352307SN/A} 2362307SN/A 2372307SN/Atemplate<class Impl> 2382307SN/Avoid 2392307SN/ALSQUnit<Impl>::takeOverFrom() 2402307SN/A{ 2412307SN/A switchedOut = false; 2422307SN/A loads = stores = storesToWB = 0; 2432307SN/A 2442307SN/A loadHead = loadTail = 0; 2452307SN/A 2462307SN/A storeHead = storeWBIdx = storeTail = 0; 2472307SN/A 2482307SN/A usedPorts = 0; 2492307SN/A 2502329SN/A memDepViolator = NULL; 2512307SN/A 2522307SN/A blockedLoadSeqNum = 0; 2532307SN/A 2542307SN/A stalled = false; 2552307SN/A isLoadBlocked = false; 2562307SN/A loadBlockedHandled = false; 2572307SN/A} 2582307SN/A 2592307SN/Atemplate<class Impl> 2602307SN/Avoid 2612292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 2622292SN/A{ 2632329SN/A unsigned size_plus_sentinel = size + 1; 2642329SN/A assert(size_plus_sentinel >= LQEntries); 2652292SN/A 2662329SN/A if (size_plus_sentinel > LQEntries) { 2672329SN/A while (size_plus_sentinel > loadQueue.size()) { 2682292SN/A DynInstPtr dummy; 2692292SN/A loadQueue.push_back(dummy); 2702292SN/A LQEntries++; 2712292SN/A } 2722292SN/A } else { 2732329SN/A LQEntries = size_plus_sentinel; 2742292SN/A } 2752292SN/A 2762292SN/A} 2772292SN/A 2782292SN/Atemplate<class Impl> 2792292SN/Avoid 2802292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 2812292SN/A{ 2822329SN/A unsigned size_plus_sentinel = size + 1; 2832329SN/A if (size_plus_sentinel > SQEntries) { 2842329SN/A while (size_plus_sentinel > storeQueue.size()) { 2852292SN/A SQEntry dummy; 2862292SN/A storeQueue.push_back(dummy); 2872292SN/A SQEntries++; 2882292SN/A } 2892292SN/A } else { 2902329SN/A SQEntries = size_plus_sentinel; 2912292SN/A } 2922292SN/A} 2932292SN/A 2942292SN/Atemplate <class Impl> 2952292SN/Avoid 2962292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 2972292SN/A{ 2982292SN/A assert(inst->isMemRef()); 2992292SN/A 3002292SN/A assert(inst->isLoad() || inst->isStore()); 3012292SN/A 3022292SN/A if (inst->isLoad()) { 3032292SN/A insertLoad(inst); 3042292SN/A } else { 3052292SN/A insertStore(inst); 3062292SN/A } 3072292SN/A 3082292SN/A inst->setInLSQ(); 3092292SN/A} 3102292SN/A 3112292SN/Atemplate <class Impl> 3122292SN/Avoid 3132292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3142292SN/A{ 3152329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3162329SN/A assert(loads < LQEntries); 3172292SN/A 3182292SN/A DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n", 3192292SN/A load_inst->readPC(), loadTail, load_inst->seqNum); 3202292SN/A 3212292SN/A load_inst->lqIdx = loadTail; 3222292SN/A 3232292SN/A if (stores == 0) { 3242292SN/A load_inst->sqIdx = -1; 3252292SN/A } else { 3262292SN/A load_inst->sqIdx = storeTail; 3272292SN/A } 3282292SN/A 3292292SN/A loadQueue[loadTail] = load_inst; 3302292SN/A 3312292SN/A incrLdIdx(loadTail); 3322292SN/A 3332292SN/A ++loads; 3342292SN/A} 3352292SN/A 3362292SN/Atemplate <class Impl> 3372292SN/Avoid 3382292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3392292SN/A{ 3402292SN/A // Make sure it is not full before inserting an instruction. 3412292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3422292SN/A assert(stores < SQEntries); 3432292SN/A 3442292SN/A DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n", 3452292SN/A store_inst->readPC(), storeTail, store_inst->seqNum); 3462292SN/A 3472292SN/A store_inst->sqIdx = storeTail; 3482292SN/A store_inst->lqIdx = loadTail; 3492292SN/A 3502292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3512292SN/A 3522292SN/A incrStIdx(storeTail); 3532292SN/A 3542292SN/A ++stores; 3552292SN/A} 3562292SN/A 3572292SN/Atemplate <class Impl> 3582292SN/Atypename Impl::DynInstPtr 3592292SN/ALSQUnit<Impl>::getMemDepViolator() 3602292SN/A{ 3612292SN/A DynInstPtr temp = memDepViolator; 3622292SN/A 3632292SN/A memDepViolator = NULL; 3642292SN/A 3652292SN/A return temp; 3662292SN/A} 3672292SN/A 3682292SN/Atemplate <class Impl> 3692292SN/Aunsigned 3702292SN/ALSQUnit<Impl>::numFreeEntries() 3712292SN/A{ 3722292SN/A unsigned free_lq_entries = LQEntries - loads; 3732292SN/A unsigned free_sq_entries = SQEntries - stores; 3742292SN/A 3752292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 3762292SN/A // empty/full conditions. Subtract 1 from the free entries. 3772292SN/A if (free_lq_entries < free_sq_entries) { 3782292SN/A return free_lq_entries - 1; 3792292SN/A } else { 3802292SN/A return free_sq_entries - 1; 3812292SN/A } 3822292SN/A} 3832292SN/A 3842292SN/Atemplate <class Impl> 3852292SN/Aint 3862292SN/ALSQUnit<Impl>::numLoadsReady() 3872292SN/A{ 3882292SN/A int load_idx = loadHead; 3892292SN/A int retval = 0; 3902292SN/A 3912292SN/A while (load_idx != loadTail) { 3922292SN/A assert(loadQueue[load_idx]); 3932292SN/A 3942292SN/A if (loadQueue[load_idx]->readyToIssue()) { 3952292SN/A ++retval; 3962292SN/A } 3972292SN/A } 3982292SN/A 3992292SN/A return retval; 4002292SN/A} 4012292SN/A 4022292SN/Atemplate <class Impl> 4032292SN/AFault 4042292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 4052292SN/A{ 4062292SN/A // Execute a specific load. 4072292SN/A Fault load_fault = NoFault; 4082292SN/A 4092292SN/A DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n", 4102292SN/A inst->readPC(),inst->seqNum); 4112292SN/A 4122669Sktlim@umich.edu load_fault = inst->initiateAcc(); 4132292SN/A 4142292SN/A // If the instruction faulted, then we need to send it along to commit 4152292SN/A // without the instruction completing. 4162292SN/A if (load_fault != NoFault) { 4172329SN/A // Send this instruction to commit, also make sure iew stage 4182329SN/A // realizes there is activity. 4192292SN/A iewStage->instToCommit(inst); 4202292SN/A iewStage->activityThisCycle(); 4212292SN/A } 4222292SN/A 4232292SN/A return load_fault; 4242292SN/A} 4252292SN/A 4262292SN/Atemplate <class Impl> 4272292SN/AFault 4282292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 4292292SN/A{ 4302292SN/A using namespace TheISA; 4312292SN/A // Make sure that a store exists. 4322292SN/A assert(stores != 0); 4332292SN/A 4342292SN/A int store_idx = store_inst->sqIdx; 4352292SN/A 4362292SN/A DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n", 4372292SN/A store_inst->readPC(), store_inst->seqNum); 4382292SN/A 4392292SN/A // Check the recently completed loads to see if any match this store's 4402292SN/A // address. If so, then we have a memory ordering violation. 4412292SN/A int load_idx = store_inst->lqIdx; 4422292SN/A 4432292SN/A Fault store_fault = store_inst->initiateAcc(); 4442292SN/A 4452329SN/A if (storeQueue[store_idx].size == 0) { 4462292SN/A DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n", 4472292SN/A store_inst->readPC(),store_inst->seqNum); 4482292SN/A 4492292SN/A return store_fault; 4502292SN/A } 4512292SN/A 4522292SN/A assert(store_fault == NoFault); 4532292SN/A 4542336SN/A if (store_inst->isStoreConditional()) { 4552336SN/A // Store conditionals need to set themselves as able to 4562336SN/A // writeback if we haven't had a fault by here. 4572329SN/A storeQueue[store_idx].canWB = true; 4582292SN/A 4592329SN/A ++storesToWB; 4602292SN/A } 4612292SN/A 4622292SN/A if (!memDepViolator) { 4632292SN/A while (load_idx != loadTail) { 4642329SN/A // Really only need to check loads that have actually executed 4652329SN/A // It's safe to check all loads because effAddr is set to 4662329SN/A // InvalAddr when the dyn inst is created. 4672292SN/A 4682329SN/A // @todo: For now this is extra conservative, detecting a 4692329SN/A // violation if the addresses match assuming all accesses 4702329SN/A // are quad word accesses. 4712329SN/A 4722292SN/A // @todo: Fix this, magic number being used here 4732292SN/A if ((loadQueue[load_idx]->effAddr >> 8) == 4742292SN/A (store_inst->effAddr >> 8)) { 4752292SN/A // A load incorrectly passed this store. Squash and refetch. 4762292SN/A // For now return a fault to show that it was unsuccessful. 4772292SN/A memDepViolator = loadQueue[load_idx]; 4782292SN/A 4792292SN/A return genMachineCheckFault(); 4802292SN/A } 4812292SN/A 4822292SN/A incrLdIdx(load_idx); 4832292SN/A } 4842292SN/A 4852292SN/A // If we've reached this point, there was no violation. 4862292SN/A memDepViolator = NULL; 4872292SN/A } 4882292SN/A 4892292SN/A return store_fault; 4902292SN/A} 4912292SN/A 4922292SN/Atemplate <class Impl> 4932292SN/Avoid 4942292SN/ALSQUnit<Impl>::commitLoad() 4952292SN/A{ 4962292SN/A assert(loadQueue[loadHead]); 4972292SN/A 4982292SN/A DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n", 4992292SN/A loadQueue[loadHead]->readPC()); 5002292SN/A 5012292SN/A loadQueue[loadHead] = NULL; 5022292SN/A 5032292SN/A incrLdIdx(loadHead); 5042292SN/A 5052292SN/A --loads; 5062292SN/A} 5072292SN/A 5082292SN/Atemplate <class Impl> 5092292SN/Avoid 5102292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 5112292SN/A{ 5122292SN/A assert(loads == 0 || loadQueue[loadHead]); 5132292SN/A 5142292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 5152292SN/A commitLoad(); 5162292SN/A } 5172292SN/A} 5182292SN/A 5192292SN/Atemplate <class Impl> 5202292SN/Avoid 5212292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 5222292SN/A{ 5232292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 5242292SN/A 5252292SN/A int store_idx = storeHead; 5262292SN/A 5272292SN/A while (store_idx != storeTail) { 5282292SN/A assert(storeQueue[store_idx].inst); 5292329SN/A // Mark any stores that are now committed and have not yet 5302329SN/A // been marked as able to write back. 5312292SN/A if (!storeQueue[store_idx].canWB) { 5322292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 5332292SN/A break; 5342292SN/A } 5352292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 5362292SN/A "%#x [sn:%lli]\n", 5372292SN/A storeQueue[store_idx].inst->readPC(), 5382292SN/A storeQueue[store_idx].inst->seqNum); 5392292SN/A 5402292SN/A storeQueue[store_idx].canWB = true; 5412292SN/A 5422292SN/A ++storesToWB; 5432292SN/A } 5442292SN/A 5452292SN/A incrStIdx(store_idx); 5462292SN/A } 5472292SN/A} 5482292SN/A 5492292SN/Atemplate <class Impl> 5502292SN/Avoid 5512292SN/ALSQUnit<Impl>::writebackStores() 5522292SN/A{ 5532292SN/A while (storesToWB > 0 && 5542292SN/A storeWBIdx != storeTail && 5552292SN/A storeQueue[storeWBIdx].inst && 5562292SN/A storeQueue[storeWBIdx].canWB && 5572292SN/A usedPorts < cachePorts) { 5582292SN/A 5592678Sktlim@umich.edu if (isStoreBlocked) { 5602678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 5612678Sktlim@umich.edu " is blocked!\n"); 5622678Sktlim@umich.edu break; 5632678Sktlim@umich.edu } 5642678Sktlim@umich.edu 5652329SN/A // Store didn't write any data so no need to write it back to 5662329SN/A // memory. 5672292SN/A if (storeQueue[storeWBIdx].size == 0) { 5682292SN/A completeStore(storeWBIdx); 5692292SN/A 5702292SN/A incrStIdx(storeWBIdx); 5712292SN/A 5722292SN/A continue; 5732292SN/A } 5742678Sktlim@umich.edu 5752292SN/A ++usedPorts; 5762292SN/A 5772292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 5782292SN/A incrStIdx(storeWBIdx); 5792292SN/A 5802292SN/A continue; 5812292SN/A } 5822292SN/A 5832292SN/A assert(storeQueue[storeWBIdx].req); 5842292SN/A assert(!storeQueue[storeWBIdx].committed); 5852292SN/A 5862669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 5872669Sktlim@umich.edu 5882669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 5892292SN/A storeQueue[storeWBIdx].committed = true; 5902292SN/A 5912669Sktlim@umich.edu assert(!inst->memData); 5922669Sktlim@umich.edu inst->memData = new uint8_t[64]; 5932678Sktlim@umich.edu memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data, 5942678Sktlim@umich.edu req->getSize()); 5952669Sktlim@umich.edu 5962669Sktlim@umich.edu PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 5972669Sktlim@umich.edu data_pkt->dataStatic(inst->memData); 5982292SN/A 5992678Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 6002678Sktlim@umich.edu state->isLoad = false; 6012678Sktlim@umich.edu state->idx = storeWBIdx; 6022678Sktlim@umich.edu state->inst = inst; 6032678Sktlim@umich.edu data_pkt->senderState = state; 6042678Sktlim@umich.edu 6052292SN/A DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " 6062292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 6072669Sktlim@umich.edu storeWBIdx, storeQueue[storeWBIdx].inst->readPC(), 6082669Sktlim@umich.edu req->getPaddr(), *(inst->memData), 6092292SN/A storeQueue[storeWBIdx].inst->seqNum); 6102292SN/A 6112669Sktlim@umich.edu if (!dcachePort->sendTiming(data_pkt)) { 6122669Sktlim@umich.edu // Need to handle becoming blocked on a store. 6132678Sktlim@umich.edu isStoreBlocked = true; 6142669Sktlim@umich.edu } else { 6152292SN/A if (isStalled() && 6162292SN/A storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 6172292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 6182292SN/A "load idx:%i\n", 6192292SN/A stallingStoreIsn, stallingLoadIdx); 6202292SN/A stalled = false; 6212292SN/A stallingStoreIsn = 0; 6222292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 6232292SN/A } 6242678Sktlim@umich.edu 6252678Sktlim@umich.edu if (!(req->getFlags() & LOCKED)) { 6262678Sktlim@umich.edu assert(!storeQueue[storeWBIdx].inst->isStoreConditional()); 6272678Sktlim@umich.edu // Non-store conditionals do not need a writeback. 6282678Sktlim@umich.edu state->noWB = true; 6292329SN/A } 6302678Sktlim@umich.edu 6312669Sktlim@umich.edu if (data_pkt->result != Packet::Success) { 6322329SN/A DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n", 6332329SN/A storeWBIdx); 6342292SN/A 6352292SN/A DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n", 6362292SN/A storeQueue[storeWBIdx].inst->seqNum); 6372292SN/A 6382292SN/A //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum); 6392292SN/A 6402292SN/A //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size()); 6412292SN/A 6422329SN/A // @todo: Increment stat here. 6432292SN/A } else { 6442292SN/A DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n", 6452292SN/A storeWBIdx); 6462292SN/A 6472292SN/A DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", 6482292SN/A storeQueue[storeWBIdx].inst->seqNum); 6492292SN/A } 6502292SN/A 6512292SN/A incrStIdx(storeWBIdx); 6522292SN/A } 6532292SN/A } 6542292SN/A 6552292SN/A // Not sure this should set it to 0. 6562292SN/A usedPorts = 0; 6572292SN/A 6582292SN/A assert(stores >= 0 && storesToWB >= 0); 6592292SN/A} 6602292SN/A 6612292SN/A/*template <class Impl> 6622292SN/Avoid 6632292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 6642292SN/A{ 6652292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 6662292SN/A mshrSeqNums.end(), 6672292SN/A seqNum); 6682292SN/A 6692292SN/A if (mshr_it != mshrSeqNums.end()) { 6702292SN/A mshrSeqNums.erase(mshr_it); 6712292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 6722292SN/A } 6732292SN/A}*/ 6742292SN/A 6752292SN/Atemplate <class Impl> 6762292SN/Avoid 6772292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 6782292SN/A{ 6792292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 6802329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 6812292SN/A 6822292SN/A int load_idx = loadTail; 6832292SN/A decrLdIdx(load_idx); 6842292SN/A 6852292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 6862292SN/A DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, " 6872292SN/A "[sn:%lli]\n", 6882292SN/A loadQueue[load_idx]->readPC(), 6892292SN/A loadQueue[load_idx]->seqNum); 6902292SN/A 6912292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 6922292SN/A stalled = false; 6932292SN/A stallingStoreIsn = 0; 6942292SN/A stallingLoadIdx = 0; 6952292SN/A } 6962292SN/A 6972329SN/A // Clear the smart pointer to make sure it is decremented. 6982292SN/A loadQueue[load_idx]->squashed = true; 6992292SN/A loadQueue[load_idx] = NULL; 7002292SN/A --loads; 7012292SN/A 7022292SN/A // Inefficient! 7032292SN/A loadTail = load_idx; 7042292SN/A 7052292SN/A decrLdIdx(load_idx); 7062292SN/A } 7072292SN/A 7082292SN/A if (isLoadBlocked) { 7092292SN/A if (squashed_num < blockedLoadSeqNum) { 7102292SN/A isLoadBlocked = false; 7112292SN/A loadBlockedHandled = false; 7122292SN/A blockedLoadSeqNum = 0; 7132292SN/A } 7142292SN/A } 7152292SN/A 7162292SN/A int store_idx = storeTail; 7172292SN/A decrStIdx(store_idx); 7182292SN/A 7192292SN/A while (stores != 0 && 7202292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 7212329SN/A // Instructions marked as can WB are already committed. 7222292SN/A if (storeQueue[store_idx].canWB) { 7232292SN/A break; 7242292SN/A } 7252292SN/A 7262292SN/A DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, " 7272292SN/A "idx:%i [sn:%lli]\n", 7282292SN/A storeQueue[store_idx].inst->readPC(), 7292292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 7302292SN/A 7312329SN/A // I don't think this can happen. It should have been cleared 7322329SN/A // by the stalling load. 7332292SN/A if (isStalled() && 7342292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 7352292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 7362292SN/A stalled = false; 7372292SN/A stallingStoreIsn = 0; 7382292SN/A } 7392292SN/A 7402329SN/A // Clear the smart pointer to make sure it is decremented. 7412292SN/A storeQueue[store_idx].inst->squashed = true; 7422292SN/A storeQueue[store_idx].inst = NULL; 7432292SN/A storeQueue[store_idx].canWB = 0; 7442292SN/A 7452292SN/A storeQueue[store_idx].req = NULL; 7462292SN/A --stores; 7472292SN/A 7482292SN/A // Inefficient! 7492292SN/A storeTail = store_idx; 7502292SN/A 7512292SN/A decrStIdx(store_idx); 7522292SN/A } 7532292SN/A} 7542292SN/A 7552292SN/Atemplate <class Impl> 7562292SN/Avoid 7572678Sktlim@umich.eduLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 7582678Sktlim@umich.edu{ 7592678Sktlim@umich.edu iewStage->wakeCPU(); 7602678Sktlim@umich.edu 7612678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 7622678Sktlim@umich.edu if (inst->isSquashed()) { 7632678Sktlim@umich.edu assert(!inst->isStore()); 7642678Sktlim@umich.edu return; 7652678Sktlim@umich.edu } 7662678Sktlim@umich.edu 7672678Sktlim@umich.edu if (!inst->isExecuted()) { 7682678Sktlim@umich.edu inst->setExecuted(); 7692678Sktlim@umich.edu 7702678Sktlim@umich.edu // Complete access to copy data to proper place. 7712678Sktlim@umich.edu inst->completeAcc(pkt); 7722678Sktlim@umich.edu } 7732678Sktlim@umich.edu 7742678Sktlim@umich.edu // Need to insert instruction into queue to commit 7752678Sktlim@umich.edu iewStage->instToCommit(inst); 7762678Sktlim@umich.edu 7772678Sktlim@umich.edu iewStage->activityThisCycle(); 7782678Sktlim@umich.edu} 7792678Sktlim@umich.edu 7802678Sktlim@umich.edutemplate <class Impl> 7812678Sktlim@umich.eduvoid 7822292SN/ALSQUnit<Impl>::completeStore(int store_idx) 7832292SN/A{ 7842292SN/A assert(storeQueue[store_idx].inst); 7852292SN/A storeQueue[store_idx].completed = true; 7862292SN/A --storesToWB; 7872292SN/A // A bit conservative because a store completion may not free up entries, 7882292SN/A // but hopefully avoids two store completions in one cycle from making 7892292SN/A // the CPU tick twice. 7902292SN/A cpu->activityThisCycle(); 7912292SN/A 7922292SN/A if (store_idx == storeHead) { 7932292SN/A do { 7942292SN/A incrStIdx(storeHead); 7952292SN/A 7962292SN/A --stores; 7972292SN/A } while (storeQueue[storeHead].completed && 7982292SN/A storeHead != storeTail); 7992292SN/A 8002292SN/A iewStage->updateLSQNextCycle = true; 8012292SN/A } 8022292SN/A 8032329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 8042329SN/A "idx:%i\n", 8052329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 8062292SN/A 8072292SN/A if (isStalled() && 8082292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 8092292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 8102292SN/A "load idx:%i\n", 8112292SN/A stallingStoreIsn, stallingLoadIdx); 8122292SN/A stalled = false; 8132292SN/A stallingStoreIsn = 0; 8142292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 8152292SN/A } 8162316SN/A 8172316SN/A storeQueue[store_idx].inst->setCompleted(); 8182329SN/A 8192329SN/A // Tell the checker we've completed this instruction. Some stores 8202329SN/A // may get reported twice to the checker, but the checker can 8212329SN/A // handle that case. 8222316SN/A if (cpu->checker) { 8232316SN/A cpu->checker->tick(storeQueue[store_idx].inst); 8242316SN/A } 8252292SN/A} 8262292SN/A 8272292SN/Atemplate <class Impl> 8282292SN/Ainline void 8292292SN/ALSQUnit<Impl>::incrStIdx(int &store_idx) 8302292SN/A{ 8312292SN/A if (++store_idx >= SQEntries) 8322292SN/A store_idx = 0; 8332292SN/A} 8342292SN/A 8352292SN/Atemplate <class Impl> 8362292SN/Ainline void 8372292SN/ALSQUnit<Impl>::decrStIdx(int &store_idx) 8382292SN/A{ 8392292SN/A if (--store_idx < 0) 8402292SN/A store_idx += SQEntries; 8412292SN/A} 8422292SN/A 8432292SN/Atemplate <class Impl> 8442292SN/Ainline void 8452292SN/ALSQUnit<Impl>::incrLdIdx(int &load_idx) 8462292SN/A{ 8472292SN/A if (++load_idx >= LQEntries) 8482292SN/A load_idx = 0; 8492292SN/A} 8502292SN/A 8512292SN/Atemplate <class Impl> 8522292SN/Ainline void 8532292SN/ALSQUnit<Impl>::decrLdIdx(int &load_idx) 8542292SN/A{ 8552292SN/A if (--load_idx < 0) 8562292SN/A load_idx += LQEntries; 8572292SN/A} 8582329SN/A 8592329SN/Atemplate <class Impl> 8602329SN/Avoid 8612329SN/ALSQUnit<Impl>::dumpInsts() 8622329SN/A{ 8632329SN/A cprintf("Load store queue: Dumping instructions.\n"); 8642329SN/A cprintf("Load queue size: %i\n", loads); 8652329SN/A cprintf("Load queue: "); 8662329SN/A 8672329SN/A int load_idx = loadHead; 8682329SN/A 8692329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 8702329SN/A cprintf("%#x ", loadQueue[load_idx]->readPC()); 8712329SN/A 8722329SN/A incrLdIdx(load_idx); 8732329SN/A } 8742329SN/A 8752329SN/A cprintf("Store queue size: %i\n", stores); 8762329SN/A cprintf("Store queue: "); 8772329SN/A 8782329SN/A int store_idx = storeHead; 8792329SN/A 8802329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 8812329SN/A cprintf("%#x ", storeQueue[store_idx].inst->readPC()); 8822329SN/A 8832329SN/A incrStIdx(store_idx); 8842329SN/A } 8852329SN/A 8862329SN/A cprintf("\n"); 8872329SN/A} 888